KR100227269B1 - Semiconductor memory device - Google Patents

Abstract

The present invention discloses a semiconductor memory device. The apparatus comprises a plurality of banks arranged in a stack having a plurality of memory cell arrays, connected between a wide area column select line and a ground voltage and connected to a local column select line of each bank of the plurality of banks in response to each bank control signal. A plurality of local column select line driving means for outputting a column select control signal, a column decoder disposed in each of the plurality of banks to generate a wide column select signal with the wide column select lines, and a plurality of the plurality of banks And a plurality of column selection means connected between the bit line pair and the input / output line pair of each array of the two memory cell arrays and for connecting the bit line pair and the input / output line pair in response to the column selection control signal. Therefore, the chip area can be reduced.

Description

Semiconductor memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly, to a column selection circuit and a driving circuit of a semiconductor memory device.

There is a need for a structure in which a global column select line and a local column select line are used together in a method of selecting a column address in a high speed memory device having a multi bank and having a stack structure. Wide column select lines are used across the banks in the longitudinal direction and local column select lines are divided into banks for use in each bank only.

FIG. 1 illustrates an arrangement of a conventional semiconductor memory device, and illustrates a memory device having a 4-bank structure, in which four banks bank0-bank3 are arranged in left and right directions, and a row line is provided between the left and right banks. A row control circuit for controlling the circuit is located and a column control circuit, an interface, and an input / output buffer are arranged under the banks bank0 -bank3.

Each bank is arranged with 16 arrays, 4 horizontally and 4 vertically, and 20 sense amplifiers are arranged between the horizontal arrays and at the outermost sides. The banks shown in Fig. 1 are respectively arranged on the left and right sides equally.

Fig. 2 shows an arrangement of sense amplifiers and circuits of column select lines and column drive circuits of a conventional semiconductor memory device, in which an equalization circuit EQ for equalizing a pair of bit lines, the operation of an array arranged on the left and right sides, Isolation circuit (ISO) for controlling the signal, sense amplifiers (PSA, NSA) for amplifying and outputting data from bit line pairs, and data from bit line pairs (BL, BLB). Column select line and input / output line pairs CSL & IO to which a signal for controlling a column select transistor for transmission is applied are arranged between the bit line pairs BL and BLB. One column decoder, one for each bank, is a circuit that decodes the column address, and the signal decoded by the circuit is transmitted through four banks of wide column select lines (GCSL) regardless of the bank. The sense amplifiers are placed coincident in the direction of the arrow in the figure.

The conventional column select line and input / output line pairs CSL & IO are turned on in response to a signal applied through the local column select line LCSL to connect the bit line pairs BL and BLB and the input / output line pairs IO and IOB. The column select transistors N1 and N2, and the local column select line LCSL connected in series between the wide column select line GCSL and the ground voltage VSS and turned on in response to the signals Y and YB, respectively. And column driving transistors N3 and N4 for outputting a column selection signal.

If the signal Y is at the "high" level, the NMOS transistor N3 is turned on and the NMOS transistor N4 is turned off so that the signal from the wide area column select line GCSL is applied to the local column select line LCSL to select a column. The transistors N1 and N2 are controlled. When the signal Y is at the "low" level, the NMOS transistor N3 is turned off, the NMOS transistor N4 is turned on, and a ground voltage is applied to the local column select line LCSL to turn off the column select transistors N1 and N2. do.

The signal output to the local column select line LCSL is an output signal of the column drive circuit and is a signal enabled in response to a signal transmitted through the wide column select line GCSL. That is, in the above-described conventional semiconductor memory device, the local column select line driving circuits are all located in the respective sense amplifier regions, which use the same wide column select line and are controlled by the respective bank information (Y, YB). The column select line driver circuit in the sense amplifier region is not easy to layout, so the local column select line driver circuit occupies an area of 20.65 μm in the bit line direction. This means that if 5 sense amplifiers are used per bank as shown in Fig. 1, 20 of the total sense amplifiers are required, and thus the area occupied by the column select line driving circuit is 413 mu m.

That is, the above-described column driving circuits of the conventional semiconductor memory device are provided in each bank, and the control signals are generated by the local column select line. Therefore, it is intended to design more efficiently by taking advantage of the fact that the wide-area heat selection lines of each bank are commonly used.

An object of the present invention is to provide a semiconductor memory device that can reduce the chip area by designing the column select line driving circuit more efficiently.

The semiconductor memory device of the present invention for achieving the above object is a plurality of banks configured in a stack type having a plurality of memory cell arrays, connected between a wide area column select line and a ground voltage and the plurality of banks in response to each bank control signal. A plurality of local column select line driving means for outputting a column select control signal to a local column select line of each bank of the plurality of banks, disposed in each of the plurality of banks to generate a wide column select signal with the wide column select lines A plurality of column decoders connected between the bit line pairs and the input / output line pairs of each array of the plurality of memory cell arrays of the plurality of banks, and for connecting the bit line pairs to the input / output line pairs in response to the column selection control signal. Characterized in that the column selection means.

1 shows an arrangement of a conventional semiconductor memory device.

Fig. 2 shows an arrangement, a column selection circuit, and a driving circuit of a sense amplifier in a conventional semiconductor memory device.

Fig. 3 shows the arrangement, the column selection circuit and the driving circuit of the sense amplifier in the semiconductor memory device of the present invention.

Hereinafter, a semiconductor memory device of the present invention will be described with reference to the accompanying drawings.

Fig. 3 shows the arrangement of the sense amplifiers and the circuits of the column select lines and the column drive circuits of the semiconductor memory device of the present invention, each bank having four arrays arranged in the transverse direction and between the arrays and the outermost sense amplifiers. Is arranged. And a column select drive circuit and a column decoder are arranged to control the array and the sense amplifier. Each sense amplifier includes an equalization circuit EQ for equalizing the bit line pairs, a separation circuit ISO for controlling the operation of the array arranged on the left and right sides, and a sense amplifier for amplifying and outputting data from the bit line pairs. Column select line and I / O line pair (CSL & IO) to which a signal for controlling a column select transistor for transferring data from PSA, NSA) and bit line pair BL, BLB to I / O line pair IO, IOB is applied. ) Is arranged between the bit line pairs BL and BLB. One column decoder, one for each bank, is a circuit that decodes the column address, and the signal decoded by the circuit is transmitted through four banks of wide column select lines (GCSL) regardless of the bank. The sense amplifiers are placed coincident in the direction of the arrow in the figure.

The column select transistor is turned on in response to a signal applied from the local column select line LCSL, and NMOS transistors N1 and N2 for connecting the input / output line pairs IO and IOB and the bit line pairs BL and BLB, respectively. ), And the wide column select lines GCSL and the bit line pairs are arranged in parallel.

In addition, the column select line driving circuit is connected in series between the wide column select line GCSL and the ground voltage VSS and is turned on in response to the bank control signals Y and YB, respectively, and is transmitted from the wide column select line GCSL. NMOS transistors (N3, N4) for transmitting the signal to the local column select line (LCSL) or the ground voltage (VSS) to the local column select line (LCSL), the wide column select line (GCSL) The local column select line LCSL and the ground voltage applying line VSS are arranged in parallel.

That is, in the present invention, since each bank shares a wide range column select line, only one column select line driving circuit is required for each bank.

In the conventional semiconductor memory device, a wide line selection line-a ground voltage applying line-a wide line selection line-a ground voltage applying line, which are lines required for the entire bank, are alternately arranged. However, the semiconductor memory device of the present invention is arranged in the order of a wide heat select line, a local heat select line, a ground voltage apply line, a local heat select line, a wide heat select line, and a wide heat select line, which are necessary lines for the entire bank. It becomes usable.

According to the structure of the present invention, since the column select line driver circuits need only one for each bank, that is, four column select line driver circuits, if one column select line driver circuit occupies an area of 23.45 μm, the total area of the present invention is 93.8 μm. Therefore, compared with the conventional semiconductor memory device, the area of 319.2 μm can be reduced.

Therefore, the semiconductor memory device of the present invention can reduce the chip area by designing the column select line driver circuit efficiently.

Claims (4)

A plurality of banks configured in a stack type having a plurality of memory cell arrays; A plurality of local column select line driving means connected between a wide area column select line and a ground voltage and outputting a column select control signal to a local column select line of each bank of the plurality of banks in response to each bank control signal; A column decoder disposed in each of the plurality of banks to generate a wide range column selection signal with the wide range column selection lines; A plurality of column selecting means connected between the bit line pair and the input / output line pair of each array of the plurality of memory cell arrays of the plurality of banks and connecting the bit line pair and the input / output line pair in response to the column selection control signal. The semiconductor memory device characterized by the above-mentioned. The semiconductor memory according to claim 1, wherein lines are arranged in the order of the wide column selection line, the local column selection line, the ground voltage applying line, the local column selection line, and the wide region column selection line in the longitudinal direction of the banks. Device. 2. The NMOS of claim 1, wherein the column driving means is connected in series between the wide-range heat selection line and the ground voltage applying line and generates the column selection control signal to the local column selection line in response to the bank control signal. A semiconductor memory device comprising a transistor. 2. The NMOS transistor according to claim 1, wherein the column selector is connected between the bit line pair and the input / output line pair, respectively, and couples two NMOS transistors for connecting the bit line pair and the input / output line pair respectively in response to the local column select signal. A semiconductor memory device comprising:

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