JPH04170271A - Clamp circuit - Google Patents

Abstract

PURPOSE:To reduce a response time of clamping by providing a low pass filter through which a clamp pulse is generated even for a vertical blanking erasure period and which comprises a capacitor between a signal line and a power supply and between the signal line and ground respectively to the clamp circuit. CONSTITUTION:It is noticed that a level of signals other than a horizontal synchronizing signal and an equalizing pulse is at a pedestal level for a vertical blanking period, a clamp pulse is generated even when the equalizing pulse exists for the vertical blanking period to widen its pulse width. As a result, the settling of the clamp level is quickened, and for example, even for a period of one clamp pulse, the clamp level is quickly settled. Thus, a response time till the clamp level is settled is reduced at application of power and at signal input. Moreover, a capacitor whose capacitance is a half of a capacitance of a conventional capacitance is connected to both a power supply side and a ground side in this LPF. Thus, although the filter characteristic is the same but the time constant is halved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a clamp circuit, and more particularly to a digital feedback type clamp circuit.

[Prior Art] Generally, when analog signals are processed into digital signals,
In order to obtain stable and accurate digital signal power, A/
It is necessary to clamp the analog signal input before D conversion. Although there are various clamping methods, digital feedback clamping is known as a clamping method that is less susceptible to temperature drift and power supply voltage fluctuations and can obtain stable digital signal input.

FIG. 2 shows the basic configuration of a digital feedback clamp circuit in a digital signal processing circuit for analog video signals. 10 is an analog video signal input terminal; 1
2 is an A/D converter, 14 is a latch circuit that latches the output data of the A/D converter 12 with a clock having the same timing as the sampling clock of the A/D converter 12, and 16 is a latch circuit that latches the output data of the latch circuit 14. a certain reference value, e.g. 0
1h (decimal number); 18 is a clamp gate circuit that enters a pass state during the period of a clamp pulse 26 to be described later; 20 is a circuit that removes digital noise contained in the output of the clamp gate circuit 18; 22 is a buffer, 2 is a low-pass filter (L P F ) for
4 is a clamp closed by a clamp pulse 26.
It's a switch.

28 is a memory for storing output data of the latch circuit 14;
30 is a D/A converter that converts the image data read from the memory 28 into an analog signal, and 32 is an output terminal for a video signal digitally processed on the memory 28 by a digital arithmetic processing circuit (not shown). Since the processing on the memory 28 is unrelated to the present invention, a description thereof will be omitted.

FIG. 3 shows the timing of clamp pulse 26 relative to the luminance signal. The clamp pulse 26 is applied to the clamp switch 24 at a timing and width that captures the timing of the pedestal level of the luminance signal, ie, the period of the back porch of the horizontal synchronization signal. Also, Figure 4 shows L P
The circuit configuration of F20 is shown. LPF20 is a well-known RC
It is a circuit.

The operation shown in FIG. 2 will be briefly explained. The analog video signal input to the input terminal 10 is digitized by the A/D converter 12 and then applied to the comparison circuit 16 via the latch circuit 14. The comparison circuit 16 compares the output value of the latch circuit 14 with the reference value 01h, and the output value of the latch circuit 14 becomes OOh.
When the output of the comparison circuit 16 becomes "H" and the clamp level is raised, and when the output of the latch circuit 14 is Olh, the output J impedance becomes high and the clamp level at that point is maintained, and the latch circuit When the output of the comparator circuit 14 is 02h or more, the output of the comparator circuit 16 becomes °°L'' and lowers the clamp level.The clamp gate circuit 18 applies the output of the comparator circuit 16 to the LPF 20 at the timing of the clamp pulse 26. I-P F20 is a digital
Removes noise and outputs a stable DC level signal. The output of the LPF 20 is sent to the switch 2 via the buffer 22.
4 and switch 2 by clamp pulse 26
4, the analog video signal at the input terminal 10 is clamped. In this way, the pedestal level of the analog video signal input to the input terminal 10 is maintained at a predetermined constant level, and stable clamping is performed.

[Problems to be Solved by the Invention] However, in the above conventional example, in order to ensure the S/N ratio of the signal, it is necessary to increase the capacitor capacity of the LPF 20 (Fig. 4) to a certain extent, and as a result, the capacitor capacity of the LPF 20 The drawback is that the time constant becomes large, and it takes a long time for the clamp signal to stabilize when inputting a signal or turning on the power, resulting in poor response.

An object of the present invention is to provide a clamp circuit that solves these problems.

[Means for Solving the Problems] The clamp circuit according to the present invention is a feedback type clamp circuit that clamps a video signal, and vertically blanks the clamp pulse that turns on the clamp switch means in the feedback path. It is characterized in that it also occurs during the period. In addition, a low-pass filter is provided for the clamp level signal by connecting a capacitor between the signal line and the power supply, and between the signal line and the ground, and the capacitor connected between the signal line and the power supply , the capacitance ratio of the capacitor connected between the signal line and the ground, and the voltage applied to the series circuit of both capacitors, to a value that matches or approximates the clamp level at which the filter output finally stabilizes when the power is turned on. It is preferable to set it to .

[Operation] By generating a clamp pulse also during the vertical retrace period, the clamp level can be stabilized more quickly. Further, by configuring the low-pass filter as described above, the time constant can be reduced to 1/2 while the filter characteristics remain unchanged, and the clamp level can be stabilized quickly. Therefore, by one or both of the above means,
Clamp response time can be significantly reduced.

[Example] Hereinafter, the present invention will be described in detail with reference to the drawings.

The basic configuration of the first embodiment of the present invention is conceptually the same as that in FIG. 2, but the timing of the clamp pulse is different. FIG. 1 shows a timing diagram of the clamp pulse in this embodiment. FIG. 1(a) shows a video signal to be clamped, FIG. 1(b) shows a normal pedestal clamp pulse used in the conventional example, and FIG. 1(C) shows a clamp pulse in this embodiment.

As can be seen from FIG. 1(b), in the conventional example, the clamp pulse is an extremely short pulse of approximately 0.044I ((IH is one horizontal scanning period) at the timing to capture the back porch of the horizontal synchronization signal. , and does not occur during the vertical blanking period.

Thus, not only does the short pulse width of the clamp pulse cause a significantly longer time to obtain a stable clamp, but the absence of a clamp pulse during the vertical blanking period also reduces the The clamp is not stabilized before the image is applied to the image area, and therefore, it is necessary to wait for a period corresponding to one screen to be captured into the memory 28.

On the other hand, in this embodiment, we focus on the fact that in the vertical blanking period, signals other than the horizontal synchronizing signal and the equalization pulse are at the pedestal level, and as shown in FIG. 1(C), the vertical blanking period is A clamp pulse was also generated between the equalization pulses, and the pulse width was widened. By doing this, the clamp level is stabilized more quickly, and for example, even within the period of one clamp pulse, the clamp level is stabilized more quickly than in the conventional example. Therefore, the response time T until the clamp level stabilizes when the power is turned on or when a signal is input is shortened.

When the power supply of the digital circuit is Vcc, the clamp voltage that finally stabilizes is Vc, the vertical scanning period is Tv, and the clamp time during the vertical scanning period is Tc, the response time T is given by the following formula.

T=-1n(1-Vc/Vcc)XCXRXTv/Tc
(1) Here, CxR is the time constant of the LPF 20.

In order to shorten the response time T, as can be seen from equation (1), the clamp width must be widened and the LPF20
It is effective to reduce the time constant of

Therefore, the present invention also proposes to use the LPF shown in FIG. 5 instead of the LPF shown in FIG. In the LPF shown in FIG. 5, a capacitor with half the capacity is connected to both the power supply side and the ground side, so that the filter characteristics are the same as those in FIG. 4, but the time constant is halved.

Furthermore, in the LPF shown in FIG. 5, the filter output becomes 1/2 of the power supply voltage (2.5 [V] when the power supply voltage Vcc is, for example, 5 [■]) immediately after the power is turned on. By matching this DC level with the final stabilized clamp level and giving an offset level to the clamp level before inputting it to the A/D converter, the response at signal input and power-on can be improved. You can hasten it. An example of the circuit is shown in FIG.

In FIG. 6, 40 is a clamp pulse input terminal;
42 is an input terminal for a clamp level signal (for example, the output of the gate circuit 18), 44 is an input terminal for an analog video signal, 46 is an LPF having the same circuit configuration as in FIG. 5, and 48 is a clamp level signal corresponding to the clamp switch 24. switch, 50
52 is a buffer transistor, and 52 is an output terminal connected to an A/D converter.

For example, if the operating range of the input DC level of the A/D converter used is 0.6 to 2.5 [V], and the pedestal level is set to the lowest operating level of the A/D converter, the The pedestal potential at point 0 in Figure 6 is 0.6 [V]
Therefore, at point B, approximately 1.2 [V],
At point A, the voltage is approximately 2.4 [V]. A immediately after turning on the power.
Since the potential at the point is 2.5 [V], the time it takes for the signal level at the output terminal 52 to stabilize is quite quick.

In this way, the response time T when an offset is given in advance is given by the following equation.

T=-1n(1-Vc/(Vcc-Vo)IXc/2X
RXTv/Tc...Vo<Vc (2) T = -1n(Vc/Vo) X C/2x RX T
v/Tc...Vo>Vc (3) However, VC is the clamp level that finally stabilizes, Vc
c is a power supply voltage (for example, 5 [V]), Vo is an offset voltage (2.5 [V] in this example), the vertical scanning period is Tv, and the clamp time during the vertical scanning period is Tc.

When Vo<Vc, the signal corresponding to the output of the comparator circuit 16 in FIG. 2 becomes "H", and the signal from the input terminal 42 in FIG.
A clamp level signal of 5 [V] is supplied to the PF 46 during the clamp pulse period, and the capacitor of the LPF 46 is charged. Conversely, when ■0>Vc, the signal corresponding to the output of the comparator circuit 16 in FIG.
A clamp level signal of O [V] is supplied from the input terminal 42 to the LPF 46 during the clamp pulse period, and
The capacitor of I and PF46 is discharged and stabilized at Vc.

When Vo=Vc, that is, when the offset voltage and the eventually stabilized clamp voltage are equal, the response time T becomes 0 seconds, and even if they are not equal, as the difference between vO and Vc becomes smaller, Response time T logarithmically
becomes shorter.

By using the configuration described in FIGS. 1, 5, and 6, for example, when digitizing an analog video signal from the beginning of the vertical blanking period and writing it into memory, it is possible to Once the clamp level is stabilized, the portion of the video following the vertical blanking period can be written to memory, allowing subsequent video processing to occur more quickly.

Next, a case where the present invention is applied to a processing circuit for color difference line sequential signals in a still video camera will be described.

In still video cameras, for color difference signals, I
A color difference line sequential signal obtained by alternately switching color difference components R-Y and B-Y every H (horizontal scanning period) is FM-modulated and recorded on a magnetic disk. In the color difference line sequential signal, an offset corresponding to 100 KHz is provided between the color difference components R-Y and B-Y.

When performing digital video signal processing on such a color difference line sequential signal, first, the signal from which the offset has been removed is digitized and written into a memory, and upon digitization, ramping is performed as described above. The present invention can also be applied to this clamp circuit.

That is, a wide clamp pulse is applied within the vertical blanking period even to the color difference line sequential signal from which the offset has been removed. This speeds up the stabilization of the clamp level. In addition, the LF shown in FIG.
By adopting P, the time constant can be halved without changing the filter effect, and the clamp level can be stabilized even faster.

Furthermore, if the circuit configuration shown in Fig. 6 is adopted, since the color difference line sequential signal is clamped at the center level, for example, an A/D converter with an operating DC range of 06 to 26 [■] can be used. Then, the center 1, 6 [V]
If we clamp it to
[V], therefore the potential at point B is approximately 2.2 [V],
The potential at point A is approximately 2.8 [V]. L P F
Assuming that C-22μF and R=470Ω in 46, the response time T=0.12m5 and becomes stable at 2H. Therefore, when digitizing from the beginning of the vertical blanking period, the clamp level is stabilized within two horizontal scanning periods, and subsequent digital video signals can be written into the memory.

[Effects of the Invention] As can be easily understood from the above explanation, according to the present invention, the clamp level is stabilized more quickly, and therefore the original video signal processing can be started sooner when the power is turned on or when a signal is input. become able to.

[Brief explanation of the drawing]

FIG. 1 is a timing diagram in one embodiment of the present invention, and FIG.
The figure is a basic configuration diagram of a digital feedback type clamp circuit, Figure 3 is a timing diagram in a conventional example, Figure 4 is a circuit configuration of an LPF 20 in a conventional example, Figure 5 is a circuit example of an LPF according to the present invention, and Figure 6 is a circuit diagram of a partial circuit in another embodiment of the present invention. 10: Analog video signal input terminal 12: A/D converter 14: Latch circuit 16: Comparison circuit 18: Clamp gate circuit 20: Low-pass filter 22:
Buffer 24: Clamp switch 26; Clamp pulse 28: Memory 30: D/A converter 32
: Output terminal 40, 42.44: Input terminal 46: LP
F 48: Clamp switch 50. Buffer transistor 52: output terminal

Claims (3)

[Claims] (1) A feedback type clamp circuit for clamping a video signal, which is characterized in that it generates a clamp pulse for turning on a clamp switch means in a feedback path also during the vertical blanking period. (2) A clamp circuit characterized in that a low-pass filter is provided for the clamp level signal by connecting a capacitor between the signal line and the power supply and between the signal line and the ground. (3) The capacitance ratio of the capacitor connected between the signal line and the power supply and the capacitor connected between the signal line and the ground, and the voltage applied to the series circuit of both capacitors, will eventually stabilize the filter output when the power is turned on. The clamp circuit according to claim 2, wherein the clamp circuit is set to a value that matches or approximates a clamp level.