JPH04170061A - Manufacture of semiconductor memory device - Google Patents

Abstract

PURPOSE:To facilitate increase of the storage capacity of a capacitor dielectric film by a method wherein solid phase reaction between Al and silicon is utilized in order to make the surface of a polycrystalline silicon film uneven. CONSTITUTION:An Al film 8 is formed on a polycrystalline silicon film 7 which is to be a storage electrode. The Al film 8 is subjected to a thermal treatment to have silicon melted into A and an unevenness is formed along the boundary between the Al film 8 and the polycrystalline silicon film 7. Then the Al film 8 is removed by etching and a dielectric film 9 is formed on the uneven polycrystalline silicon film 7 and, further, a polycrystalline silicon film 10 which is to be a cell plate is formed on the dielectric film 9. With this constitution, a capacitor having a storage electrode which has an enlarged effective area and is suitable for a batch treatment can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a semiconductor memory device, and particularly to a method of manufacturing a capacitor for a dynamic random access memory (DRAM).

(Prior Art) Conventionally, as a method of increasing the storage capacity without thinning the capacitor dielectric film of a DRAM, there is a method of increasing the surface area by providing unevenness on the electrode surface. As a method of making the polysilicon surface, which will become the storage electrode of the canopy, uneven, the surface is made uneven by controlling the polysilicon formation temperature using low pressure CVD (chemical vapor deposition) using SiH4 gas as a raw material. How to make it uneven is the Proceedings of the 37th Spring 1990 Conference of the Japan Society of Applied Physics, P.
, 58329a-8B-4r Stacked carrier A using rough polysilicon film? Jitter Formation”. According to this, S s H4 as a storage electrode
570℃~640℃ using low pressure CVD method using gas as raw material
A polysilicon film that will become a storage electrode is formed at 5°C.
As the crystallinity changes from polycrystalline to amorphous at 80° C. or lower, irregularities are formed on the surface of the polysilicon film.

(Problem to be Solved by the Invention) However, in the conventional method as described above, the temperature range at which unevenness is formed on the surface of the polysilicon film serving as the storage electrode is an extremely narrow range at which the crystallinity of the polysilicon changes. However, there is a problem in that temperature control is difficult and unevenness cannot be easily formed.In addition, when actually forming polysilicon, in order to control the amount of gas reaction, the temperature distribution must be such that the reaction occurs evenly over the length of the reactor. However, since the furnace length is short enough to maintain the reaction gas conditions and temperature conditions that can form unevenness on the surface of the polysilicon film, the throughput is approximately 20 sheets per batch (approximately 2 hours). Very low.

There is a problem in that this throughput is inferior to the practical value of 50 sheets or more per patch from the viewpoint of mass production.

(Means for Solving the Problems) In order to solve the above problems and easily form unevenness, the present invention provides an A
I! A step of forming a film, a step of heat-treating this At film and melting silicon during AJ to form irregularities at the interface between the AJ film and polysilicon, a step of etching away this AJ film, and a step of removing the dielectric film. This is a method of manufacturing a semiconductor memory device, comprising the steps of forming a film on the polysilicon having irregularities, and forming polysilicon that will become a cell plate on the dielectric film.

(Function) The polysilicon that becomes the storage electrode undergoes AJ by heat treatment.
Melting into a film creates irregularities on the polysilicon. Furthermore, silicon nodules are deposited on the polysilicon surface during the cooling process after the heat treatment. These silicon nodules also cause unevenness.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the process sectional views shown in FIGS. 1(a) to 1(c) and the interfacial reaction model diagram shown in FIG. 1(d).

As shown in the cross-sectional view of FIG. 1, a thick field oxide film 2 is first selectively formed on the surface of a silicon substrate 1 by the Locos method.

Next, a date oxide film 3 is formed, and then polysilicon 4 for forming a gate electrode is formed on the entire surface, and is doped with phosphorus V using POC/3 as a diffusion source to make it conductive. next,
4. Dart electrode by normal photolithography and etching. The date oxide film 3 is shaped. Here, a source region 6c and a drain region 6d having a low concentration are provided by ion implantation.

Thereafter, a sidewall 5 is formed on the side wall of the dirt electrode 4, and using this sidewall 5 and the Y-t electrode 4 as a mask, a high concentration source region 6a and a drain region 6 are formed in predetermined regions.
b.

The steps up to this point are normal.

Next, as shown in FIG. 1(b), polysilicon 7 that will become a storage electrode is grown for about 1,000 years using the low-pressure CVD method, and phosphorus is doped into this polysilicon 7 using POC7!3 as a diffusion source to make it conductive. to have. On this polysilicon 7, 50 AJ s was applied using a sputtering method.
The polysilicon 7 is deposited at a temperature of about 0.times.0.degree. This situation will be explained using FIG. 2 AJ and a model diagram of solid phase reaction of polysilicon. FIG. 2(a) is a cross-sectional view when AJ & is deposited on polysilicon 7. FIG. Next, FIG. 2(b) shows a cross-sectional view after heat treatment. Since the solid phase reaction between polysilicon 7 and Aps occurs first from grain boundary portions 11 of relatively low energy in polysilicon 7, the interface between AJ 8 and polysilicon 7 does not react uniformly, resulting in unevenness. In addition, part of the polysilicon 7 melted during A2B is removed from the polysilicon 2 during the cooling process after the heat treatment.
The silicon nodules 12 are deposited on the surface. This silicon nodule 12 also causes polysilicon 7
Creates unevenness on the surface. Figure 3 shows an SEM (scanning electron microscope) of the surface of polysilicon 7 when AJ 8 was deposited on polysilicon 7, heat treated at 45°C for 20 minutes in a nitrogen atmosphere, and then Al& was removed with sulfuric acid. )
A reproduction of the photograph is shown. From this figure, it can be seen that irregularities are formed on the surface of the polysilicon 7. According to experiments 3
A similar shape can be obtained in the region of 80°C to 500°C.

After removing AlB by sulfurization, a dielectric film such as a silicon nitride film 9. is formed on the polysilicon 7 as shown in FIG. 1(c). Polysilicon 11, which will become a cell plate, is successively formed thereon, and then polysilicon 7, silicon nitride film 9. polysilicon 1
0 into the required shape to form the main part of the capacitor. The subsequent steps are the same as the normal cano mat production process.

(Effects of the Invention) According to the present invention, since the solid phase reaction between AJ and silicon is used to make the surface of the polysilicon film uneven, the effective area can be easily increased due to the advantage that the reaction temperature range can be widened. - A capacitor having a storage electrode that can be easily processed in batches can be manufactured.

[Brief explanation of the drawing]

FIGS. 1(a)-(c) are process cross-sectional views in an embodiment of the present invention. FIGS. 2(a) and 2(b) are model diagrams of an in-phase reaction between l' and silicon in an example of the present invention. FIG. 3 is a replica of a SEM photograph of the first polysilicon surface after AJ has been removed after the solid phase reaction between AJ and silicon in an example of the present invention. 1... Silicon substrate, 2... Field oxide film, 3
... Dirt oxide film, 4... r-) electrode, 5... Side wall s 6a p 6e... Source region, 6
b, 6d...Drain region, 7...First polysilicon, 8...AI. 9... Silicon nitride film, 10... Second polysilicon. 11...Polysilicon grain boundaries, 12...Silicon Noju patent applicant Oki Electric Industry Co., Ltd. Eρ model diagram Figure 2

Claims (1)

[Claims] A step of forming an Al film on a first polysilicon serving as a storage electrode, and heat-treating the first polysilicon and the Al film to form the A
making the interface between the Al film and the first polysilicon uneven by melting silicon in the Al film; removing the Al film by etching; A method for manufacturing a semiconductor memory device, comprising: forming a dielectric film on silicon; and forming a second polysilicon serving as a cell plate on the dielectric film.