JPH04170037A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH04170037A JPH04170037A JP2296594A JP29659490A JPH04170037A JP H04170037 A JPH04170037 A JP H04170037A JP 2296594 A JP2296594 A JP 2296594A JP 29659490 A JP29659490 A JP 29659490A JP H04170037 A JPH04170037 A JP H04170037A
- Authority
- JP
- Japan
- Prior art keywords
- connection conductor
- stress
- connecting conductor
- stress absorbing
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 239000004020 conductor Substances 0.000 claims abstract description 29
- 230000007704 transition Effects 0.000 claims description 9
- 230000035882 stress Effects 0.000 abstract description 19
- 229910000679 solder Inorganic materials 0.000 abstract description 10
- 230000008646 thermal stress Effects 0.000 abstract description 5
- 238000005336 cracking Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 229910000831 Steel Inorganic materials 0.000 description 1
- 230000002745 absorbent Effects 0.000 description 1
- 239000002250 absorbent Substances 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/4005—Shape
- H01L2224/4009—Loop shape
- H01L2224/40091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/4005—Shape
- H01L2224/4009—Loop shape
- H01L2224/40095—Kinked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
- H01L2224/848—Bonding techniques
- H01L2224/84801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、パワートランジスタモジュールなどを対象と
した半導体装置、特にその内部配線の構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device such as a power transistor module, and particularly to the structure of internal wiring thereof.
(従来の技術)
まず、第3図に本発明の実施対象となる半導体装置の従
来構成を示す0図において、lはプリント配線板、2は
プリント配線板1の回路パターン、3は回路パターン2
に例えば半田付けしてマウントしたトランジスタ、ダイ
オードなどの半導体素子、4は半導体素子3の相互間、
あるいは半導体素子3と図示されてない他の回路部品と
の間にまたがって内部配線した接続導体、5は半田接合
部である。ここで、接続導体4は、例えば平角状の鋼材
を図示のように矩形波状に屈曲成形して半田付は脚部4
aと渡り部4bを交互に形成したものであり、前記脚部
4aと半導体素子3.ないし他の回路部品との間が半田
付は接合されている。なお、かかる半導体装!の回路組
立体はパッケージのケースに収容した上で、ケース内に
注入した充填樹脂で封止される。(Prior Art) First, in FIG. 3, which shows a conventional configuration of a semiconductor device to which the present invention is applied, l is a printed wiring board, 2 is a circuit pattern of the printed wiring board 1, and 3 is a circuit pattern 2.
For example, a semiconductor element such as a transistor or a diode is mounted by soldering to the semiconductor element 3;
Alternatively, a connecting conductor 5 is a solder joint, which is internally wired between the semiconductor element 3 and other circuit components (not shown). Here, the connecting conductor 4 is formed by bending a rectangular steel material into a rectangular wave shape as shown in the figure, and soldering is done on the leg portion 4.
A and transition portions 4b are alternately formed, and the leg portions 4a and semiconductor elements 3. or other circuit components are soldered together. In addition, such a semiconductor device! The circuit assembly is housed in a package case and then sealed with a filling resin injected into the case.
〔発明が解決しようとする課H]
ところで、前記した従来の内部配線構造のままでは次記
のような問題点が残る。すなわち、ヒートサイクル(例
えば−55〜150°C)、あるいは断続通電試験によ
るパワーサイクルにより、半導体装置を構成している各
部品に熱膨張、収縮が生じると、各部の熱膨張差から例
えば半導体素子3と接続導体4との間に熱応力が繰り返
し加わり、この応力が基で半田接合部が剥離したり、半
導体素子自身が割れたりするトラブルの発生することが
ある。[Problem H to be Solved by the Invention] However, if the conventional internal wiring structure described above remains unchanged, the following problems remain. In other words, when thermal expansion and contraction occur in each component of a semiconductor device due to a heat cycle (for example, -55 to 150°C) or a power cycle using an intermittent current test, for example, the semiconductor element Thermal stress is repeatedly applied between the connecting conductor 3 and the connecting conductor 4, and this stress may cause problems such as peeling of the solder joint or cracking of the semiconductor element itself.
一方、このようなトラブルの回避対策として、発明者等
は接続導体4に焼なまし処理を施して材質を軟質化し、
応力を接続導体自身の変形により吸収するようにした方
法を試みたがその効果が不十分であり、前記した半田接
合部の剥離、半導体素子の割れなどを完全に防止するこ
とが困難であることが判った。On the other hand, as a measure to avoid such troubles, the inventors subjected the connecting conductor 4 to annealing treatment to soften the material.
A method of absorbing stress through deformation of the connecting conductor itself has been attempted, but the effect is insufficient, and it is difficult to completely prevent the aforementioned peeling of solder joints and cracking of semiconductor elements. It turns out.
本発明は上記の点にかんがみなされたものであり、接続
導体に簡単な加工を施すことにより、ヒートサイクル、
パワーサイクルに対して高い耐久性、信較性が得られる
ようにした半導体装置、特にその内部配線構造を提供す
ることを目的とする。The present invention has been made in consideration of the above points, and by applying simple processing to the connecting conductor, heat cycle,
It is an object of the present invention to provide a semiconductor device, particularly an internal wiring structure thereof, which has high durability and reliability against power cycles.
[課題を解決するための手段]
上記課題を解決するために、本発明の半導体装置におい
ては、各種素子の相互間にまたがって配線した接続導体
に対し、その渡り部分に円弧状に湾曲した応力吸収部を
形成するものとする。[Means for Solving the Problems] In order to solve the above problems, in the semiconductor device of the present invention, stress curved in an arc shape is applied to the connecting conductors wired between various elements. It shall form an absorbent part.
ここで、前記の応力吸収部は、矩形波状に屈曲成形した
接続導体に対して、各渡り部分の両肩部、ないし渡り部
分の中央部に形成して実施することができる。Here, the stress absorbing portions can be formed on both shoulders of each transition portion or the center portion of the transition portion of the connection conductor bent into a rectangular wave shape.
上記の構成により、ヒートサイクル、パワーサイクルな
どに伴って生じる熱応力は、接続導体に湾曲形成した応
力吸収部の変形によって吸収されるので、半導体素子な
どとの間の半田接合部に加わる応力が極小に抑えられ、
これにより半田接合部の疲労による剥離、あるいは半導
体素子の割れなどのトラブルが確実に回避される。With the above configuration, thermal stress that occurs due to heat cycles, power cycles, etc. is absorbed by the deformation of the stress absorbing part formed in a curved manner on the connecting conductor, so that the stress applied to the solder joint between the semiconductor element and the like is reduced. suppressed to a minimum,
This reliably avoids troubles such as peeling of the solder joint due to fatigue or cracking of the semiconductor element.
第1回、第2図はそれぞれ本発明の異なる実施例を示す
ものであり、各実施例において第3図と同一部材には同
じ符号が付しである。The first part and FIG. 2 each show a different embodiment of the present invention, and in each embodiment, the same members as in FIG. 3 are given the same reference numerals.
まず、第1図の実施例においては、半導体素子3の相互
間にまたがって配線された矩形波状に屈曲成形された平
角状の接a導体4に対し、その渡り部4bにおける両肩
の各コーナには、外方に向けて円弧状に湾曲して膨出す
る応力吸収部4Cが形成されている。この応力吸収部4
Cは、接続導体4を矩形波状に成形加工する過程で同時
に曲げ加工される。First, in the embodiment shown in FIG. 1, each of the corners of both shoulders of the transition portion 4b is connected to the rectangular contact conductor 4 which is bent in a rectangular wave shape and is wired between the semiconductor elements 3. A stress absorbing portion 4C is formed which curves and bulges outward in an arc shape. This stress absorbing part 4
C is bent at the same time as the connecting conductor 4 is formed into a rectangular wave shape.
かかる構成により、半導体素子3と接続導体4との熱膨
張差が基でヒートサイクルなどにより生じる熱応力は、
接続導体4に形成した応力吸収部4c自身の変形により
大半が吸収されるので、半導体素子3との間の半田接合
部5に作用する応力は僅少となる。したがって半田接合
部5の剥離、半導体素子3の割れなどのトラブルを安全
に回避できる。With this configuration, thermal stress caused by heat cycles or the like due to the difference in thermal expansion between the semiconductor element 3 and the connecting conductor 4 can be reduced.
Most of the stress is absorbed by the deformation of the stress absorbing portion 4c formed on the connecting conductor 4, so that the stress acting on the solder joint 5 between the semiconductor element 3 becomes small. Therefore, troubles such as peeling of the solder joint 5 and cracking of the semiconductor element 3 can be safely avoided.
また、第2図の実施例は、特に半導体素子同士が接近し
て配置されている場合に好適な実施例であり、応力吸収
部4Cが接続導体4に対して渡り部4bの中央部に形成
されている。この実施例でも応力吸収部4Cが第1図の
実施例と同様に機能し、半田接合部5.半導体素子3自
身に加ね乞応力を緩和させる効果を奏する。The embodiment shown in FIG. 2 is particularly suitable when semiconductor elements are arranged close to each other, and the stress absorbing part 4C is formed in the center of the transition part 4b with respect to the connecting conductor 4. has been done. In this embodiment, the stress absorbing portion 4C functions similarly to the embodiment shown in FIG. 1, and the solder joint portion 5. This has the effect of alleviating the stress applied to the semiconductor element 3 itself.
なお、図示実施例では、接続導体4として平角状のバー
を採用した例を示したが、接続導体は半導体素子に流す
電流値に適応した断面積を有するものであれば、断面円
形のバーを使用して実施することもできる。Although the illustrated embodiment shows an example in which a rectangular bar is used as the connecting conductor 4, a bar with a circular cross section may be used as the connecting conductor as long as it has a cross-sectional area suitable for the current value flowing through the semiconductor element. It can also be implemented using
本発明の半導体装置は、以上説明したように構成されて
いるので、熱応力を接続導体自身の変形で十分に吸収し
て半導体素子2および半田接合部に加わる応力を軽減す
ることができ、これによりヒートサイクル、パワーサイ
クルに対する耐久性。Since the semiconductor device of the present invention is configured as described above, thermal stress can be sufficiently absorbed by the deformation of the connecting conductor itself, thereby reducing the stress applied to the semiconductor element 2 and the solder joint. Durability against heat cycles and power cycles.
信鯨性の大幅な向上が図れる。This will greatly improve trustworthiness.
第1図、第2図はそれぞれ異なる本発明実施例の構成図
、第3図は従来の半導体装置の構成図である。
1ニブリント配線板、2:回路パターン、3:半導体素
子、4:接続導体、4b=渡り部、4C:応第2図1 and 2 are configuration diagrams of different embodiments of the present invention, and FIG. 3 is a configuration diagram of a conventional semiconductor device. 1 Niblint wiring board, 2: Circuit pattern, 3: Semiconductor element, 4: Connection conductor, 4b = Transition part, 4C: Figure 2
Claims (1)
ないし半導体素子と他の回路部品の間にまたがり接続導
体を半田付けして内部配線した半導体装置において、前
記接続導体の渡り部分に円弧状に湾曲した応力吸収部を
形成したことを特徴とする半導体装置。 2)請求項1に記載の半導体装置において、矩形波状に
屈曲成形された接続導体に対し、応力吸収部が各渡り部
分の両肩部に形成されていることを特徴とする半導体装
置。 3)請求項1に記載の半導体装置において、矩形波状に
屈曲成形された接続導体に対し、応力吸収部が各渡り部
分の中央部に形成されていることを特徴とする半導体装
置。[Claims] 1) between semiconductor elements mounted on a wiring board;
Alternatively, a semiconductor device in which a connecting conductor is soldered to span between a semiconductor element and another circuit component for internal wiring, characterized in that a stress absorbing portion curved in an arc shape is formed in a transition portion of the connecting conductor. Device. 2) The semiconductor device according to claim 1, wherein stress absorbing portions are formed on both shoulders of each transition portion of the connecting conductor which is bent into a rectangular wave shape. 3) The semiconductor device according to claim 1, wherein the stress absorbing portion is formed in the center of each transition portion of the connecting conductor which is bent into a rectangular wave shape.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2296594A JPH04170037A (en) | 1990-11-01 | 1990-11-01 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2296594A JPH04170037A (en) | 1990-11-01 | 1990-11-01 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04170037A true JPH04170037A (en) | 1992-06-17 |
Family
ID=17835568
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2296594A Pending JPH04170037A (en) | 1990-11-01 | 1990-11-01 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04170037A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2012127696A1 (en) * | 2011-03-24 | 2012-09-27 | 三菱電機株式会社 | Power semiconductor module and power unit device |
-
1990
- 1990-11-01 JP JP2296594A patent/JPH04170037A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2012127696A1 (en) * | 2011-03-24 | 2012-09-27 | 三菱電機株式会社 | Power semiconductor module and power unit device |
JP5701377B2 (en) * | 2011-03-24 | 2015-04-15 | 三菱電機株式会社 | Power semiconductor module and power unit device |
US9129931B2 (en) | 2011-03-24 | 2015-09-08 | Mitsubishi Electric Corporation | Power semiconductor module and power unit device |
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