JPH04169875A - Testing of logically integrated circuit - Google Patents

Abstract

PURPOSE:To enable the shortening of a reading time of a test pattern by storing the subsequent test pattern into another IC memory card during the use of one IC memory card. CONSTITUTION:A test pattern is stored previously into an IC memory card 10a composing a large-capacity buffer memory 9a. During a function test of an integrated circuit (DUT) to be tested, the memory 9a is selected with a selecting section 6 and the card 10a is connected to an IC memory card connection part 11a to read out. Here, as there is no transfer of any test pattern to a pattern generating section 7 from a large-capacity buffer memory 9b, an IC memory card 10b can be removed from the IC memory card connection part 11b. Therefore, when a test pattern of a DUT next to the DUT under the present test is stored into the card 10b beforehand, there is no need for reading the test pattern from an input section 2 through a control section 1 immediately before the testing of the subsequent DUT thereby shortening the time accordingly. To achieve the purpose, this operation is performed between the cards 10a and 10b.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a method for testing logic integrated circuits.

[Conventional technology]

Recently, as the degree of integration of logic integrated circuits has increased and their functions have become more complex, test patterns have become longer and longer.

For this reason, it is often becoming impossible to store all test patterns at once in a pattern generating section of a logic integrated circuit testing device (hereinafter referred to as a logic tester). Therefore,
Divide one type of test pattern into multiple parts and temporarily store them in a large-capacity buffer memory, and then transfer the divided test patterns one by one from the large-capacity buffer memory to the pattern generator as needed to generate test patterns. By repeating this process, all test patterns are input to the DUT and a functional test is performed.

FIG. 2 is a block diagram of a logic tester for explaining an example of a conventional logic integrated circuit testing method.

The control unit 1 controls the integrated circuit under test (
Interpreted the test program that describes the test conditions for the DUT (hereinafter referred to as DUT), set the test conditions for each part of the logic tester by interpreting the test program, and described the test program and DUT input pattern or expected output pattern from the DUT. An interpreter that reads the test pattern from the input section 2.
Store programs.

The input unit 2 reads the test program and test pattern from a storage medium such as a floppy disk magnetic tape.

The pass line 3 transfers the test conditions obtained by interpreting the test program by the control section 1 to each section.

The large capacity buffer memory 5 temporarily stores test patterns.

The pattern generator a17 receives and stores a test pattern designated by the test program from among the test patterns previously stored in the large capacity buffer memory 5, and generates the test pattern at the frequency designated by the test program.

The test head section 8 DUs the test pattern from the pattern generation section 7 under the input voltage conditions specified by the test program.
The output from the OLT is compared with the test pattern under specified judgment voltage conditions to determine whether they match.

To explain in more detail, when performing a functional test of the DUT, the control section 1 reads a test pattern from the input section 2 and stores it in advance in the large capacity buffer memory 5 via the pass line 3.

Further, a test program is read from the input section 2 and stored in the control section 1.

At the start of the test, the interpreter program is activated to interpret the test program, and the input voltage condition to the OUT of the test pattern and the judgment voltage of the output from the DUT to the test pattern are set in the test head section 8 via the pass line 3. do.

The test patterns specified by the test program are transferred from the large-capacity buffer memory 5 to the pattern generation section 7, and the pattern generation section 7 sequentially generates test patterns at the frequencies specified by the test program.

The test head section 8 inputs a test pattern to the DUT at an input voltage specified by the test program, compares the output from the DUT with the test pattern in terms of determination voltage, and determines whether the test pattern matches the expected pattern or not.

[Problem to be solved by the invention]

2nd rl! In the conventional logic tester described in section i, a long test pattern is read from the input section 2 and stored in the large capacity buffer memory 5, so that the test pattern reading time becomes long, ranging from several minutes to several tens of minutes.

However, as test patterns become longer and the number of output terminals also increases, test pattern reading times are becoming longer.

During a functional test of a DUT, test patterns are frequently transferred from the large-capacity buffer memory to the pattern generation section, so it is impossible to read and store test patterns of other DUTs from the input section into the large-capacity buffer memory during a functional test. It becomes possible.

Therefore, when the type of DUT changes and the type of test pattern used changes, it is necessary to read the test pattern after the test of the DUT under test is completed, and the logic tester must read the test pattern for the same amount of time. I have to stop testing the DUT.

There has been a drawback that as the proportion of test pattern reading time in the operating time of a logic tester increases, the number of DUTs that can be tested with the logic tester also decreases.

[Means to solve the problem]

The integrated circuit testing method of the present invention includes a buffer memory section that stores a test bar output from a tester control section, and a test pattern read from the buffer memory section that passes through a pattern generation section and a test head section. In the method for testing a logic integrated circuit supplied to an integrated circuit under test, the buffer memory section has a plurality of internal buffer memories each having an IC memory card and an IC memory card connection section, and during a functional test, the buffer memory section select and read out one of the IC memory cards in the other internal buffer memory section from which the test pattern has not been read out.
The test pattern and test program corresponding to the next integrated circuit under test are stored in advance when removed from the memory card connection section.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of a logic tester for explaining one embodiment of the present invention.

The logic tester uses an IC memory card 10a as the memory section 4.
and a large capacity buffer memory 9a consisting of an IC memory card connection section 11a, and a large capacity buffer memory 9a consisting of an IC memory card 10b and an IC memory card connection section 11b that share an input terminal with this large capacity buffer memory 9a. The logic tester is the same as the conventional logic tester shown in FIG. 2 except that it is provided with a selector 96 and a selector 6 for selecting both output signals.

A test pattern is stored in advance in the IC memory card 10a constituting the large-capacity buffer memory 9a, and the test pattern is connected to the IC memory card connection section 11a to perform a functional test of the DUT.During a functional test, the large-capacity buffer memory 9a The selection unit 6 selects and reads out the data.

Since it is desired that the test pattern be transferred to the pattern generating section 7 in the large capacity buffer memory 9b, the IC memory card 10b can be removed from the IC memory card connecting section 11b. Removed IC memory card 10b
Then, the next test pattern can be written to the question being tested using the logic tester IC memory card 10a.

That is, the CU to be tested next to the DUT currently being tested.
If the test pattern of T is stored by removing the IC memory card 10b, there is no need to read the test pattern from the input section 2 via the control section 1 immediately before testing the next DUT, and the time required for this is shortened. Ru.

This question can be asked alternately between the IC memory cards 10a and 10b.

Here, three or more large-capacity buffer memories composed of an IC memory card and an IC memory card connection part may be added, and the configuration of the IC memory card may be configured using battery-backed RAM, PROM, or ROM. A similar effect can be obtained.

〔Effect of the invention〕

As explained above, the present invention provides a memory unit equipped with two or more sets of large-capacity buffer memories composed of IC memory cards, and while one IC memory card is in use, other IC memory
Since the next test pattern is stored in the memory card, it is possible to omit the conventional long time required to read the test pattern from the input section into the large-capacity buffer memory and store it, and the longer the test pattern becomes, the more effective it is expected to be. can.

Furthermore, since no waiting time is required to read test patterns and the number of tests per logic tester increases, it can also be expected to reduce testing costs.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a logic tester for explaining an embodiment of the present invention, and FIG. 2 is a block diagram of a logic tester for explaining an example of a conventional logic integrated circuit testing method. DESCRIPTION OF SYMBOLS 1... Control part, 2... Input part, 3... Pass line, 4... Memory part, 5.9a, 9b... Large capacity buffer memory, 6... Selection part, 7.・Bang generation part,
8... Last head section, 10a, 10b... IC memory card, lla, llb... IC memory card connection section.

Claims (1)

[Claims] A method for testing a logic integrated circuit that includes a buffer memory section that stores a test pattern output from a tester control section, and supplies the test pattern read from the buffer memory section to an integrated circuit under test via a pattern generation section and a test head section. The buffer memory section has a plurality of internal buffer memories each having an IC memory card and an IC memory card connection section, and during a functional test, one of the internal buffer memory sections is selected and read, and the test pattern is read out. removing the IC memory card of the other internal buffer memory section that has not been read out from the IC memory card connection section, and storing in advance a test pattern and a test program corresponding to the next integrated circuit under test; Characteristic testing method for logic integrated circuits.