JPH04167292A - Dualization control processing system - Google Patents

Abstract

PURPOSE:To make it possible to write both active and standby memories by installing a synchronous timing transfer means to refresh other systems and mediating a refresh request signal together with other request from a different device. CONSTITUTION:When an active refresh control circuit 3a outputs a refresh request signal 10 to a bus arbiter 4a gives priority to the refresh, the bus arbiter 4a outputs a refresh priority permission signal 11a to the circuit 3a. At the same time, it outputs a refresh synchronous timing signal 14a to a stand-by bus arbiter and grants refresh permission to the refresh control circuit 3a by way of a refresh permission signal 11b. The both control circuits 3a and 3b commits simultaneous refreshment based on refresh timing signals 12a and 12b by way of memory control signals 6a and 6b. This construction makes it possible to write the both active and stand-by memories simultaneously.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a redundant control processing system.

[Conventional technology]

Referring to FIG. 2, which shows an example of the device configuration in a conventional redundant control processing system, la and lb are processors,
2a and 2b are CPUs, 3a and 3b are refresh control circuits, 4a and 4b are bus arbiters that arbitrate the bus, and 5
a and 5b are memories (main storage devices), 6a and 6b are memory control circuits, 7a and 7b are buses, and 8 is an active CP
Bus request signal from U2a, 9 is bus arbiter 4
A priority permission signal from a to the CPU 2a, 12a.

12b is a refresh timing signal from the refresh control circuits 3a, 3b to the memory control circuits 6a, 6b;
3 is a data bus for writing data from the active system CI'U 2a to the standby system memory 5b during synchronous operation.2 In the above configuration, in the redundant control processing system, during synchronous operation, during write operation to the memory, In order to match the contents of the memories of both systems, a write operation is performed to both systems at the same time. The procedure is such that the active CPU 2a first makes a request to the bus arbiter 4a using the bus request signal 8. The bus arbiter 4a performs arbitration with other devices (input/output devices, etc.) connected to the bus 7a, and when the CPU 2a obtains priority, a priority permission signal 9 notifies the CPU 2a of permission. Active CPU2a
When receiving permission from the bus arbiter 4a, it writes data to the memory 5a via the bus 7a and the memory control circuit 6a, and at the same time writes the same data to the standby memory 5b via the data bus 13. At this time, the refresh control circuits 3a and 3b generate refresh timing signals 12a and 12b at independent cycles, respectively, and refresh the memory circuit (not shown) composed of DRAM, so the memory control circuits 6a and 6
In b, the conflict between the data writing from the CPU 2a and the refresh timing is arbitrated, and control is performed such as delaying the data writing or delaying the refresh.

[Problem to be solved by the invention]

However, in conventional redundant control processing systems, refresh timing is independent for each active or standby system, so if a simultaneous write from the active CPU to the memory of both systems conflicts with refresh, both systems simultaneously write. Not done.

Furthermore, if refresh is performed before writing in both systems, the writing time will be extended by one refresh time at most. In addition to the bus reservation, a circuit with a similar function, such as a contention arbitration circuit for data writing and refresh (in the configuration shown in FIG. 2, is provided in the memory control circuits 6a and 6b), must be placed in the same system. I had to.

[Means to solve the problem]

The duplex control processing system of the present invention includes a main storage means constituted by a DRAM, a refresh control means for generating a refresh timing signal to the main storage means, and a refresh request signal generated by the refresh control means on a bus. A bus request arbitration means that arbitrates with bus request signals from other devices connected to the device and gives priority to bus use, and the refresh control means to which priority is given by the bus request arbitration means are duplicated. A refresh synchronization timing transfer means is provided for transferring a refresh synchronization timing signal to the main storage means of another system.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows the device configuration of a redundant control processing system in one embodiment. la and lb are processors, 2a and 2b are CPUs, 3a and 3b are refresh control circuits, 4a and 4
b is a bus arbiter that arbitrates the bus; 5a and 5b are memories (main storage devices); 6a and 6b are memory control circuits;
a and 7b are buses; 8 is a bus request signal from the CPU 2a; 9 is a priority permission signal from the bus arbiter 4a to the CPU 2a; 10 is a refresh request signal from the refresh control circuit 3a to the bus arbiter 4a; 11a and llb are bus arbiters 4a and 4b. from the refresh control circuit 3a
, priority permission signal to 3b, 12a, 12b are refresh timing signals from refresh control circuits 3a, 3b to memory control circuits 6a, 6b, 13 is writing data from active system CPU 2a to standby system memory 5b during synchronous operation. A data bus 14 is a refresh synchronization timing signal from the active bus arbiter 4a to the standby bus arbiter 4b.

In the above configuration, when writing data in a synchronous operation, the active CPU 2a first outputs the bus request signal 8 to the bus arbiter 4a. The bus arbiter 4a arbitrates requests and sends the request to the CPU via a priority permission signal 9.
Grant permission to 2a. When the CPU 2a receives permission, the CPU 2a connects the bus 7a, the active memory control circuit 6a, and the data bus 13. Writing is simultaneously performed to both the active and standby systems through the standby system memory control circuit 6b. During refresh, the active refresh control circuit 3a similarly outputs the refresh request signal 10 to the bus arbiter 4a, and when refresh is given priority, the bus arbiter 4a gives refresh priority to the refresh control circuit 3a. A permission signal 11a is output. At the same time, the bus arbiter 4a outputs the refresh synchronization timing signal 14.
is output to the standby system bus arbiter 4b, and the bus arbiter 4b gives refresh permission to the refresh control circuit 3b through the refresh permission signal 11b. Refresh control circuit 3a of both systems that has received refresh permission
, 3b are refresh timing signals 12a, 3b, respectively.
12b performs refresh simultaneously through memory control circuits 6a and 6b. At this time, there is no access to the memories 5a, 5b from other devices connected on the buses 7a, 7b because the bus arbiters 4a, 4b have not granted permission.

Here, when both systems are in synchronous operation, if it is a cold standby configuration in which there is no access from other devices to the memory 5b on the bus 7b of the standby system, the refresh synchronization timing signal 14 is directly transmitted to the refresh control circuit 3b.
Alternatively, it may be connected to the memory control circuit 6b. In addition, D
A memory circuit composed of a RAM is provided in the memories 5a and 5b, but is not shown. Furthermore, the bus arbiters 4a and 4b may be arranged independently from the processors la and lb.

〔Effect of the invention〕

As described above, according to the present invention, synchronized operation is achieved by providing a refresh synchronization timing transfer means to other systems and by arbitrating the refresh request signal together with requests from other devices connected to the bus. At the time of writing, it is possible to simultaneously write to both active and standby memories without performing control such as delaying data writing or refreshing when there is a conflict between data writing and refresh timing. Furthermore, by inputting a refresh request signal to the bus arbiter, simultaneous writing in both systems can be realized without placing a circuit having a function similar to a bus arbiter, such as a contention arbitration circuit for data writing and refresh, in the same system.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional duplex control processing system. 1a, 1b--processor, 2a, 2b-CPU, 3
a, 3b... Refresh control circuit, 4a. 4b...Bus arbiter, 5a, 5b...Memory, 6
a, 6b...Memory control circuit, 7a, 7b...Bus, 8...Bus request signal, 9...Priority permission signal, 10...Refresh request signal, lla, llb.
...Refresh priority permission signal, 12a, 12b...
Refresh timing signal, 13... data bus,
14...Refresh synchronization timing signal.

Claims (1)

[Claims] A main memory means constituted by DRAM, a refresh control means for generating a refresh timing signal to the main memory means, and a refresh request signal generated by the refresh control means and a bus from other devices connected on the bus. Refreshing to the main storage means of another system in which a bus request arbitration means arbitrates with a request signal and gives priority to bus use, and the refresh control means given priority by the bus request arbitration means are duplicated. A duplex control processing system comprising refresh synchronization timing transfer means for transferring a synchronization timing signal.