JPH04165390A - Drive circuit for display device - Google Patents

Abstract

PURPOSE:To reduce kinds of external voltage by supplying an external voltage whose level differs depending upon the former half or the latter half of a signal voltage, respectively to an image element, and properly determining the voltage supply time in response to the capacity and so on of a source line. CONSTITUTION:The first voltage V0 is sent to a signal electrode during a begin ning period of one output period and the second voltage V1 is sent out during the residual period by an output selection means 20. As an image element con nected to the signal electrode has an electrical capacity Cs, a signal voltage practically applied to the image element can be in the middle of the first and the second voltages V0, V1 by properly determining the sending times of the first and second voltages V0, V1. Therefore, for the purpose of expressing a set number of gradation, external voltages corresponding to the set number of gradation is unnecessary, and since a fewer number of external voltages V0-V4, will do, a supply circuit for the external voltages can be made smaller and also the number of terminals in the driving circuit of a display circuit can be made fewer.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a drive circuit for a display device, and more particularly to a drive circuit for a display device that can perform gradation display using an amplitude modulation drive method. Although the following explanation will be given by taking a matrix type liquid crystal display device as an example, the present invention is also applicable to drive circuits for other types of display devices, such as EL (electroluminescence) display devices and plasma displays.

(Prior art) When driving a liquid crystal display device, the response speed of the liquid crystal is faster than that of a CRT.
(Cathode Ray Tube) Because it is very low compared to the fluorescent materials used in displays, special display drive circuits are used. In other words, the liquid crystal display drive circuit does not directly apply the video signals that are sent to each pixel as they are, but rather
Video signals sampled corresponding to each picture element within one horizontal scanning period are held during that horizontal scanning period, and are output all at once at the beginning of the next horizontal scanning period or at an appropriate time in the middle thereof.

After starting to output the video signal voltage to each picture element, the signal voltage is held for a time that sufficiently exceeds the response speed of the liquid crystal.

In order to maintain this signal voltage, conventional drive circuits use capacitors. Figure 8 shows the 1 selected by the scanning signal.
This figure shows a signal voltage output circuit (source driver) that supplies drive voltages to N picture elements on the scanning line, and the signal voltage output circuit for the n-th picture element is as shown in FIG.
It is composed of an analog switch SWl, a sampling capacitor Cshp, an analog switch sw2, a hold capacitor CHs, and an output buffer amplifier A.

The operation of conventional signal voltage output will be explained with reference to these figures. The analog video signal v3 input to the analog switch SWI is the sampling clock signal Tsnpt~T.
5IIPN, and the instantaneous voltage of the video signal vg at each time point VS11ρ1~■5NP
N is applied to each sampling capacitor CSMP.

The n-th sampling capacitor Csnp is charged with the video signal voltage value VSl'lPn corresponding to the n-th picture element and holds that value. The signal voltage V thus sequentially sampled and held during the horizontal scanning period
sMp+~V 5IIPN is all analog switch S
Due to the output pulse OE given to W2 all at once,
The signal is transferred from each sampling capacitor Csr+p to a hold capacitor CH, and is output via a buffer amplifier A to source lines 01 to ON connected to each picture element.

<Problems to be Solved by the Invention> The drive circuit described above is for the case where the video signal is given in analog form, but when the video signal is given in the form of digital data, the drive circuit as shown in Fig. 10 is used. A driving circuit is used. Here, for the sake of simplicity, it is assumed that the video signal data consists of 2 bits (D++, D+). In other words, the video signal data is 4 of 0 to 3.
The signal voltage given to each picture element is Va~■
It will be one of the 4 levels of 3. FIG. 10 shows a signal voltage output circuit (source driver) for the n-th source line On, and this circuit is a first-stage circuit provided for each bit (Ds, D+) of video signal data. D flip-flop (sampling flip-flop) Msnp and second stage flip-flop.

Buflo Sob (hold flip-flop) M, 1 decoder DEC, and 4-level external voltage source V8~■
3 and the source line ON. This circuit operates as follows. Video signal data D
,, D1 is taken into the hold flip-flop M+ from the sampling flip-flop knob MgHp at the rising edge of the sampling pulse TSMPn corresponding to the n-th picture element, and is held there. At the end of sampling for one horizontal scanning period, an output pulse OE is applied to the hold flip-flop MH, and the video signal data D, , Di held in the hold flip-flop M+ is output to the decoder DEC. The decoder DEC is this 2
The analog switch ASW@=A S
W 4 level outside I with any one of 3 conductive
J [pressure Va-V3 is output to the source line On.

In the example shown in Figure 10, the video signal data is 2 bits, so the external voltage output to the source line orl is 4 bits.
(=22) level (Ve”Vs).When the video signal data is given in 3 bits, the signal voltage output circuit becomes as shown in Fig. 11, and the external voltage is 23-
Eight levels (Vl-V7) are required. That is, in a digital video signal drive circuit constructed using such a method, if the digital video signal data is n bits, external voltages of 2n levels must be prepared. When the number of types of voltages to be applied from the outside increases in this way, the following problems arise.

(1) As the types of voltages to be supplied increase, the voltage supply circuit becomes larger and the cost also increases.

(2) Since the number of input terminals of the LSI forming the drive circuit including the signal voltage output circuit described above increases, it becomes difficult to implement the LSI.

The present invention was made in view of the current situation, and
The object is to provide a drive circuit for digital video signals that can eliminate the above-mentioned drawbacks and reduce the number of types of external voltages.

(Means for Solving the Problems) A drive circuit for a display device of the present invention is a drive circuit for a display device provided with a plurality of parallel signal electrodes to which picture elements are connected. In accordance with the voltage supply means that outputs the voltage and the input digital image signal, the first m pressure, which is any one of the plurality of levels, is applied during the first period of one output period during the output period. During the remaining period, selection output means is provided for sending a second voltage, which is different from the first voltage, to the signal electrode, thereby achieving the above object.

(Operation) The selection output means sends out the first voltage to the signal electrode during the first period of one output period, and sends out the 211th voltage during the remaining period. Since the picture element connected to the signal electrode has an electric capacity, by appropriately setting the time for sending out the first and second voltages, the signal voltage actually applied to the picture element can be equal to the first and second voltages. The voltage can be between 211 and 211 voltages.

(Example) The invention will now be described with reference to examples.

FIG. 1 shows a signal voltage output circuit corresponding to the nth signal line (source line) of a drive circuit for a liquid crystal display device when digital video signal data is composed of 3 bits. This circuit is a sampling flip-flop MS gate P
1 Hold flip-flop M+4, AND circuit 2
2. Selection circuit 20 and 5 analog switches ASWI
~AS W a is provided.

Both the sampling flip-flop MBHp and the hold flip-flop MW are composed of three D flip-flops corresponding to each bit DIIs DI, D2 of the digital video signal data. One terminal of each of the five analog switches A S Wa - A S Wa is connected to an external five-level voltage source Ve=V4 (however, vl<V,<
V2<V3<V4), and the other terminal is commonly connected to the n-th source line On.

The output 5s=S4 of the selection circuit 20 is sent to the control terminal of each analog switch A S We=A S Wa.

Digital video signal data D, D, % D3 input to the sampling flip-flop MBHp is a sampling pulse TsM corresponding to each source line Orl.
The signals are sequentially sampled by Pn and sent to the hold flip-flop MH. After the sampling of the video signal data of all picture elements on one scanning line is completed, the data held in the hold flip-flop MH is sent to the selection circuit 20 and the AND circuit 22 by the output pulse OE applied to the hold flip-flop MW. . The top two bits held in the hold flip-flop MH) D2,
The video signal data of Dl is directly sent to terminal B of the selection circuit 20.
and A, but the lowest pitch of the video signal data)
D is ANDed with the control signal TM in the AND circuit 22, and the resultant signal CTM is input to the selection circuit 20.

These human forces A, B and CTM in the selection circuit 20
and the output selected by the selection circuit 20 (Sll-
5J) is shown in the table of FIG. For example, video signal data (DI% DI, D2) is (0
, 0, 0), regardless of the value of the control signal TM (
A, B, CTM) = (0, 0, 0), and the selection circuit 20 selects the output S1.

As a result, only the analog switch ASW- becomes conductive, and the power supply voltage $ is sent to the source line or1. The video signal data (DISDt, D2) is (1, 0,
0), the output of the selection circuit 2o depends on the value of the control signal TM. Since CTM=O while the control signal TM is at a low level (L), the selection circuit 20 selects S8 as the output, and V- is sent to the source line 0°. However, when TM becomes high level (H), CTM=1,
The selection circuit 20 selects the output S1, and VI is sent to the source line 0°. The timing diagram of FIG. 3 shows how the output pulse OE, control signal TM, and source line 0° signal change in this case.

An equivalent circuit of the load on source line 0 is shown in FIG. Here, R8 is the total resistance of the source line, CS is the capacitance of the source line, vc(t) is the potential at point A, v con
is the voltage applied to the counter electrode.

In reality, as shown by the broken line in FIG. 4, a picture element capacitor CLC is formed in parallel with the capacitor CS, but the picture element gjlc
Lc is extremely small compared to the source line capacitance Cs (for example, C5=1601)F, CLC=0. 2pF), so it can be ignored. Therefore, the potential at point A v c
(t) can be regarded as the voltage between the picture element electrode and the counter electrode. FIG. 5 shows the change in voltage of the source line Oo in more detail. As shown in FIG.
During period t1, which is the first half of the period of output pulse OE, M is Ll.
■] during the second half period t2, the voltage V(1) of the source line On is v (t)=Ve (0<t≦1+)Vl (t
l<e≦t, +t2). The voltage Ve(t) of the picture element connected to this source line 0° is obtained by solving the following simultaneous equations. Here, 1(t) is the current flowing through the source line O1, and ■θ is the potential at point A when 1=0, that is, the voltage of the source line in the previous horizontal scanning period. Solving this simultaneous equation gives vc(t)=Va+Va・(1-ex p(-t/(Cs-Rs)))
Therefore, vc(t) is 1 8 as shown by the broken line in Figure 5.
approaches. When designing a liquid crystal panel in consideration of such boosting characteristics, the values of the capacitor Cs and the resistor R5 are determined so that vc(t) sufficiently approaches Va within the period of the output Noculus OE.

Second, the change in vc(t) after t1 is obtained by solving the simultaneous equations %(). In addition, here, t−τ0t
1 The coordinate transformation is performed as follows: v = V'+VB. The solution to the above simultaneous equations is VC' (r)= (■+VB) ・! l
-exp (-τ/ (C5-Rs))
1, and the potential at point A, that is, the voltage of the picture element, is the voltage between ■1 and Ve (Vs-V+)/2 (on the v coordinate axis, (■
The time it takes to reach V+/2) is (V+-Vs)/2
= (V+-Vs) ・fl −e x p (-r/
By solving (Cs-Rs) ) ), r= (l n2) ・Cs5R5 =0.693X C5-Rs is obtained. As is clear from this equation, the time τ does not depend on the external voltages Vll, 1 and Ve. Therefore, no matter which two adjacent voltage levels of the external voltages (1a to 4) are selected by the selection circuit 20, the value is uniquely determined. Therefore, by making the time t2 for which the control signal TM is at a high level coincide with τ obtained by the above equation, the voltage of the picture element can be set to a value exactly between V@ and Vl.

The table shown in FIG. 6 summarizes the relationship between the value of the digital video signal data Das Dis D2 and the voltage applied to the picture element in this embodiment which operates in this manner. When the lowest pin FDfI of the video signal data is O, the output of the selection circuit 20 is constant regardless of changes in the control signal TM, so the voltage sent to the source line 0° is a constant value Vi! , ■1, ■2, ■3. However, when the least significant bit D8 is 1, the output of the selection circuit 20 changes as the control signal TM changes within one cycle of the output pulse OE as shown in FIG. External voltages are sequentially sent to source line O1. At this time, in particular, since the sending time τ of the voltage sent in the latter half is determined as in the above equation, as shown in this table, the intermediate value (Vs+V+)/
2, (Vl+V2)/2, (V2+V3)/2,
(V3+■4)/2 is applied to the liquid crystal. Therefore, in this embodiment, in order to supply 8 levels of voltage corresponding to 3-bit video signal data to the picture element, 5 levels of external voltage 18
~VaL is not required.

FIG. 7 shows an example in which the selection circuit 20 of FIG. 1 is specifically constructed of a logic circuit including an AND circuit, an OR circuit, and an inverter. In this example, the following logical formulas are derived from the logical table in Figure 2, and these are realized using AND circuits, OR circuits, etc. In addition, in the following logical formula, CTM is represented by T.

5Ll=B-A-T In the above embodiment, it is assumed that the digital video signal data is composed of 3 bits. In the configuration shown in FIG. 11, when any one of the external voltages is selected and directly applied to the picture element, 23=8 levels of external voltage are required.

However, in this embodiment, it is possible to generate an intermediate level between the two types of external voltages, so it is sufficient to provide five levels of external voltages. Similarly, when the video signal data is 4-bit, it is necessary to prepare an external voltage of 2'=16 levels in the above configuration, but in this embodiment, it is necessary to prepare an external voltage of 2'=16 levels.
= Level 9 is enough. In this way, when video signal data is composed of n bits, if you try to determine all the voltage levels applied to the picture elements from external voltages, you will have to prepare 2n types of external voltage levels, but in this embodiment, 2+
Only n-11+1 types are required. This reduces the burden on the voltage supply circuit and also reduces the number of terminals on the drive circuit side. The degree of reduction in the number of required external voltage levels according to the present invention increases as the number of bits of video signal data increases.

(Effects of the Invention) According to the present invention, when expressing gradation by applying signal voltages of different levels to picture elements based on digital image signal data, one output period of the signal voltage is divided into two, and the first half and In the second half, external voltages of different levels are supplied to the picture elements. By appropriately determining this voltage supply time depending on the capacitance value of the source line, etc., it is possible to apply a voltage to the picture element with a value intermediate between these levels. This eliminates the need for as many external voltages to express a predetermined number of gradations, and requires a smaller number of external voltages, making it possible to reduce the size of the external voltage supply circuit and to The number of terminals in the drive circuit can also be reduced. Furthermore, since it is possible to apply a voltage with a finer step difference to the pixel than the step difference between levels of an external voltage source, even in cases where it is difficult to generate a voltage with a fine difference with an external voltage generation circuit, it is possible to apply a voltage with a finer step difference to the picture element. Tonal expression becomes possible.

4. No words H Figure 1 is a circuit diagram of the portion corresponding to one source line of the drive circuit of a liquid crystal display device using one embodiment of the present invention,
The figure shows a logic table of the relationship between the input and output of the selection circuit used in the embodiment, Figure 3 is a timing diagram showing the operation of the signal voltage output circuit of the embodiment, and Figure 4 shows one source line. Figure 5 is a graph showing changes in the voltage applied to the picture elements of the liquid crystal panel of the example, Figure 6 is the digital video signal data and the voltage applied to the picture elements of the example. FIG. 7 is a circuit diagram of the drive circuit showing the inside of the selection circuit in more detail.
Figure 8 is a circuit diagram of a signal voltage output circuit for analog video signals, Figure 9 is a circuit diagram of only the l source line portion extracted from the circuit, and Figure 10 is each value of 2-bit digital video signal data. FIG. 11 is a circuit diagram of a drive circuit that prepares external voltages for each of the 3-bit digital video signal data.

1) e, Dt, D2... video signal data, MSM
P...Sampling flip-flop knob, MH...Hold flip-flop, 20...Selection circuit, 22.
...AND circuit, A S We"-A S Wa...
Analog switch, Ol, ... source line, Tsn
ρ...Sampling pulse, OE...Output pulse, TM...Control signal, Vθ~■4...External voltage or higher

Claims (1)

[Claims] 1. A drive circuit for a display device provided with a plurality of connected signal electrodes in parallel, comprising: voltage supply means for outputting a plurality of voltages at different levels; Accordingly, at the beginning of one output period, the first output level, which is any one of the plurality of levels, is
A drive circuit for a display device, comprising selective output means for sending a second voltage different from the first voltage to the signal electrode during the remaining period of the output period.