JPH04163952A - Lead frame for resin-sealed semiconductor device - Google Patents
Lead frame for resin-sealed semiconductor deviceInfo
- Publication number
- JPH04163952A JPH04163952A JP2288541A JP28854190A JPH04163952A JP H04163952 A JPH04163952 A JP H04163952A JP 2288541 A JP2288541 A JP 2288541A JP 28854190 A JP28854190 A JP 28854190A JP H04163952 A JPH04163952 A JP H04163952A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- slit
- inner lead
- lead frame
- wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 239000011347 resin Substances 0.000 abstract description 22
- 229920005989 resin Polymers 0.000 abstract description 22
- 238000000465 moulding Methods 0.000 abstract description 6
- 238000000926 separation method Methods 0.000 abstract 1
- 102100025490 Slit homolog 1 protein Human genes 0.000 description 6
- 101710123186 Slit homolog 1 protein Proteins 0.000 description 6
- 230000000694 effects Effects 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 229910000833 kovar Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は樹脂封止型半導体装置用リードフレームに関し
、特に、高消費電力で放熱を必要とする半導体装置の組
立に用いられるリードフレームの構造に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a lead frame for a resin-sealed semiconductor device, and in particular to a structure of a lead frame used for assembling semiconductor devices that consume high power and require heat dissipation. Regarding.
半導体パッケージの組立に用いられるリードフレームの
インナーリード部には、封止用樹脂との密着性を良くす
るために、いわゆるアンカーホールと呼ばれる小穴を開
けることが行なわれている。Small holes, so-called anchor holes, are formed in the inner lead portions of lead frames used for assembling semiconductor packages in order to improve adhesion to sealing resin.
尚リードフレームについて述べた特許および実用新案の
例としては、特公昭６２−１６５５３号公報、裏開昭４
８−８８９４２号、同５１−２１５６２号、同５２−１
６４２４４号、同５３−５６５４５号公報が挙げられる
。Examples of patents and utility models that describe lead frames include Japanese Patent Publication No. 62-16553 and Ura Kaisho 4.
No. 8-88942, No. 51-21562, No. 52-1
No. 64244 and No. 53-56545 are cited.
しかし、従来は、そのアンカーホールはボンディング領
域やその近傍に設けることを避けるのが一般的であり、
また、チップ周辺の１つのボンディングパッドとリード
フレームの１つのインナーリード部とをそれぞれ一本の
ワイヤでボンディングするのが一般的である。However, conventionally, it has been common to avoid providing anchor holes in or near the bonding area.
Further, it is common to bond one bonding pad around the chip to one inner lead portion of the lead frame with one wire.
ところで、パワーＩＣ（集積回路）やパワーＴＲ５（１
−ランジスタ）などのような高消費電力で放熱性を必要
とする半導体装置では、Ｖ ｃ ｃライン１ＧＮＤライ
ンなどの多数のラインを外部に出力するために、多数の
ボンディングパッドから１つのインナーリード部に多点
ワイヤボンディングすることが必要となり、そのために
、インナーリード部は広幅に構成されている。By the way, power IC (integrated circuit) and power TR5 (1
- In semiconductor devices that consume high power and require heat dissipation, such as transistors, it is necessary to connect many bonding pads to one inner lead in order to output many lines such as Vcc line 1GND line to the outside. It is necessary to perform multi-point wire bonding, and for this purpose, the inner lead portion is configured to have a wide width.
かかる場合、リードフレームと封止用樹脂との密着性を
欠如することが、一般の消費電力の低い半導体装置に比
して、多くなり、リードフレームと封止用樹脂との界面
剥離を生じ易くなる。In such a case, the lack of adhesion between the lead frame and the encapsulating resin is more likely to occur than in general semiconductor devices with low power consumption, and interfacial delamination between the lead frame and the encapsulating resin is likely to occur. Become.
また、封止（モールド）に際して、インナーリード部が
たわみ易くなり、ヘッダーなどとショートする割合も高
くなり、半導体装置の信頼性に悪影響を及ぼすことにな
る。Further, during sealing (molding), the inner lead portion becomes easily bent, and the probability of shorting with a header or the like increases, which adversely affects the reliability of the semiconductor device.
本発明はかかる高消費電力で放熱を必要とする半導体装
置に好適な技術を提供することを目的とする。An object of the present invention is to provide a technique suitable for such semiconductor devices that consume high power and require heat dissipation.
本発明の前記ならびにそのほかの目的と新規な特徴は、
本明細書の記述および添付図面からもあきらかになるで
あろう。The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、本発明では、リードフレームの１つのインナ
ーリード部の多点ワイヤーボンディングを行なうその先
端部にスリットを設けることを特徴とする。または、当
該先端部に切欠部を設けるようにする。That is, the present invention is characterized in that a slit is provided at the tip of one inner lead portion of the lead frame where multi-point wire bonding is performed. Alternatively, a notch is provided at the tip.
これにより、スリットに、封止用樹脂（以下、単にレジ
ンという）が流通し、当該スリットを介してレジンが上
下に連結されるので、リードフレームとレジンとの密着
性が良くなり、また、このようなスリットを有さない場
合には、モールド時にレジン圧がかかり、インナーリー
ド部がたわみ易くなり、インナーリード部がヘッダーな
どとショートし易いが、スリットがあるために、スリッ
ト内をレジンが流通し、その圧を軽減して、インナーリ
ード部のたわみを防止し、かつ、ヘッダーなどとのショ
ートを防止できる。As a result, the sealing resin (hereinafter simply referred to as resin) flows through the slit, and the resin is connected vertically through the slit, which improves the adhesion between the lead frame and the resin. If the mold does not have such a slit, resin pressure will be applied during molding, making the inner lead part easy to bend and short-circuiting with the header, etc. However, because of the slit, the resin will not flow through the slit. However, by reducing this pressure, it is possible to prevent the inner lead portion from bending and to prevent short circuits with the header, etc.
従って、半導体装置の信頼性を向上させることができる
。Therefore, reliability of the semiconductor device can be improved.
切欠部を設ける場合にも同様に作用させることができる
。The same effect can be achieved when a notch is provided.
次に、本発明の実施例を図面に基づいて説明する。 Next, embodiments of the present invention will be described based on the drawings.
第１図に示すように、スリット（貫通孔）１が開けられ
たリードフレームインナーリード部２の広幅に構成され
た先端部には、複数のコネクタワイヤ３が、チップ４に
周設されたボンディングパッド５との間で、ワイヤボン
ディングされている。As shown in FIG. 1, a plurality of connector wires 3 are connected to the bonding wires surrounding the chip 4 at the wide distal end of the lead frame inner lead portion 2 in which a slit (through hole) 1 is formed. Wire bonding is performed between the pad 5 and the pad 5.
図示のように、スリットを有する−のインナーリード部
２と当該パッド５との間に、多点ワイヤボンディングが
されている。As shown in the figure, multi-point wire bonding is performed between the - inner lead portion 2 having a slit and the pad 5.
従って、 当該多点ワイヤボンディングでは、Ｖｃｃ、
ＧＮＤなとの信号が当該−のインナーリード部２を介し
て外部に出力されるようになっている。Therefore, in the multi-point wire bonding, Vcc,
A signal such as GND is outputted to the outside via the negative inner lead section 2.
スリット１は、この実施例では、長方形に構成されてい
る例を示してあり、また、この実施例では、インナーリ
ード部２の狭幅部分の長平方向の延長上にすなわち図示
のように横方向に設けられている例を示しである。In this embodiment, the slit 1 is formed in a rectangular shape, and in this embodiment, the slit 1 is formed on an extension of the narrow portion of the inner lead portion 2 in the longitudinal direction, that is, in the lateral direction as shown in the figure. An example is provided below.
、 第１図に示すように、通常のインナーリード部６と
チップ４の周辺ボンディングパッド５との間も、コネク
タワイヤ３を用いて、ワイヤボンディングされている。As shown in FIG. 1, wire bonding is also performed between the normal inner lead portion 6 and the peripheral bonding pad 5 of the chip 4 using the connector wire 3.
当該ワイヤボンディングは、−のインナーリード部６と
−のボンディングパッド５との間で、−本のコネクタワ
イヤ３を用いて行われている。The wire bonding is performed using - connector wires 3 between - inner lead portions 6 and - bonding pads 5.
第２図は本発明の他の実施例を示す。FIG. 2 shows another embodiment of the invention.
この実施例では、インナーリード部２の広幅先端部に、
第１図に示すものとは異なり縦方向に、長方形のスリッ
ト１を設けてなる例を示しである。In this embodiment, at the wide tip of the inner lead part 2,
This shows an example in which a rectangular slit 1 is provided in the vertical direction, unlike the one shown in FIG.
第３図は、本発明のさらに他の実施例を示す。FIG. 3 shows yet another embodiment of the invention.
この実施例では、広幅のインナーリード部２に切欠部７
を設け、当該切欠部７を介して分離した当該インナーリ
ード部２とチップ４のボンディングパッド５とをコネク
タワイヤ３を用いて多点ワイヤボンディングしてなる。In this embodiment, a notch 7 is provided in the wide inner lead portion 2.
The inner lead portion 2 separated through the notch 7 and the bonding pad 5 of the chip 4 are bonded at multiple points using the connector wire 3.
この場合も−のインナーリード部７を介して複数信号が
外部に出力されるようになっている。In this case as well, a plurality of signals are outputted to the outside via the negative inner lead section 7.
第４図はスリットを設ける点では、第１図および第２図
に示す実施例と共通するが、この第４図では、スリット
を逆コ字状のスリット８に構成しである。4 is similar to the embodiments shown in FIGS. 1 and 2 in that a slit is provided, but in this FIG. 4, the slit is formed into an inverted U-shaped slit 8.
第４図に示すように、チップ４のボンディングパッド５
と当該逆コ字状スリット８の内側との間を複数のコネク
タワイヤ３（４本で例示）を用いて多点ワイヤボンディ
ングしてなる。As shown in FIG.
A plurality of connector wires 3 (four wires are illustrated) are used to perform multi-point wire bonding between the connector wires 3 and the inside of the inverted U-shaped slit 8.
第５図は本発明になる樹脂封止型半導体装置（プラスチ
ックパッケージ）の構造例を示す。FIG. 5 shows an example of the structure of a resin-sealed semiconductor device (plastic package) according to the present invention.
ヘッダー９には、導電性ペーストなどを用いて、チップ
４が固着されている。The chip 4 is fixed to the header 9 using a conductive paste or the like.
チップ４とリードフレームインナーリード部２との間は
、コネクタワイヤ３によりワイヤボンディングされてい
る。The chip 4 and the lead frame inner lead portion 2 are wire-bonded using a connector wire 3.
当該インナーリード部２には、スリット１が孔設されて
いる。A slit 1 is provided in the inner lead portion 2 .
当該チップ４を環境条件から保護することなどを目的と
して、レジン１０でモールドを施しである。The chip 4 is molded with resin 10 for the purpose of protecting it from environmental conditions.
本発明で使用されるリードフレームは、例えばコバール
合金により構成されている。The lead frame used in the present invention is made of, for example, Kovar alloy.
コネクタワイヤ３は、例えばＡｕ細線により構成される
。The connector wire 3 is made of, for example, a thin Au wire.
チップ４は、例えばシリコン単結晶基板から成り、周知
の技術によってこのチップ内には多数の回路素子が形成
され、１つの回路機能が与えられている。回路素子の具
体例は、例えばＭＯＳ）ランジスタから成り、これらの
回路素子によって、例えば論理回路およびメモリの回路
機能が形成されている。The chip 4 is made of, for example, a silicon single crystal substrate, and a large number of circuit elements are formed within this chip using well-known techniques to provide one circuit function. A concrete example of a circuit element is, for example, a transistor (MOS), and these circuit elements form, for example, a logic circuit and a memory circuit function.
本発明によれば、インナーリード部２の多点ワイヤボン
ディングが行われる先端部に、スリット１を有し、もし
くは、切欠部７が設けられているので、レジン１０がこ
れらスリット１や切欠部７を流れ込み、インナーリード
部２の表裏面をレジン１０で連結するので、インナーリ
ード部２とレジン１０との密着性を良好にし、これらの
間での界面剥離を防止するとともに、レジン１０がこれ
らスリット１や切欠部７を流通するので、レジン１０の
モールドに際し、インナーリード部２の下方向へのたわ
み（変形）を減少させることができ、インナーリード部
２の変形がおさえられ安定するので、コネクタワイヤ３
の動きも少なくなり、ヘッダー９とコネクタワイヤ３の
ショートなどを防止できる。According to the present invention, since the inner lead part 2 has the slit 1 or the notch 7 at the tip where multi-point wire bonding is performed, the resin 10 can be applied to the slit 1 or the notch 7. Since the resin 10 flows in and connects the front and back surfaces of the inner lead part 2 with the resin 10, it improves the adhesion between the inner lead part 2 and the resin 10 and prevents interfacial peeling between them. 1 and the notch 7, it is possible to reduce the downward deflection (deformation) of the inner lead part 2 when molding the resin 10, and since the deformation of the inner lead part 2 is suppressed and stabilized, the connector wire 3
movement is also reduced, and short circuits between the header 9 and the connector wire 3 can be prevented.
従って、信頼性の高いプラスチックパッケージを得るこ
とができる。Therefore, a highly reliable plastic package can be obtained.
さらに、逆コ字状のスリット８を設けることにより、リ
ークパスが長くなり、プラスチックパッケージの耐湿性
を向上させることができる。Furthermore, by providing the inverted U-shaped slit 8, the leak path becomes longer and the moisture resistance of the plastic package can be improved.
以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが、本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.
本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば下記のとうりである
。A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.
本発明によれば、インナーリード部とレジンとの密着性
が良好になり、これらの間での界面剥離を防止するとと
もに、レジンのモールドに際し、インナーリード部の下
方向へのたわみ（変形）を減少させることができ、イン
ナーリード部の変形がおさえられ安定するので、コネク
タワイヤの動きも少なくなり、ヘッダーとコネクタワイ
ヤのショートなどを防止できる。According to the present invention, the adhesion between the inner lead part and the resin is improved, preventing interfacial peeling between them, and also preventing downward deflection (deformation) of the inner lead part when molding the resin. Since deformation of the inner lead portion is suppressed and stabilized, movement of the connector wire is also reduced, and short-circuits between the header and the connector wire can be prevented.
従って、信頼性の高いプラスチックパッケージを得るこ
とができる。Therefore, a highly reliable plastic package can be obtained.
さらに、本発明によれば、リークパスが長くなり、プラ
スチックパッケージの耐湿性を向上させることができる
。Furthermore, according to the present invention, the leak path becomes longer and the moisture resistance of the plastic package can be improved.
第１図は本発明の実施例を示す要部平面図、第２図は本
・発明の他の実施例を示す要部平面図、第３図は本発明
の他の実施例を示す要部平面図、第４図は本発明の他の
実施例を示す要部平面図、第５図は本発明の他の実施例
を示す断面図である。
１・・スリット（貫通孔）、２・・リードフレームイン
ナーリード、３・・コネクタワイヤ、４・・・チップ、
５・・ボンディングパッド、６・・・インナーリード、
７・−切欠部、８・・逆コ字状スリット、９・・・ヘッ
ダー、１０ ・レジン。
第 １ 図
第 ２ 図
第 ３ 図Fig. 1 is a plan view of the main part showing an embodiment of the present invention, Fig. 2 is a plan view of the main part showing another embodiment of the present invention, and Fig. 3 is a plan view of the main part showing another embodiment of the invention. FIG. 4 is a plan view of a main part showing another embodiment of the present invention, and FIG. 5 is a sectional view showing another embodiment of the present invention. 1...Slit (through hole), 2...Lead frame inner lead, 3...Connector wire, 4...Chip,
5...Bonding pad, 6...Inner lead,
7.-notch, 8.-inverted U-shaped slit, 9.-header, 10.-resin. Figure 1 Figure 2 Figure 3
Claims (1)
ド部に複数のワイヤボンディングを行なうことを必要と
する樹脂封止型半導体装置用リードフレームにおいて、
前記インナーリード部の多点ワイヤボンディングを行な
うボンディング領域を有する先端部にスリットを設ける
かまたは当該先端部に切欠部を設けて成ることを特徴と
する樹脂封止型半導体装置用リードフレーム。 ２、リードフレームが、ヘッダーを有して成ることを特
徴とする請求項１に記載の樹脂封止型半導体装置用リー
ドフレーム。[Claims] 1. In a lead frame for a resin-sealed semiconductor device that requires multiple wire bondings from multiple bonding pads to one inner lead part,
A lead frame for a resin-sealed semiconductor device, characterized in that a slit is provided in a tip portion of the inner lead portion having a bonding region for performing multi-point wire bonding, or a notch is provided in the tip portion. 2. The lead frame for a resin-sealed semiconductor device according to claim 1, wherein the lead frame has a header.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2288541A JPH04163952A (en) | 1990-10-29 | 1990-10-29 | Lead frame for resin-sealed semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2288541A JPH04163952A (en) | 1990-10-29 | 1990-10-29 | Lead frame for resin-sealed semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04163952A true JPH04163952A (en) | 1992-06-09 |
Family
ID=17731575
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2288541A Pending JPH04163952A (en) | 1990-10-29 | 1990-10-29 | Lead frame for resin-sealed semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04163952A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5955778A (en) * | 1996-10-08 | 1999-09-21 | Nec Corporation | Lead frame with notched lead ends |
| JP2009032899A (en) * | 2007-07-27 | 2009-02-12 | Renesas Technology Corp | Semiconductor device |
-
1990
- 1990-10-29 JP JP2288541A patent/JPH04163952A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5955778A (en) * | 1996-10-08 | 1999-09-21 | Nec Corporation | Lead frame with notched lead ends |
| JP2009032899A (en) * | 2007-07-27 | 2009-02-12 | Renesas Technology Corp | Semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5648682A (en) | Resin-sealed semiconductor device and lead frame used in a resin-sealed semiconductor device | |
| US7482699B2 (en) | Semiconductor device | |
| US7012321B2 (en) | Stacked semiconductor device including improved lead frame arrangement | |
| US7078824B2 (en) | Semiconductor device having a switch circuit | |
| KR100202760B1 (en) | Semiconductor device | |
| JPH04163952A (en) | Lead frame for resin-sealed semiconductor device | |
| US20020153600A1 (en) | Double sided chip package | |
| JPH0546098B2 (en) | ||
| US20030038358A1 (en) | Semiconductor package without outer leads | |
| JPS61137352A (en) | Semiconductor device | |
| JP2002076234A (en) | Resin-sealed semiconductor device | |
| KR100220244B1 (en) | Stack package using solder bump | |
| KR100635386B1 (en) | Semiconductor chip package with high speed signal processing | |
| JPS63293963A (en) | Resin-sealed semiconductor device | |
| JPS61236144A (en) | Resin-molded semiconductor device | |
| JPH0529528A (en) | Semiconductor integrated circuit device and lead frame used for same | |
| JPH02278857A (en) | Resin-sealed type semiconductor device | |
| JP2758677B2 (en) | Semiconductor device and manufacturing method thereof | |
| KR20030083561A (en) | Resin-sealed semiconductor device | |
| KR200154510Y1 (en) | Lead on chip package | |
| JPH0595018A (en) | Manufacture of semiconductor device | |
| JPH09129812A (en) | Semiconductor device | |
| JP3251436B2 (en) | Lead frame, semiconductor device, and method of manufacturing semiconductor device | |
| KR200169834Y1 (en) | Semiconductor package | |
| JPH05291460A (en) | Resin-sealed semiconductor flat package |