JPH04162544A - Semiconductor device - Google Patents

Abstract

PURPOSE:To output an alarm when a probe is displaced, and to detect even the generation of bump collapse due to the displacement of the probe without checking appearance by forming a pump for the probe not connected to an internal circuit and a peripheral wiring layer surrounding the periphery of the bump and being connected to the bump for measurement. CONSTITUTION:In a semiconductor device having bump electrodes 4 brought into contact with the probe 7 of a probing-card on the surface of a semiconductor chip 1 in order to measure the electrical characteristics of the semiconductor chip 1, a bump 2 for a probe not connected to an internal circuit and a peripheral wiring layer 3 surrounding the periphery of the bump 2 for the probe and being bonded with the bump 4 for measurement are formed on the surface of the semiconductor chip 1. Bumps 2 for gold probes not connected to an internal circuit are formed at two corners of the semiconductor chip 1, and the peripheral wiring layers 3 having the same height and composed of gold as the same material quality are shaped around the bumps 2 at intervals of approximately 10mum. The peripheral wiring layers 3 are connected to the bumps 4 for measurement at GND potential positioned near the bumps 2 for the probe. The bumps 2 for the probes are used only for checking displacement.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor device.

[Conventional technology]

When performing electrical measurements on chips in the wafer state of semiconductor devices, the probes of the probe card that come into contact with the bump electrodes are usually aligned in the horizontal direction using a prober, and then the zero point in the rotational direction of the probe card is visually checked. or CR
Check and match on the T-monitor screen.

When the chip size is small and the number of pads is not large, zero point alignment is generally done by visually checking the probe card, and is done by observing the positions of the chip pads and the card needle tip using a microscope. If the chip has a pad, the pad size is small, and the pitch is narrow, a dummy wafer is used to make needle marks, and the prober side automatically matches the needle tip coordinates input in advance with the needle marks. The monitor screen is used for

[Problem to be solved by the invention]

This conventional semiconductor device has more than 500 bins and has gold bump electrodes, although there is no problem with visual inspection or a monitor screen because there is plenty of pad size and pitch when the number of pads on a semiconductor chip is small. T.A.
In BLSI, both the bump size and pitch are quite small, so even when using a monitor screen, it is difficult to hit the center of the bump on the chip with a probe.

If the probe 7 hits the center part 10 of the knob electrode 6 as shown in FIGS. 4(a) and (b), it is normal;
As shown in a) and (b), when the probe 7 hits the edge of the bump electrode 6, it leaves a needle mark 10a, which may cause the bump shape to become distorted. However, there was a problem in that the appearance check in the post-process resulted in defects.

Furthermore, even if the needles were properly aligned before measurement, the card would become misaligned during continuous measurement of wafers, causing damage to the bump electrodes 6 without being noticed.

[Means to solve the problem]

The semiconductor device of the present invention is a semiconductor device having a bump electrode on the surface of the semiconductor chip that contacts a probe of a probe card in order to measure the electrical characteristics of the semiconductor chip. and,
A peripheral wiring layer surrounding the probe bump and connected to the measurement bump is provided on the surface of the semiconductor chip.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a plan view of a semiconductor chip according to a first embodiment of the present invention.

There are gold probe bumps 2 at two corners of the semiconductor chip 1 that are not connected to the internal circuit, and around these bumps there are approximately 10
The peripheral wiring layers 3 are made of gold and are made of the same material and have the same height and are spaced apart by μ.

The peripheral wiring layer 3 is connected to the GND near the probe bump 2.
It is connected to a potential measurement bump 4.

FIGS. 2(a) and 2(b) are a schematic diagram and a schematic cross-sectional view taken along the line A--A for explaining the probe misalignment check operation of the semiconductor device of FIG. 1.

During the measurement of chip characteristics, a direct current voltage is applied to the probe 7 placed on the probe bump 2, and the flowing current is measured.

If the probe 7 slips and comes into contact with the peripheral wiring layer 3, or if the edge of the probe bump 2 is damaged and comes into contact with the peripheral wiring layer 3,
If there is a short circuit between the probe bump 2 and the measuring knob, a current will flow, so if the ammeter 9 determines that there is an abnormality, the chip characteristic measurement can be interrupted.

The size of the probe bump 2 is, for example, about 20 μ (on each side) smaller than the other bump electrodes in order to increase the detection sensitivity of deviation.

Further, this probe bump 2 is used only for checking misalignment and is not used for lead bonding.

FIG. 3 is a plan view of a second embodiment of the present invention, in which a probe pad 2 is placed immediately adjacent to a knob 5 for measuring the highest potential of Vcc.

〔Effect of the invention〕

As explained above, the present invention provides a probe misalignment measurement pattern layer in the chip and uses a tester to electrically check for misalignment, so an alarm can be output when misalignment occurs. There is an effect that the occurrence of bread shift due to misalignment can be detected without checking the appearance.

[Brief explanation of drawings]

Fig. 1 is a plan view of the first embodiment of the present invention, Fig. 2(a)
, (b) is a schematic diagram for explaining the operation of the probe misalignment check of the semiconductor device in FIG. 1, and a schematic cross-sectional view taken along the line A-A, and FIG. Figure 4(a),
5(b) is a schematic plan view and a schematic cross-sectional view taken along the line A-A of a bump in an example of a conventional semiconductor device in a state where there is no tip deviation, and FIG. 5(a). (1)) is a plan view and a schematic cross-sectional view taken along the line A-A of a bump in a probe misalignment state in an example of a conventional semiconductor device. 1... Semiconductor chip, 2... Bump for probe, 3...
- Peripheral wiring layer, 4.5... Measurement bump, 6... Bump, 7... Probe, 8... DC power supply, 9... Ammeter.

Claims (1)

[Claims] In a semiconductor device having a bump electrode that contacts a probe of a probe card on the surface of the semiconductor chip in order to measure the electrical characteristics of the semiconductor chip, a probe bump that is not connected to an internal circuit; A semiconductor device comprising a peripheral wiring layer on the surface of the semiconductor chip that surrounds the periphery of the semiconductor chip and is connected to the measurement bump.