JPH04160915A - Hysteresis circuit - Google Patents

Abstract

PURPOSE:To reduce operating current and to considerably reduce current consumption without allowing through current to flow in the circuit in principle by using a logic circuit constitution for realizing a particular logical expression. CONSTITUTION:Letting an input signal be x, a delay signal for input signal x by a delay circuit be xD, the initial output of a relevant hysteresis circuit be y, and the next output of the relevant hysteresis circuit be Y, the relevant hysteresis is provided with a logic circuit that realizes a logical expression Y=(X+XD).Y+X.XD. For example, the present hysteresis circuit is constituted by a delay circuit 1, the first NAND circuit 2, an OR-NAND composite gate circuit 3, and the second NAND circuit 4. When signal 105 at output terminal 52 is at H level, if a negative pulse signal having a delay time longer than tD is input as signal 101, and if signal 101 at input terminal 51 and signal 102 to be output from delay circuit 1 become L level at a time, signal 104 to be output from the OR-NAND gate circuit 3 becomes H level, and further since signal 103 to be output from the first NAND circuit 2 is at H level, signal 105 at output terminal 52 changes to L level.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a hysteresis circuit, and particularly to a hysteresis circuit formed by a semiconductor integrated circuit.

[Conventional technology]

Conventionally, the following two types of circuits are known as hysteresis circuits formed by semiconductor integrated circuits. One of them, as shown in FIG. 5, includes a P-channel transistor 9, N-channel transistors 10, 11 and 12, an inverter 13, etc. Further, FIGS. 6(a), (b) and (c) are signal timing charts showing the operation of this conventional example.

In FIG. 5, a signal 11 input from an input terminal 55
1, when a positive pulse signal (see time domain E in FIG. 6) is input, a certain amount of time elapses from when N-channel transistor 11 turns on until when N-channel transistor 12 turns off. During this time, a through current flows between N-channel transistor 11 and N-channel transistor 12. N-channel transistor 11 is designed to have a larger saturation current (hereinafter referred to as ID) than N-channel transistor 12, so although the potential at junction 114 decreases, The way it decreases follows a gradual change under the influence of the through current.

Also, the N-channel transistor 1 which is in the on state
The potential of the signal 112 output from the 0 train also gradually decreases.

At this time, if the high level period of the signal 111 elapses before the potential of the signal 112 falls to the potential at which the inverter 13 becomes operational, the signal Lt3 at the output terminal 56 becomes The level does not change and remains at the same level. Therefore, of the signal Lit input from the input terminal 55, a positive pulse signal having a certain time width or less is removed at the output terminal 56 side.

In addition, as another conventional example, as shown in FIG.
It is configured to include a first inverter 14, a second inverter 15, a third inverter 16, and the like. Figure 8 (a
), (b) and (c) are signal timing charts showing the operation of this conventional example.

In FIG. 7, the signal 11 input from the input terminal 57
5, when the positive pulse signal (see time domain G in Fig. 8) is inverted (see time domain H in Fig. 8), the first
Between the inverter 14 and the third inverter 16,
Similar to the conventional example, a through current flows. Therefore, for the same reason as explained in FIG. If the level of the signal [15 returns to the potential before inversion before the potential changes to the potential that operates the signal 117, the level of the signal 117 at the output terminal 58 does not change and is maintained at the same level. Therefore, among the pulse signals input from the input terminal 57, positive pulse signals having a certain time width or less are removed at the output terminal 58 and are not output.

[Problem to be solved by the invention]

In the conventional hysteresis circuit described above, in the case of the circuit shown in FIG. 5, the operating current is large due to the flow of through current, and in terms of operation, it is completely ineffective against negative pulse noise. Furthermore, the r of the N-channel transistor 12 has the disadvantage that there is no (see time domain F in FIG. 6). Or, if it is too large compared to ro of the N-channel transistor 11, the potential on the output side will not drop forever, resulting in an increase in the amount of through current and a decrease in the reaction speed.On the other hand, if it is too small, 10 of N-channel transistor 11 because the effect as a hysteresis circuit disappears.
[D of N-channel transistor 12 must be set accordingly.

However, in order to set this 1°, it is necessary to take into account the correlation effect with other transistors, and due to changes in IO due to variations in the transistor process, etc.
The problem is that it is extremely difficult to set and adjust the size of these transistors because the balance is easily lost. That is, there is a drawback in that it is extremely difficult to set 10 of the Ni channel transistors 12 described above.

This also applies to the circuit shown in FIG. 7, where the first inverter 14 and the third inverter 1
There is a drawback that the operating current is large because a through current flows between the first inverter 14 and the third inverter 16. The drawback is that it is difficult to set values and difficult to make fine adjustments.

[Means for solving problem y]

The hysteresis circuit of the present invention is a hysteresis circuit that removes a large caballus signal of a certain time width or less as noise, in which a human input signal is x, a delay signal of the input signal X by a delay circuit is x(, the hysteresis circuit When the initial output of the hysteresis circuit is y, and the next output of the hysteresis circuit is Y, the circuit is configured to include a logic circuit that realizes the logical formula Y - (x+Xo)·y+x·x□.

〔Example〕

Next, the present invention will be explained with reference to the drawings. FIG. 1 is a circuit diagram showing a first embodiment of the present invention. As shown in FIG. 1, this embodiment includes a delay circuit 1, a first NAND circuit 2, an RN, AAND composite gate circuit 3, and a second NAND circuit 4. Prepared and configured. In addition, FIGS. 2(a), (b), (c), (d), and (e) show the timing diagram of the signals showing the operation of this embodiment.
It is a chart.

In FIG. 1, a signal 10 input from an input terminal 51
1. When the signal 102 output from the delay circuit 1 and the signal 105 at the output terminal 52 are both at L level, the delay time to (second
Consider the case where a shorter positive pulse signal is input (see time domain A in FIG. 2(a)).
In this case, N in the 0R-NAND composite gate circuit 3
The level of the signal 105 connected as a feedback input as an AND input is at L level at this point, so the NAN
The signal 104 as the D output is at H level. Furthermore, since the pulse width of the signal 101 is shorter than that of the LD, the signals 101 and 102 do not become H level at the same time. Therefore, the signal 101 and the signal 103 output from the first NAND circuit 2 are Both remain at H level, and signal 105 remains at L level. That is, positive pulse noise at output terminal 52 is removed.

Next, consider the case where a positive pulse signal longer than the delay times t and o is input as the signal 101 when the signal 105 at the output terminal 52 is at the L level (Fig. 2 (a)
). In this case, when the signal 101 at the input terminal 51 and the signal 102 output from the delay circuit 1 go to H level at the same time, the signal 103 output from the first NAND circuit 2 goes to L level. Therefore, the signal 105 output from the second NAND circuit 4 changes to H level. At the time of 2, the signal 104 output from the 0R-NAND composite gate circuit 3 changes to L level, but the signal 105 remains at H level.

Next, consider the case where a negative pulse signal shorter than the delay times t and o is input as the signal 101 when the signal 105 at the output terminal 52 is at H level (see Fig. 2(a).
), in which case the signal 101 at the input terminal 51 and the signal 102 output from the delay circuit 1
Since at least one of the signals is at H level and the signal 105 at the output terminal 52 is at H level, 0R-
The signal 104 output from the NAND composite gate circuit 3 becomes L level.

Therefore, the signal 105 is maintained at the H level and does not change by -1. Therefore, the negative pulse noise at the output terminal 52 is removed.

Finally, consider the case where a negative pulse signal longer than the delay times t and o is manually input as the signal 101 when the signal 105 at the output terminal 52 is at H level (see Fig. 2).
In this case, if the signal 101 at the input terminal 51 and the signal 102 output from the delay circuit 1 go to L level at the same time, the signal 102 output from the 0R-NAND composite gate circuit 3 The signal 104 becomes H level, and the signal 1 output from the first NAND circuit 2
Since signal 03 is at H level, signal 105 at output terminal 52 changes to L level. This level change of the signal 105 is caused by the signal 105 being 0R-NAN where the return force is weak.
The level of the signal 104 which is the output of the D composite gate circuit 3 is not affected in any way.

Next, a second embodiment of the present invention will be described. FIG. 3 is a circuit diagram of the second embodiment. As shown in FIG. 3, this embodiment includes a delay circuit 5 and a first NOR circuit 6.
, AND-NOR composite gate circuit 7, and second NOR
The circuit 8 is configured to include a circuit 8. Also, Fig. 4(a),
(b), (c), (d) and (e) are signal timing charts showing the operation of this embodiment.

In FIG. 3, a signal 10 input from an input terminal 51
6 and the signal 107 output from the delay circuit 5 are respectively output from the first NOR circuit 6 and the AND-N.

It is input to the Ri combination gate circuit 7. Consider a case where a positive pulse signal shorter than the delay time to by the delay circuit 1 is input as the signal 101 when the signal 110 at the output terminal 54 is at L level. In this case, the signal 106 inputted from the input terminal 51 and the signal 107 outputted from the delay circuit 5 do not become H level at the same time, and the signal 109 outputted from the AND-NOR composite gate circuit 7 will never go to L level, therefore, signal 1
10 is kept at L level.

Furthermore, when the signal 110 is at the L level, if a positive pulse signal longer than the delay time t, D by the delay circuit 1 is input as the signal 106, in this case, the signal 106 and the signal 1
Since it can become H level at the same time as 07, AND-NO
The signal 109 output from the R composite gate circuit 7 becomes L level, and the signal 110 at the output terminal 54 changes to L level.

Further, when the signal 110 is at the H level, if a negative pulse signal with a time width shorter than the delay time LD is input as the signal 106, the signals 106 and 107 will not go to the L level at the same time, and therefore, Signals 109 and 108
Since both are held at L level, the output terminal 54
The signal 11O at is maintained at the H level.

Finally, if a negative pulse signal with a time width longer than the delay time LD is input as signal 106 when signal 110 is at H level, signals 106 and 107 may become L level at the same time. Therefore, when the signal 10g is at H level and the signal 109 is at L level, the signal 110 at the output terminal pair changes to L level. Therefore, pulse signals having a certain time width or less are ignored and removed on the output terminal 54 side.

〔Effect of the invention〕

As described above in detail, the present invention has the effect that by using a logic circuit configuration, no through current flows in principle, the operating current is reduced, and the current consumption is significantly reduced. be.

Further, there is an effect that the circuit operates normally regardless of changes in the saturation current In caused by process variations of individual transistors.

Furthermore, since the delay amount of the delay circuit is easily adjusted, there is no need for difficult transistor size adjustment.

[Brief explanation of the drawing]

1 and 3 are circuit diagrams of the first and second embodiments of the present invention, respectively, and FIGS. 2(a) and 2(b). (c), (d) and (e) are timing diagrams of signals in the first embodiment;
(d) and (e) are signal timing diagrams in the second embodiment, FIGS. 5 and 7 are circuit diagrams of the conventional example, and FIGS. Figure 8(a),
(b) and (C) are timing diagrams of signals in the conventional example, respectively. In the figure, 1.5...delay circuit, 2...
...First NAND circuit, 3...0R-NAN
D composite gate circuit, 4...second N A N'
D circuit, 6...first NOR circuit, 7...
...AND-NOR composite gate circuit, 8...
Second NOR circuit, 9... P-channel transistor, 10-13... N-channel transistor, 14... First inverter, 15...
...Second inverter, 16...Third inverter.

Claims (1)

[Claims] In a hysteresis circuit that removes an input pulse signal with a certain time width or less as noise, an input signal is x, a delayed signal of the input signal x by a delay circuit is x_D, an initial output of the hysteresis circuit is y, and the hysteresis circuit is When the next output of is Y, the logical formula Y=(x+x_D)・
A hysteresis circuit characterized by comprising a logic circuit that realizes y+x・x_D.