JPH04160662A - Line controller - Google Patents

Abstract

PURPOSE:To prevent the rejection of data reading from a buffer memory at the time of receiving and to prevent the absence of transmitting data in the buffer memory at the time of transmitting by temporarily changing priority order and receiving an interruption when the number of interruptions held in an interruption control part reaches a prescribed value. CONSTITUTION:This line control device is constituted of an MPU 1 for controlling the whole system, a bus interface control means 3 for transferring data between a master device and the buffer memory 2 through an internal bus 6, a line control means 4 for transferring data between a line and the memory 2, and the interruption control means 5 for receiving an internal bus using request interruption outputted from the means 3 and executing interrupting processing to the MPU 1 in the previously determined priority order. A means for interrupting the MPU 1 with priority when the number of interruption processing queue interruption requests reaches the previously determined value is also included. Consequently, the generation of over run/under run in which data can not be loaded to the master device can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a line control device, and particularly to a priority control system for interrupts from a line control unit and a bus interface control unit.

[Conventional technology]

Conventional line control devices of this type store data from a host device in a buffer memory connected to the internal bus when transmitting to the line, and store received data stored in the buffer memory when receiving from the line. In order to transfer the data to the host device, the bus interface control unit issues a bus request interrupt to the MPU. The line control unit also issues an interrupt in order to transmit data in the buffer memory onto the line and to store data received from the line in the buffer memory. Upon receiving the interrupt, the MPU gives the right to use the bus to each control unit to perform data transfer. The priority order in this case is determined by the numbers of the interrupt signal input pins provided in advance in the MPU. A normal line control device connects the line control section to a high priority input pin to prevent line overrun/underrun.

[Problem to be solved by the invention]

The priority control of the conventional line control device mentioned above is determined by the input pin of the MPU to which the interrupt signal line is connected, and the line control unit is always given priority, so when the number of interrupts from the line increases, the right to use the bus is transferred to the line control unit. Interrupts from the bus interface control unit are suspended, and the bus interface control unit becomes inoperable and data is not received by the host device, resulting in an overrun/interrupt.
This has the disadvantage that underrun occurs.

[Means to solve the problem]

The present invention provides an MPU that controls the entire system, a bus interface control unit that transfers data via an internal bus between a host device and a buffer memory provided in advance, and a bus interface control unit that transfers data between a line and the buffer memory. The line control means that transfers data via the internal bus and the interrupt of the internal bus use request from the bus interface control means or the line control means are normally accepted by separate receivers. In a line control device comprising an interrupt control means for processing interrupts to the MPU in priority order of acceptors, the interrupt control means receives requests from the bus interface control means or the line control means that are accepted by the respective acceptors. When the number of interrupt requests waiting for interrupt processing to the MPU reaches a predetermined number,
The present invention is characterized in that it includes means for processing interrupts to the MPU preferentially for the interrupt requests that have reached the predetermined number.

〔Example〕

FIG. 1 is a block diagram of one embodiment of the present invention. Reference numeral 1 denotes an MPU 12 that runs on a microprogram, which is a buffer memory, 3 a bus interface control unit that transfers data with a host device, 4 a line control unit that controls transmission and reception with a line, and 5 an internal interrupt priority control function. 6 is a common internal bus within the line control device, and 7 is a system bus having an interface with a host device.

Next, the operation of this embodiment will be explained. When transmitting to the line, the bus interface control unit 3 receives data from the system bus 7 and transfers it to the buffer memory 2.
Generates an interrupt to PU1. Interrupted MPUI
returns the right to use the bus to the bus interface control unit 3,
After securing the bus, the Kitabus interface control unit 3 stores the transmission data in the buffer memory 2 by DMA transfer, and once the transfer is completed, issues an end interrupt to the MPUI again. The MPU 1 that received the end interrupt activates the line control unit 4. The activated line control unit 4 issues a bus request to the MPU 1, and if the right to use the bus is obtained, it takes over the transmission data from the buffer memory 2 by DMA transfer and outputs it onto the line.

At the time of reception, the operation is opposite to that described above. Further, an interrupt signal for a bus request on the line control section side is connected to the L1 pin of the MPU 1, and an interrupt signal for a bus request on the path interface control section side is connected to the L2 pin of the MPUI. Inside the MPU 1, priority control is performed in the order of LL>L2, and the line control unit 4
is given priority. If there are bus request interrupts from both the line control section 4 and the bus interface control section 3, the interrupt from the bus interface control section 3 is suspended. When the multiplicity of transmission/reception on the line increases, bus request interrupt signals for reception from the line control unit 4 occur frequently, and the number of times received data is stored in the buffer memory increases.
I activates the bus interface control unit 3 to transfer the received data stored in the buffer memory to the host device, but the interrupt from the bus interface control unit 3 has a lower priority than the interrupt from the line control unit 4. Therefore, many cases are put on hold. When the number of pending interrupt signals from the bus interface control unit 3 reaches a predetermined number in response to activation of the bus interface control unit 3, the interrupt control unit 5 prioritizes them within the interrupt control circuit unit 5. The control is changed so that interrupts from the bus interface control unit 3 are accepted by the MPUI microprogram, giving priority to the bus use right to the bus interface control unit, making it possible to transfer the received data in the buffer memory to the host device. do. When the DMA transfer from the bus interface control unit 3 is completed, the MPUI restores the priority order and accepts interrupts from the line control unit 4 again. Further, when the number of pending interrupts of the line control unit 4 reaches a certain value, the priority is temporarily changed, the interrupt is accepted, and data transmission/reception is performed.

〔Effect of the invention〕

As explained above, in the present invention, when the number of pending interrupts in the interrupt control unit 5 reaches a predetermined number, the priority order is temporarily changed and the interrupt is accepted. This has the effect of preventing overruns/underruns in which data cannot be picked up or there is no transmission data in the buffer memory 2 at the time of transmission.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. 1...MPU12...Buffer memory, 3...Bus interface control unit, 4...Line control unit, S...
- Interrupt control unit, 6... internal bus, 7... system bus.

Claims (1)

[Claims] An MPU that controls the whole, a bus interface control means that transfers data via an internal bus between a host device and a buffer memory provided in advance, and a bus interface control unit that transfers data between a line and the buffer memory via the internal bus. a line control means for data transfer, and a line control means that receives interrupts for requests for use of the internal bus from the bus interface control means or the line control means through separate receivers; In a line control device comprising interrupt control means for processing interrupts to an MPU, the interrupt control means waits for processing of interrupts to the MPU from the bus interface control means or the line control means accepted at the separate reception ports. When the number of interrupt requests reaches a predetermined number, the device is characterized by having means for processing the interrupt to the MPU preferentially for the interrupt requests that have reached the predetermined number. Line control device.