JPH04158687A - Minimum value circuit - Google Patents

Abstract

PURPOSE:To obtain a high precision minimum value circuit by providing an emitter coupling pair so as to correct an error forcibly. CONSTITUTION:In order to improve the switching characteristic, NPN transistors(TRs) Q11-Q14 are employed, an output current of constant current sources I11-I13 is set to 2Io and an output current of constant current sources I11, I15 is set to Io. Then the circuit is provided with an emitter coupling pair 53 comprising TRs Q19, Q20 and a constant current source I16 whose current is set to 2Io. Thus, a highly accurate minimum circuit with less error (leakage) is realized, and a correlation circuit or an intermediate value circuit with high accuracy or a luminance signal chrominance carrier signal separation circuit with high performance or the like is realized.

Description

Detailed Description of the Invention [Purpose of the Invention (Field of Industrial Application) The present invention is applicable to image filters including, for example, a high-precision correlator circuit 1 intermediate value circuit, a luminance signal carrying color signal separation circuit, etc. This invention relates to improvements in minimum value circuits suitable for use.

(Prior Art) As is well known, by combining a minimum value circuit and a maximum value circuit, a high precision correlator circuit as shown in FIG. 8 or a high precision intermediate value circuit as shown in FIG. 9 can be created. Can be configured.

First, the correlator circuit shown in FIG.
．． 12 are both supplied to the maximum value circuit 13 and the minimum value circuit 14, and after selecting the respective maximum value components and minimum value components, the maximum value circuit 13
The reference voltage V re applied to the output and power supply terminal 15
An output selected by supplying f to the minimum value circuit 16 and an output selected by supplying the reference voltage V ref applied to the output and power supply terminal 7 of the minimum value circuit 14 to the maximum value circuit 18. By adding the signals in an adding circuit 19, a correlation signal is generated in which the levels of the first and second signals are controlled, and the correlation signal is outputted from an output terminal 20.

Further, the intermediate value circuit shown in FIG. 9 has three input terminals 21
, 22. Among the second and third signals inputted to 23, the first and second signals are supplied to the maximum value circuit 24,
After providing the second and third signals to maximum value circuit 25 and the third and first signals to maximum value circuit 26 to select the respective maximum value components, each maximum value circuit 24.25. 26
By supplying the output to the minimum value circuit 27, the intermediate value components of the first to third signals are taken out,
8.

Here, by using the correlator circuit and the intermediate value circuit configured as described above, a luminance signal carrying chrominance signal separation circuit as shown in FIG. 10 can be constructed. That is, the composite image signal supplied to the input terminal 29 is delayed by one horizontal line in the IH delay circuits 30 and 31, and then supplied to the matrix circuit 32, whereby the signals before and after the H delay circuit 30 are a first color signal is generated based on
A second color signal is generated based on the signals before and after the IH delay circuit 310 and is output in a time-division manner. These first and second color signals are supplied to a correlator circuit 33 to become a level-controlled third color signal, which is then supplied to an intermediate value circuit 34.

Although not shown in FIG. 9, the intermediate value circuit 34 delays the third color signal output from the correlator circuit 33 by a predetermined amount and divides it into three parts. The intermediate value component of a color signal is extracted as a color signal. Then, the color signal output from the intermediate value circuit 34 is taken out from the output terminal 35, and is added to the composite image signal delayed by the delay circuit 36 in order to adjust the processing time in the addition circuit 37 to obtain the luminance. A signal is generated and taken from output terminal 38.

Here, the minimum value circuits 14, 16.degree. 27 are constructed as shown in FIG. That is, Q1 in the figure is a PNP type transistor, the base of which is connected to a terminal 39 to which a constant voltage vH is applied. Further, the emitter of this transistor Q1 is connected to a power supply terminal 40 to which a positive voltage element B is applied via a resistor R1. Further, the collector of the transistor Q1 is connected to the output terminal 41 and to a common connection point between the emitters of the PNP transistors Q2 and Q3. Each of these transistors Q2. The bases of Q3 are respectively connected to input terminals 42.
43, and both collectors are connected to a power supply terminal 44 to which a negative voltage -B is applied.

Here, the voltages of input terminals 42 and 43 are respectively %Nnl
, Vin2, the voltage at the output terminal 41 is set to V out, and the emitter-coupled transistor Q2. The collector current of transistor Q1, which becomes the bias current of Q3, is assumed to be 2io. Then, if the voltages Vinl and Vin2 are at the same potential, the transistors Q2. An equal current 1o flows through Q3. Also, the voltage Vinl or the voltage Vin2
When the voltage rises to some extent (for example, about 100 mV), transistor Q2 is cut off and transistor Q
A current 2Io flows only through the terminal 3. Conversely, when the voltage V inl becomes lower than the voltage Vjn2, the transistor Q3 is cut off and the current 210 flows only through the transistor Q2.

By using a correlator circuit using the minimum value circuit configured as described above to form a luminance signal carrier chrominance signal separation circuit, there is an advantage that dot interference and cross color are reduced.

By the way, in an image filter that uses a correlator circuit using a minimum value circuit as described above, the characteristics of the correlator circuit greatly affect the overall characteristics, and the characteristics of the correlator circuit are determined by the characteristics of the minimum value circuit. Ru. However, since the characteristics of actual minimum value circuits are not ideal, problems arise in that dot interference and cross color remain in reality.

That is, in the minimum value circuit shown in FIG. 112, if the thermal voltage is Vt (approximately 26 mV at room temperature) and the emitter-collector saturation current of the transistor is Is, then
The output voltage Vout when the voltages Vinl and Vin2 are at the same potential is Vout-L'tnl+Vt-j7n (Io/
Is ), but the voltage V inl is the voltage V In2
The output voltage V out when it is lower than Vout −Vtt+l +Vt −in (21o
/Is). In other words, the conventional minimum value circuit is
The output voltage Vout essentially has an error of Vt-In2 (approximately 18 mV) depending on whether the input voltages Vtn1 and Vin2 are equal or not.

FIG. 12 and FIG. 13 each show the characteristics of the conventional minimum value circuit. These characteristics are the results obtained from a simulation using the circuit analysis program 5PICE. Figure 12 shows the DC (direct current) characteristics17, and Figure 13 shows a sine wave with one of the input terminals 42 and 43 fixed at a potential and the other. It shows the transient characteristics when inputting , where the voltage of the sine wave is low, the output voltage is slightly higher than the input terminal, and where the voltage of the sine wave is high, the output voltage is slightly higher than the fixed voltage. I can see why it's getting higher. Note that in this minimum value circuit, there is a DC (direct current) offset due to the voltage between the base and emitter of the transistor, but this DC offset is corrected for simplicity here.

In these characteristic examples, it is important that the output voltage is lower than the ideal when the input signal voltage is low, but even more important is that the output voltage becomes higher than the fixed voltage when the input signal voltage is high. This is a problem because when a correlator circuit or an intermediate value circuit is configured, this error leaks directly to the output and appears, causing dot interference and cross color.

Here, a correlator circuit configured using such a minimum value circuit has an error (leakage) of about 36 mV because the above-mentioned error occurs. Conventionally, the lack of performance of the correlator circuit related to the characteristics of the minimum value circuit has been addressed by increasing the signal amplitude. That is, if the signal amplitude is, for example, lVpp', the leakage component is 36 mV, so the relative ratio of the leakage component is about -30 dB, which is suitable for practical use.

However, there is currently a strong demand for the development of a minimum value circuit with higher accuracy. In addition, in conventional minimum value circuits, the minimum value of leakage voltage is fixed, so the only way to improve the characteristics is to increase the input signal amplitude, but on the other hand, there is also a restriction on the power supply voltage. There are limits to the improvement of characteristics, and it is becoming difficult to operate at low voltages.

(Problems to be Solved by the Invention) As described above, the conventional minimum value circuit has an inherent error, and therefore has the problem that high-precision performance cannot be expected.

Therefore, the present invention was made in consideration of the above circumstances, and has high-precision performance, making it possible to realize, for example, a high-precision correlator circuit, an intermediate value circuit, and a high-performance luminance signal carrier chrominance signal separation circuit. The first objective is to provide an extremely good minimum value circuit that satisfies the requirements.

[Configuration of the Invention (Means for Solving the Problems) The minimum value circuit according to the present invention includes a first transistor connected to the collector or the first reference potential point, and a transistor having the same polarity as the first transistor. A first emitter-coupled pair whose emitters are commonly connected to a second transistor connected to the base and collector, and a second reference potential point between the first emitter-coupled pair's common emitter connection point and the second reference potential point. a first current source that is interposed and connected; and a third transistor whose base and collector are connected with the same polarity as the second transistor and whose connection point is commonly connected to the base and collector connection point of the second transistor. and a fourth transistor having the same polarity as this third transistor and whose collector is connected to the first reference potential point, and a second emitter-coupled pair whose emitters are commonly connected; and this second emitter-coupled pair. The emitter common connection point and the second
a second current source inserted and connected between the reference potential point of the second transistor and a common connection point between the base-collector connection point of the second transistor and the base-collector connection point of the third transformer and the star; , a third current source interposed and connected between the reference potential point of the first transistor and the reference potential point of the first transistor; a fifth transistor connected to the f1 potential point; a fourth current source interposed and connected between the emitter of the fifth transistor and the first reference potential point; and a fourth current source having a polarity opposite to that of the first transistor. a sixth transistor, the base of which is connected to the emitter of the first transistor and whose collector is connected to a second reference potential point; a seventh transistor whose base is connected to the third reference potential point; a fifth current source interposed and connected between the emitter of the seventh transistor and the first reference potential point; an eighth transistor having a polarity opposite to that of the fourth transistor and having a collector connected to the base or emitter of the fourth transistor and having a collector connected to a second reference potential point; a ninth transistor whose collector is connected to the base of the transistor and whose collector is connected to the emitter of the seventh transistor; and a fifth transistor whose base is connected to the base of the eighth transistor and which has the same polarity as the ninth transistor and whose collector is connected to the emitter of the seventh transistor. a third emitter-coupled pair having a common emitter connection with a tenth transistor connected to the emitter of the third transistor;
a sixth current source interposed and connected between the emitter common connection point of the emitter-coupled pair and the second reference potential point; , the base-collector common connection point of each of the second and third transistors is configured as an output terminal.

(Function) According to the above-mentioned configuration, the effect of the third emitter-coupled pair makes it possible to forcibly correct the error that has conventionally occurred. This makes it possible to realize high-performance luminance signal carrier, color signal separation circuits, etc.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings. In FIG. 1, 45 is a first emitter-coupled pair consisting of a pair of NPN transistors Q1], Qi2 whose emitters are connected in common;
1 is its collector or power supply terminal 4 to which positive voltage element B is applied
6, and the transistor Q12 has its base and collector connected to form a diode configuration.

Further, a common emitter connection point of these transistors Qll and Q12 is connected to a power supply terminal 47 to which a negative voltage -B is applied via a constant current [111]. On the other hand, 4 in the figure
8 is a pair of NPN type transistors Q13. A second emitter-coupled pair formed by connecting Q14 in common with the emitters,
The collector of transistor Q14 is connected to the power supply terminal 46, and the base and collector of transistor Q13 are connected to form a diode configuration. Furthermore, these transistors Q13. The emitter connection point of Q14 is connected to the power supply terminal 47 via the constant current source I12. The base-collector connection points of the transistors Q12 and 013 are commonly connected to each other,
The common connection point is connected to the output terminal 49 and also to the power supply terminal 46 via the constant current source 113.

Here, the base of the transistor Q 1 ] is PN
It is connected to the connection point between the collector of the P-type transistor Q1.5 and the emitter of the PNP-type transistor Q16. The transistor Q], 5 has its emitter connected to the power supply terminal 46 via the constant current source 114, the transistor Q16 has its collector connected to the power supply terminal 47, and its base connected to the input terminal 50. Further, the base of the transistor Q],4 is connected to the connection point between the collector of the PNP type transistor Q17 and the emitter of the PNP type transistor 018.

This transistor Q17 has its emitter connected to the power supply terminal 46 via the constant current source 115, and the transistor 018 has its collector connected to the power supply terminal 47.
The base is connected to input terminal 51. And transistor Q15. The respective bases of Q17 are commonly connected, and the connection point thereof is connected to a voltage terminal 52 to which a constant voltage V)I is applied.

In addition, 53 in FIG. 1 is a pair of NPN type transistors Q.
19. This is a third emitter-coupled pair in which the emitters of Q20 are connected in common, and the common emitter connection point is connected to the power supply terminal 47 via the constant current source 116. Among these, the base of the transistor Q], 9 is commonly connected to the base of the transistor Q16, and the collector is connected to the emitter of the transistor Q], 7 and the constant current source 11.5.
connected to the connection point. Also, transistor Q
20 has its base commonly connected to the base of the transistor Q18, and its collector connected to the connection point between the emitter of the transistor Q1.5 and the constant current source 114.

Before explaining the circuit operation of this embodiment configured as described above, the circuit shown in FIG. 2, which is obtained by removing the third emitter coupling pair 53 from the circuit shown in FIG. 1, will be explained. I'll leave it there. The circuit shown in FIG. 2 constitutes a minimum value circuit like the conventional circuit shown in FIG.
This uses N-type transistors Qll to Q14. Then, the output current of the constant current source Ill~113 is 21
o, and the output current of the constant current sources 114 and 115 is I
Suppose that it is set to o.

Here, consider fixing the voltage V jn12 of the input terminal 51 to a constant potential and varying the voltage V 1nll of the input terminal 50. First, the voltage V 1nll, V
When 1n12 are at the same potential, all transistors Ql
]~A current IO equal to Q18 flows. If the base-emitter voltage of each transistor Q1.1~018 is Vhell~V'be1g, then the input terminal V1
n11. The relationship between V 1n12 and the output voltage V out is V out −V 1nll+ V belG−
V bell+ V be12- V 1n12+ V
belg −V be14±Vbe13. Furthermore, the type pressures Vbe11 to Vbelg between the .
t and the saturation current Is, and if the saturation current Is is equal for each transistor Qll~018, then Vout −Vinll+Vt −f) n (Io
/Is)Vt-In(Io/Is
)+Vt-I n (io/Is)-Vin
ll+Vt -nn (Io/Is)・
...(1), and the output voltage vout is Vt-1n (No/Is) higher than the input voltage V1nll.

Next, when the voltage Vin becomes lower than the voltage V1n12, the tra-shifter Q13 is cut off and the output voltage V
out is V out −V 1nll+ V belG
−V bell+V be12, or what must be noted here is that the transistors Qll to Q14 of the first and second emitter coupling pair 45°48
Since the main current flowing through the transistors changes depending on the voltage Vjnll, a voltage difference occurs between the base-emitter voltages Vbe11 to Vbe14 of these transistors Qll to Q14.

That is, if the voltage Vinll has now become low, the current flowing through the transistor Qll has become ■0-α, and the current flowing through the transistor Q12 has become No+α, the output voltage Vout is as follows: out = V jnll + v t - Ωn (Io/ l5)-V
t-1) n [(io-a)/Is]+Vt
-11n [(No +a)/Isco. Here, the output voltage Voutl when the input voltage V ir+11 is lower than the fixed voltage V 1n12 and the input voltage V jn
Output voltage V when ll is equal to fixed voltage V 1n12
When calculating the difference voltage with out2, V out l-V
out2 −Vt −M n E (No +a) / (Io
-α) E≧0 ・・
- (2), and when the input terminal V 1nll changes, an offset depending on the input voltage V 1nll occurs. Furthermore, since this offset is greater than or equal to 0, the essential offset that the circuit shown in FIG. 2 has is added to this offset.

On the other hand, the minimum value circuit of the embodiment shown in FIG.
Transistor Q19. Since it includes the third emitter coupling pair 53 made of Q20 and the constant current source 116, it operates so that the offset determined by the above equation (2) is canceled. That is, when the output current of each constant current source Ill to 116 is set to 21o, the input voltage V 1nll,
When V jn12 is at the same potential, all transistors Q
], The current flowing through 1 to Q20 is 0. In this case, the output voltage v out is equal to the above equation (1), and is expressed as Vout − Vinll + Vt l n (Io /
Is).

Next, the output voltage Vout when the voltage V1nll becomes lower than the voltage Vjn12 is calculated.In the circuit of the embodiment shown in FIG.
The current flowing through is also changing depending on the voltage v1nll. In other words, if the voltage V1nll decreases and the current flowing through the transistor Q17.9 becomes Io-α, then the current flowing through the transistor Q17. Q18. 1o+α for Q20
current flows. This causes transistor Q15. Q
Since the current of 1.6 is Io-α, the transistor Q1
The base-emitter voltage V belG of 6 is also the input voltage V
It changes depending on 1nll.

Therefore, the output voltage v out when the voltage V finll becomes lower than the voltage V 1n12 is \ out - Vinll + Vt - I n [(No - α) /
Is]-Vt-Iln[(Io-α)/I
s ]+Vt −II n [CIo 1α) /Is
].

Here, the input voltage V 1nll is the fixed voltage V 1n12
Output voltage Voutl when lower and input voltage V 1
Finding the difference voltage between the output voltage V out2 when nll is equal to the fixed voltage V 1n12, we get: VOut low Vout2 - Vt-gn [(Io '-, a>y' No
] ≧0・(3). Comparing the above equations (2) and (3), we can see whether the offset is the same in the above equation (3). α,
)co≧Vt-11n [(Io +a)/Ioco, and the offset of formula (3) that is added to the essential C offset of the circuit shown in FIG. 1 is the circuit shown in FIG. You can see that it is kept smaller than the actual size.

3 and 4 show the characteristics of the minimum value circuit shown in FIG. 1, respectively. These characteristics are the results obtained by simulation using the circuit analysis program 5PICE, and FIG. 3 shows the DC characteristics, and FIG. 4 shows the input terminal 50.
When one side of 51 is set to a fixed potential and a sine wave is applied manually to the other side! It shows the characteristic of 5 degrees. Comparing with the amount of offset generated in the conventional circuit shown in FIGS. 12 and 13,
It can be seen that the offset is extremely small in the example. Note that the current Io used in the above-mentioned simulation was set to 00 μA, and the essential offset of the circuit occurring between the input and output was corrected.

As described above, according to the above embodiment, it is possible to realize a highly accurate minimum value circuit with few errors (leakages).

Here, the circuit of the embodiment shown in FIG. 1 can be embodied as shown in FIG. That is, the constant current sources I], 4, 115 are replaced by resistors R14 and R15, and the constant current source 11.3 is replaced by a PNP type transistor Q21 and a resistor R13. This transistor Q21 has its base connected to the voltage terminal 52 and is biased. Further, the constant current source I
1. ] instead of the PNP type transistor Q22 and the resistor R11, and instead of the constant current source 112, a PNP type transistor Q22 and a resistor R11 are used.
A PNP type transistor Q23 and a resistor R13 are used, and a PNP type transistor Q23 is used instead of the constant current source 116.
4 and resistor R16 are used. These transistors Q22 to Q24 are biased by having their respective bases commonly connected to a voltage terminal 54 to which a constant voltage VL is applied.

Next, FIG. 6 shows a modification of the embodiment shown in FIG. 1, in which transistors Q19. Emitter digital resistors R17 and R18 are interposed and connected between the emitters of Q20. The curvature of the DC characteristic shown in FIG. 3 can be varied by changing the values of the emitter degeneration resistors R17 and R18. The circuit shown in FIG. 6 can also implement each of the constant current sources 111 to 116 as shown in FIG. 7.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and can be implemented with various modifications within the scope of the invention.

[Effects of the Invention] As detailed above, according to the present invention, it is possible to realize a high-precision correlator circuit, an intermediate value circuit, a high-performance luminance signal carrier chrominance signal separation circuit, etc., which have high-precision performance. It is possible to provide a very good minimum value circuit that makes it possible.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the minimum value circuit according to the present invention, FIG. 2 is a circuit diagram used to explain the operation of the embodiment, and FIGS. 3 and 4 are respectively Characteristic diagrams of the same embodiment, FIGS. 5 to 7 are circuit configuration diagrams showing modified examples of the same embodiment, and FIGS. 8 to 10 are block configuration diagrams each showing circuit examples using the minimum value circuit. , 1st
FIG. 1 is a circuit configuration diagram showing a conventional minimum value circuit, and FIGS. 12 and 13 are characteristic diagrams of the conventional circuit. 11.12...input terminal, 13, maximum value circuit, 14.
...Minimum value circuit, 15...Power terminal, 16...Minimum value circuit, 17...Power supply circuit, 18...Maximum value circuit, one...Addition circuit, 20 Output terminal, 21 to 23 people Horn end 1
-324~26 Maximum value circuit, 27-Minimum value circuit, 28
Output terminals, 2・Input terminals, 30. 31・IH delay circuit, 32・Matrix circuit, '33... Correlator circuit,
34 intermediate value circuit, 35 output terminal, 36 delay circuit,
37・Adder circuit, 38・Output terminal r-139 terminal, 40・
Power supply terminal, 41... Output terminal, 42.43 Input terminal, 44... Power supply terminal, 45... First emitter coupling pair, 46.47... Power supply terminal, 48... Second emitter coupling pair, 49...output terminal, 50.51...input terminal,
52 Voltage terminal, 53...Third emitter coupling pair, 54
...Voltage terminal. Applicant's agent Patent attorney Takehiko Suzue [V] Enter υIIIPi Fig. 3 EV] Teacher Yami Fig. 4 17-■... Fig. 8 Fig. 9 Fig. 11 Person 7'3N circumference Fig. 12! Tanya Figure 13

Claims (1)

[Claims] A first transistor whose collector is connected to a first reference potential point, and a base whose collector is connected to a first reference potential point and which has the same polarity as the first transistor.
a first emitter-coupled pair whose emitters are commonly connected to a second transistor whose collector is connected;
a first current source interposed and connected between the reference potential point of the second transistor, and a base-collector connected with the same polarity as the second transistor, the connection point being connected to the base-collector of the second transistor;
A second transistor whose emitters are commonly connected, a third transistor commonly connected to the collector connection point, and a fourth transistor having the same polarity as the third transistor and whose collector is connected to the first reference potential point. a second current source interposed and connected between the emitter common connection point of the second emitter-coupled pair and the second reference potential point; and a base of the second transistor. a third current source interposed and connected between a common connection point between a collector connection point and a base-collector connection point of the third transistor and the first reference potential point; a fifth transistor with polarity opposite to that of the first transistor, the base of which is connected to the collector and the base of which is connected to a third reference potential point; and the emitter of the fifth transistor and the first reference potential point. a fourth current source interposed and connected between the transistors; and a fourth current source having a polarity opposite to that of the first transistor, the base of which is connected to the emitter, and the collector of which is connected to the second reference potential point. a seventh transistor having a polarity opposite to that of the fourth transistor, the base of the fourth transistor being connected to the collector and the base being connected to the third reference potential point; and the seventh transistor a fifth current source interposed and connected between the emitter of the transistor and the first reference potential point; an eighth transistor connected to a second reference potential point; and an eighth transistor having the same polarity as the first transistor, having a base connected to the base of the sixth transistor and a collector connected to the emitter of the seventh transistor. A ninth transistor and a tenth transistor having the same polarity as the ninth transistor and having a base connected to the base of the eighth transistor and a collector connected to the emitter of the fifth transistor are connected in common at their emitters. and a sixth current source interposed and connected between the emitter common connection point of the third emitter-coupled pair and the second reference potential point, A minimum value circuit characterized in that the bases of the sixth and eighth transistors are respectively input terminals, and the base-collector common connection points of the second and third transistors are the output terminals. .