JPH03117008A - Current mirror circuit - Google Patents
Current mirror circuitInfo
- Publication number
- JPH03117008A JPH03117008A JP1254159A JP25415989A JPH03117008A JP H03117008 A JPH03117008 A JP H03117008A JP 1254159 A JP1254159 A JP 1254159A JP 25415989 A JP25415989 A JP 25415989A JP H03117008 A JPH03117008 A JP H03117008A
- Authority
- JP
- Japan
- Prior art keywords
- current
- transistor
- mirror circuit
- ratio
- base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
- 238000006243 chemical reaction Methods 0.000 claims abstract description 20
- 238000010586 diagram Methods 0.000 description 9
- 230000000694 effects Effects 0.000 description 8
- 230000003321 amplification Effects 0.000 description 4
- 238000003199 nucleic acid amplification method Methods 0.000 description 4
- 239000002131 composite material Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000003503 early effect Effects 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は電流ミラー回路に係シ、特にトランジスタの対
称性を利用した基本回路として用いられている複合電流
ミラー回路において特にトランジスタのｈＦＥとアーリ
ー効果の影醤に対しても高精度が得られかつ入出力の電
流比の設定範囲を広げたバイポーラ集積回路からなる回
路構成に関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to current mirror circuits, and in particular, to complex current mirror circuits that are used as basic circuits that take advantage of the symmetry of transistors. The present invention relates to a circuit configuration consisting of a bipolar integrated circuit that achieves high accuracy even with respect to effects and has a wide setting range of input/output current ratios.
第７図において、従来の電流ミラー回路は、ＰＮＰ）ラ
ンジスタＱ１．Ｑ２．Ｑａと、電流■□の流れる電流入
力端子１と、電流出力端子２と、共通端子３と、電流供
給源４とを含み、構成される。In FIG. 7, the conventional current mirror circuit consists of PNP) transistors Q1. Q2. Qa, a current input terminal 1 through which current ■□ flows, a current output terminal 2, a common terminal 3, and a current supply source 4.
従来から用いられている電流ミラー回路の一例を、第７
図に示す。ベースをトランジスタＱ１ト共通接続し、コ
レクタ・ベース間を短絡したトランジスタＱ２のコレク
タ側へ、トランジスタＱｓのエミッタを接続し、トラン
ジスタＱ のベースをトランジスタＱ１のコレクタに接
続して、電流入力端子１とし、トランジスタＱ３のコレ
クタを電流出力端子２とする構成である。トランジスタ
Ｑ□ｌＱ２のエミッタは短絡するが、各々抵抗を介して
共通端子３へ接続され、これは電流供給源４へ結合され
る。電流入力端子１に印加する電流を１１とし電流出力
端子２に流出する電流を１２とすると、それらの関係は
以下のように衣わされる。An example of a conventionally used current mirror circuit is shown in the seventh section.
As shown in the figure. The emitter of the transistor Qs is connected to the collector side of the transistor Q2 whose base is commonly connected to the transistor Q1 and the collector and base are shorted, and the base of the transistor Q is connected to the collector of the transistor Q1. , the collector of transistor Q3 is used as current output terminal 2. The emitters of the transistors Q□lQ2 are shorted but each connected via a resistor to a common terminal 3, which is coupled to a current source 4. Assuming that the current applied to the current input terminal 1 is 11 and the current flowing out to the current output terminal 2 is 12, the relationship between them is as follows.
但し、トランジスタＱｌ、Ｑ２の特性は同一であるとし
、エミッタ接地電流増幅率をβ、各々のコレクタ電流を
’Ｃ１＋ ＩＣ２とすると、次式が得られる。However, assuming that the characteristics of transistors Ql and Q2 are the same, and assuming that the common emitter current amplification factor is β and each collector current is 'C1+IC2, the following equation is obtained.
これら両式から、次式が得られる。From these two equations, the following equation can be obtained.
前記（１）式よシ、電流増幅率βが十分大きければ、出
力電流Ｉ２は入力電流■、にほぼ等しくなシ、β＝１０
０では０．０２％の誤差である。また、電流比を決定す
るトランジスタＱ１とトランジスタＱ２のコレクタ・エ
ミッタ間電圧■。は電流出力端子２の電位に関係なく、
ベース・エミッタ順方向電圧ＶＢＨによる定電圧が与え
られるので、トランジスタのアーリー効果による電流比
の変動が抑えられ、高精度の電流ミラー回路が得られる
。According to equation (1) above, if the current amplification factor β is sufficiently large, the output current I2 is approximately equal to the input current , β = 10.
At 0, the error is 0.02%. Also, the collector-emitter voltage ■ of transistor Q1 and transistor Q2 determines the current ratio. is regardless of the potential of current output terminal 2,
Since a constant voltage is provided by the base-emitter forward voltage VBH, fluctuations in the current ratio due to the Early effect of the transistor are suppressed, and a highly accurate current mirror circuit can be obtained.
しかし、第７図の電流ミラー回路は、電流比１対１の場
合に限シ前述の効果が得られ、電流比を自由に設定する
ことができないという欠点があシ、使用範囲が限定され
てしまう。However, the current mirror circuit shown in Fig. 7 can obtain the above-mentioned effect only when the current ratio is 1:1, and has the disadvantage that the current ratio cannot be set freely, which limits the range of use. Put it away.
第７図において、もしトランジスタＱ１をトランジスタ
Ｑ２のＮ倍のエミツタ面積比とし、トランジスタＱ２の
エミッタ電流に対し、Ｎ倍のエミッタ電流が流れる構成
とした場合には、前記の（１）式は次式となる。In FIG. 7, if the emitter area ratio of the transistor Q1 is N times that of the transistor Q2, and the emitter current is N times the emitter current of the transistor Q2, then the above equation (1) becomes as follows. The formula becomes
ここで、Ｎの値が１以外ではベース電流の補償効果がな
くな、？、（ｘ−Ｎ）の１倍された成分が電流比の誤差
として現れてくる。例えば、β＝１００でも、Ｎ＝２で
は０．９５％、Ｎ＝３では１．９％もの誤差が生じてし
まうことになる。Here, if the value of N is other than 1, the compensation effect of the base current disappears, and ? , (x-N) appears as an error in the current ratio. For example, even when β=100, an error of 0.95% occurs when N=2, and an error of 1.9% occurs when N=3.
本発明の目的は、前記欠点が解決され、高精度で、電流
比を広範囲に設定できるようにした電流ミラー回路を提
供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a current mirror circuit in which the above-mentioned drawbacks are solved and the current ratio can be set over a wide range with high precision.
本発明の構成は、第１のトランジスタおよび第２のトラ
ンジスタのベース同士およびエミッタ同士を互いに接続
して、その共通エミッタを電流供給源に接続し、前記第
１．第２のトランジスタの電流比をＮ対１（但しＮ〉１
）に設定し、前記第２のトランジスタのコレクタにエミ
ッタを接続した第３のトランジスタを設け、前記第１の
トランジスタのコレクタを電流入力端子に接続し、前記
−
第３のトランジスタのコレクタを電流出力端子とする入
出力電流比Ｎ対１の電流ミラー回路において、前記第２
のトランジスタのベース・コレクタ間に、２／（Ｎ＋１
）倍の変換比を有する第１の電流変換手段を介在させ、
前記第３のトランジスタのベースと前記電流入力端子と
の間に、Ｎ倍の変換比を有する第２の電流変換手段を介
在させたことを特徴とする。The configuration of the present invention is such that the bases and emitters of the first transistor and the second transistor are connected to each other, and their common emitters are connected to a current supply source. The current ratio of the second transistor is set to N to 1 (where N>1
), a third transistor is provided whose emitter is connected to the collector of the second transistor, the collector of the first transistor is connected to a current input terminal, and the collector of the third transistor is connected to a current output terminal. In a current mirror circuit with an input/output current ratio of N to 1, the second
2/(N+1) between the base and collector of the transistor
) a first current conversion means having a conversion ratio of
The present invention is characterized in that a second current conversion means having a conversion ratio of N times is interposed between the base of the third transistor and the current input terminal.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例の電流ミラー回路の基本回路
を示す回路図である。FIG. 1 is a circuit diagram showing a basic circuit of a current mirror circuit according to an embodiment of the present invention.
第１図において、本実施例の基本回路は、入力電流Ｉ□
に対して１／Ｎ倍の出力電流 １２を得ようとするもの
で、共通端子３にトランジスタＱ２とエミッタ面積Ｎ倍
のトランジスタＱ１のエミッタが接続され、ベースは共
通接続されている。共通ベースには、ベース電流の２／
（Ｎ＋ １ ）倍の成分を取シ出す第１の電流変換手段
１０が接続され、トランジスタＱ２のコレクタへの電流
経路と６−
なる。トランジスタＱ２のコレクタにはトランジスタＱ
３のエミッタが接続され、トランジスタＱ３のコレクタ
は、電流出力端子２として出力電流Ｉ２が出力される。In FIG. 1, the basic circuit of this embodiment has an input current I□
The purpose is to obtain an output current 12 that is 1/N times larger than that of the transistor Q2, and the emitters of a transistor Q2 and a transistor Q1 whose emitter area is N times larger are connected to a common terminal 3, and their bases are commonly connected. The common base has 2/2 of the base current.
A first current converting means 10 which extracts (N+1) times the component is connected and forms a current path 6- to the collector of the transistor Q2. A transistor Q is connected to the collector of transistor Q2.
The emitter of the transistor Q3 is connected to the collector of the transistor Q3, and the output current I2 is outputted to the collector of the transistor Q3 as a current output terminal 2.
トランジスタＱ３のベースは、ベース電流１１３をＮ倍
する第２の電流変換手段２゜を介して、トランジスタＱ
１のコレクタに接続され、その接続点を電流入力端子１
として、入力電流■□を与える構成となっている。The base of the transistor Q3 is connected to the transistor Q through the second current conversion means 2° which multiplies the base current 113 by N.
1, and its connection point is connected to the current input terminal 1.
The configuration is such that an input current of ■□ is given.
同様に、トランジスタのエミッタ接地電流増幅率をβ、
トランジスタＱｌ、Ｑ２の各々のコレクタ電流をＩＣ□
、■ｏ２、トランジスタＱ３のベース電流をより３とし
て、入力電流ｌ□と出力電流Ｉ２の関係を求めると、以
下のように表わされる。Similarly, the common emitter current amplification factor of the transistor is β,
The collector current of each of transistors Ql and Q2 is IC□
, ■o2, and the base current of the transistor Q3 is set to 3, and the relationship between the input current l□ and the output current I2 is expressed as follows.
工Ｃ１＝ Ｎ ＩＣ２ これら（３）式を解いて、 次式が得られる。Engineering C1= N IC2 Solving these equations (3), The following equation is obtained.
前記（４）式を前記（３）式へ代入して、次式が得られ
る。By substituting the above equation (4) into the above equation (3), the following equation is obtained.
以上のように、トランジスタＱｌ、Ｑ２の電流比Ｎと、
２つの電流変換手段１０．２０の係数Ｎが等しい場合に
は、前記（５）式が成立し、Ｎの値にかかわらず、第７
図の回路と同じ補償効果をもった高精度電流ミラー回路
を得ることができる。誤差成分は（１）式と同一の２／
（β２＋２β＋２）で与えられている。As described above, the current ratio N of transistors Ql and Q2 is
If the coefficients N of the two current conversion means 10.20 are equal, the above formula (5) is established, and regardless of the value of N, the seventh
A high-precision current mirror circuit with the same compensation effect as the circuit shown in the figure can be obtained. The error component is 2/ which is the same as in equation (1).
It is given by (β2+2β+2).
ここで前述の第１図の電流変換手段１０．２０の具体例
につき、第２図と第３図により説明する。A specific example of the current converting means 10.20 shown in FIG. 1 will now be described with reference to FIGS. 2 and 3.
第２図は第１の電流変換手段１ｏを最も基本的な電流ミ
ラー回路によ多構成したもので、エミッタとベースを共
通接続したトランジスタＱ□□、Ｑ０２のうち、トラン
ジスタＱｌｌのコレクタと共通ベースの接続点を入力端
子１１、トランジスタＱ□２のコレクタを出力端子１２
としている。トランジスタＱ□、のエミッタ面積をＱ□
２の２７（Ｎ−１）倍に設定することで、共通端子１３
と入力端子１１との電流比は、（Ｎ＋１）対２の関係に
なる。電流増幅率βを考慮して電流比を算出すると、（
Ｎ＋が生じる。Fig. 2 shows the first current converting means 1o configured in the most basic current mirror circuit. Among the transistors Q□□ and Q02 whose emitters and bases are commonly connected, the collector and common base of the transistor Qll are shown in Fig. 2. The connection point is the input terminal 11, and the collector of the transistor Q□2 is the output terminal 12.
It is said that Let the emitter area of transistor Q□ be Q□
By setting 27 (N-1) times 2, the common terminal 13
The current ratio between the input terminal 11 and the input terminal 11 is (N+1) to 2. When calculating the current ratio by considering the current amplification factor β, (
N+ occurs.
第３図は第２の電流変換手段２０を同様に電流ミラー回
路によ多構成したもので、第２図とは逆導電性のトラン
ジスタを用いている。トランジスタＱ２１のエミッタ面
積をＱ２２の１／（Ｎ−１）倍に設定することで、入力
端子２１と共通端子２３との電流比は、１対Ｎの関係に
なる。同じくβを考以上のように、第１図の回路を具体
化する際には、トランジスタＱ、 、Ｑ２の電流比Ｎと
、２つの電流変換手段１０．２０の係数とＮは、厳密に
致させることは難しい。In FIG. 3, the second current converting means 20 is similarly configured with a current mirror circuit, and uses transistors having conductivity opposite to those in FIG. 2. By setting the emitter area of the transistor Q21 to 1/(N-1) times that of Q22, the current ratio between the input terminal 21 and the common terminal 23 becomes 1:N. Considering β in the same way, as mentioned above, when embodying the circuit of Fig. 1, the current ratio N of the transistors Q, , Q2, and the coefficients and N of the two current conversion means 10.20 must be strictly It's difficult to make it happen.
そこで、第４図に示すように、第１の電流変換−ｆｆ＝
手段１０の係数をｎｌ 、第２の電流変換手段２０の係
数をｎ２として、入力電流１１と出力電流Ｉ２の関係を
求めると、次式が得られる。Therefore, as shown in FIG. 4, the relationship between the input current 11 and the output current I2 is determined by setting the coefficient of the first current conversion means 10 to nl and the coefficient of the second current conversion means 20 to n2. , the following equation is obtained.
・・・・・・・・・・・・・・・（６）係数ｎ□＋”２
は、前述のように第２図と第３図のような簡単な回路を
用いた場合でも数パーセントの値（例えばＮ＝２で、β
＝１００のとき、約１％）に収まるので、前記（６）式
は前記（５）式とほとんど同等となると考えてよい。従
って、設定すべき係数Ｎに対して、第２図において通常
発生する誤差を含む程度の係数ｎ□、ｎ２を実現するこ
とで、第１図で説明した本実施例の効果を得ることがで
きる。・・・・・・・・・・・・・・・(6) Coefficient n□+”2
As mentioned above, even when using simple circuits as shown in Figures 2 and 3, the value of β is a few percent (for example, when N = 2, β
= 100, the equation (6) can be considered to be almost equivalent to the equation (5). Therefore, the effect of this embodiment explained in FIG. 1 can be obtained by realizing coefficients n□, n2 that include the error that normally occurs in FIG. 2 for the coefficient N to be set. .
第５図は第１図の実施例のよシ具体的な一例を示した回
路図である。第５図において、本例は、第１図のうち２
つの電流変換手段１０．２０を第２図と第３図とで実現
した複合電流ミラー回路である。ＰＮＰトランジスタＱ
□ＩＱ２の共通ベース１０−
には、第２図で示した電流ミラー回路の共通端子１３が
接続され、トランジスタＱｌ’、Ｑ２のベース電流は入
力端子１１側に２ ／ （Ｎ ＋ ｔ ）倍の成分とな
って、トランジスタＱ３のエミッタへ分配される。残シ
の（Ｎ−１）／（Ｎ＋ｉ ）倍の成分は、出力端子１２
から流出させて、接地している。また、トランジスタＱ
３のベースには、第３図で示した電流ミラー回路の入力
端子２１が接続され、トランジスタＱ３のベース電流は
共通端子２３側からＮ倍されて、電流入力端子１へ流出
する。Ｎ倍するために必要な（Ｎ−１）倍成分は、出力
端子２２を介して電流供給源となる共通端子３から得て
いる。FIG. 5 is a circuit diagram showing a more specific example of the embodiment shown in FIG. In FIG. 5, in this example, two of FIG.
This is a composite current mirror circuit in which two current converting means 10.20 are realized by the combination of FIGS. 2 and 3. PNP transistor Q
□The common terminal 13 of the current mirror circuit shown in FIG. 2 is connected to the common base 10- of IQ2, and the base current of transistors Ql' and Q2 is 2 / (N + t) times larger on the input terminal 11 side. component and is distributed to the emitter of transistor Q3. The remaining component (N-1)/(N+i) times is output to the output terminal 12.
It flows out from the ground and is grounded. Also, transistor Q
The base of transistor Q3 is connected to the input terminal 21 of the current mirror circuit shown in FIG. The (N-1) times component required for multiplying by N is obtained from the common terminal 3, which serves as a current supply source, via the output terminal 22.
第６図は本発明の他の実施例の電流ミラー回路を示す回
路図である。第２図において、本実施例は、Ｎ＝２の場
合を示したものである。第１の電流変換手段１０には、
第２図の電流ミラー回路をマルチコレクタＰＮＰ）ラン
ジスタＱ□３で構成したものを用いている。また、トラ
ンジスタＱ□のコレクタと電流出力端子の間にはコレク
タ・ベースを短絡したトランジスタＱ４とトランジスタ
Ｑ５を直列に挿入して、トランジスタＱ□とトランジス
タＱ２とのコレクタ・エミッタ間電圧を一致させ、素子
特性の対称性を改善している。FIG. 6 is a circuit diagram showing a current mirror circuit according to another embodiment of the present invention. In FIG. 2, this embodiment shows the case where N=2. The first current conversion means 10 includes:
The current mirror circuit shown in FIG. 2 is constructed using a multi-collector PNP transistor Q□3. In addition, a transistor Q4 and a transistor Q5 with their collectors and bases shorted are inserted in series between the collector of the transistor Q□ and the current output terminal to match the collector-emitter voltages of the transistor Q□ and the transistor Q2. The symmetry of device characteristics is improved.
以上本実施例は、前記従来回路のベース電流補償効果を
、電流比１対１ではなく、入力電流に対して出力電流を
ｌ／Ｎ倍（但し、Ｎは１よシ大きい任意の実数）に設定
できる高精度電流ミラー回路であシ、第７図のトランジ
スタＱ２のベース・コレクタ間に２／（Ｎ＋１）倍の電
流変換手段を挿入シ、更にトランジスタＱ３のベース電
流をＮ倍の電流変換手段を介して、電流入力端子に与え
る構成となっている。As described above, in this embodiment, the base current compensation effect of the conventional circuit is increased by multiplying the output current by l/N (where N is any real number larger than 1) with respect to the input current, instead of the current ratio of 1:1. A high-precision current mirror circuit that can be set is used, and a 2/(N+1) current converting means is inserted between the base and collector of the transistor Q2 shown in Fig. 7, and a current converting means for N times the base current of the transistor Q3 is inserted. The configuration is such that the current is supplied to the current input terminal via the current input terminal.
以上説明したように、本発明は、電流ミラー回路を構成
するトランジスタのベース電流経路に、電流変換手段を
挿入することによシ、ベース電流による電流比の誤差を
補償し、高精度の電流ミラー回路を得ることができ、ま
た従来の高精度電流ミラー回路の電流比は１対１に限ら
れていたが、本発明は、入力に対して出力電流を減少さ
せる方向に任意の比率で設定することができるという効
果がある。尚、前記実施例では、ＰＮＰトランジスタが
主体となる回路を示したが、これをＮＰＮトランジスタ
に置き換えても、同様の効果が得られることは明白であ
る。As explained above, the present invention compensates for the error in the current ratio due to the base current by inserting a current conversion means into the base current path of the transistor that constitutes the current mirror circuit. In addition, the current ratio of conventional high-precision current mirror circuits was limited to 1:1, but the present invention allows the output current to be set at an arbitrary ratio in the direction of decreasing the input current. It has the effect of being able to Although the above embodiments have shown circuits mainly composed of PNP transistors, it is clear that similar effects can be obtained even if this is replaced with NPN transistors.
第１図は本発明の一実施例の電流ミラー回路の基本回路
を示す回路図、第２図と第３図は各々電流変換手段の具
体例を示す回路図、第４図は第１図の電流変換係数の影
餐を説明するための基本回路図、第５図は第１図の実施
例のよシ具体的な一例の回路図、第６図は本発明の他の
実施例の電流ミラー回路を示す回路図、第７図は従来か
ら用いられている高精度電流ミラー回路の基本回路図で
ある。
Ｑ□ｌＱ２？Ｑ３１Ｑ４＃Ｑ１１＋Ｑ１２１Ｑ１３・・
・ＰＮＰ）ランジスタ、Ｑ５＝Ｑ２□、Ｑ２□・・・Ｎ
ＰＮ ）ランジスタ、１０・・・第１の電流変換手段、
２０・・・第２の電流変換手段、１・・・電流入力端子
、２・・・電流出力端子、１３−
３・・・共通端子、
４・・・電流供給源。FIG. 1 is a circuit diagram showing a basic circuit of a current mirror circuit according to an embodiment of the present invention, FIGS. 2 and 3 are circuit diagrams showing specific examples of current converting means, and FIG. A basic circuit diagram for explaining the influence of the current conversion coefficient, FIG. 5 is a circuit diagram of a specific example similar to the embodiment of FIG. 1, and FIG. 6 is a current mirror of another embodiment of the present invention. The circuit diagram shown in FIG. 7 is a basic circuit diagram of a conventionally used high-precision current mirror circuit. Q□lQ2? Q31Q4#Q11+Q121Q13...
・PNP) transistor, Q5=Q2□, Q2□...N
PN) transistor, 10... first current conversion means,
20... Second current conversion means, 1... Current input terminal, 2... Current output terminal, 13-3... Common terminal, 4... Current supply source.
Claims (1)
ス同士およびエミッタ同士を互いに接続して、その共通
エミッタを電流供給源に接続し、前記第１、第２のトラ
ンジスタの電流比をＮ対１（但しＮ＞１）に設定し、前
記第２のトランジスタのコレクタにエミッタを接続した
第３のトランジスタを設け、前記第１のトランジスタの
コレクタを電流入力端子に接続し、前記第３のトランジ
スタのコレクタを電流出力端子とする入出力電流比Ｎ対
１の電流ミラー回路において、前記第２のトランジスタ
のベース・コレクタ間に、２／（Ｎ＋１）倍の変換比を
有する第１の電流変換手段を介在させ、前記第３のトラ
ンジスタのベースと前記電流入力端子との間に、Ｎ倍の
変換比を有する第２の電流変換手段を介在させたことを
特徴とする電流ミラー回路。The bases and emitters of the first transistor and the second transistor are connected to each other, the common emitters are connected to a current supply source, and the current ratio of the first and second transistors is set to N:1 (however, N >1), a third transistor is provided whose emitter is connected to the collector of the second transistor, the collector of the first transistor is connected to a current input terminal, and the collector of the third transistor is connected to a current input terminal. In a current mirror circuit with an input/output current ratio of N to 1 serving as an output terminal, a first current conversion means having a conversion ratio of 2/(N+1) is interposed between the base and collector of the second transistor, A current mirror circuit characterized in that a second current conversion means having a conversion ratio of N times is interposed between the base of the third transistor and the current input terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1254159A JP2613944B2 (en) | 1989-09-28 | 1989-09-28 | Current mirror circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1254159A JP2613944B2 (en) | 1989-09-28 | 1989-09-28 | Current mirror circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03117008A true JPH03117008A (en) | 1991-05-17 |
| JP2613944B2 JP2613944B2 (en) | 1997-05-28 |
Family
ID=17261051
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1254159A Expired - Lifetime JP2613944B2 (en) | 1989-09-28 | 1989-09-28 | Current mirror circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2613944B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007198078A (en) * | 2006-01-30 | 2007-08-09 | Toyota Motor Corp | Mounting structure of externally attached frame unit and its mounting method |
| JP2011232931A (en) * | 2010-04-27 | 2011-11-17 | Rohm Co Ltd | Current generation circuit and reference voltage circuit using the same |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57113518U (en) * | 1980-12-29 | 1982-07-14 | ||
| JPS594305A (en) * | 1982-06-30 | 1984-01-11 | Toshiba Corp | Current mirror circuit |
| JPS63305606A (en) * | 1987-06-08 | 1988-12-13 | Mitsubishi Electric Corp | Constant current circuit |
-
1989
- 1989-09-28 JP JP1254159A patent/JP2613944B2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57113518U (en) * | 1980-12-29 | 1982-07-14 | ||
| JPS594305A (en) * | 1982-06-30 | 1984-01-11 | Toshiba Corp | Current mirror circuit |
| JPS63305606A (en) * | 1987-06-08 | 1988-12-13 | Mitsubishi Electric Corp | Constant current circuit |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007198078A (en) * | 2006-01-30 | 2007-08-09 | Toyota Motor Corp | Mounting structure of externally attached frame unit and its mounting method |
| JP2011232931A (en) * | 2010-04-27 | 2011-11-17 | Rohm Co Ltd | Current generation circuit and reference voltage circuit using the same |
| US8749219B2 (en) | 2010-04-27 | 2014-06-10 | Rohm Co., Ltd. | Current generating circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2613944B2 (en) | 1997-05-28 |
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