JP3381100B2 - amplifier - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an amplifier having a large dynamic range and a wide frequency band. 2. Description of the Related Art A circuit shown in FIG. 7 has conventionally been used as an amplifier circuit for an analog IC having a wide frequency band and a large dynamic range and has excellent operation characteristics.
This circuit comprises an input differential pair composed of transistors Q1 and Q2 and an emitter resistor Rin, constant current source transistors Q4, Q5 and Q6 connected to the emitters of Q1 and Q2 and the collector of Q2, and a load. A dotted line block (1) forming a resistor Ro, an output transistor Q3, a bias circuit for the input operation pair, and a dotted line block forming a constant current circuit for flowing a constant current I to each of the constant current source transistors ( 2) and the output transistor Q3
And a dotted line block (3) forming a bias circuit for determining the operating potential of the circuit. The amplification operation of this circuit will be described.
The input signal voltage Vin is converted to a signal current i so that i = Vin / Rin in the input operation pair, and the current I +
The current I-i flows through i and Q2. On the other hand, since the constant current I is flowing through the constant current source transistor Q6, a signal current i that is the difference between the current I flowing through Q6 and the current Ii flowing through Q2 flows through the load resistor Ro. As a result, an output voltage Vout of Vout = RoＲi = Vin ・ (Ro / Rin) is generated and output via the output transistor Q3 of the emitter follower. In the dotted block (2), R
7 is set to be equal to the resistance values of R4 and R5 to form a current mirror circuit.
The current I having the same magnitude as the constant energizing current I set in the above is supplied to Q4 and Q5. Further, the resistance value of R8 is made equal to the resistance value of R7, and Q8
The current I is also applied to Qa, so that the current I of the same magnitude is applied to Qa. Here, the resistance value of Ra is further changed to R6.
And the current I is caused to flow through Q6 by the current mirror function. Note that Q9 and R9, and Qc and Rc are for compensating the base current in each current mirror circuit. [0005] Considering the dynamic range of the conventional amplifier circuit described above,
The upper limit of the output voltage Vout is V which is lower than the power supply voltage Vcc by the minimum voltage drop (about 1 V) by the constant current source Q6.
cc-1 (V), and the lower limit is the base potential of Q2 (approximately の of Vcc). Therefore, the maximum amplitude Vomax of the output voltage is Vomax = (Vcc-1) −Vcc / 2 = ( Vcc / 2) -1 (V) (1) Therefore, when operating with the power supply voltage at 9 V, 3.5 Vpp is obtained as the value of Vomax. [0006] In recent years, with the miniaturization, measurement, and low power consumption of electronic devices, low voltage operation of analog ICs has been promoted. However, when the above-mentioned conventional circuit is operated with a power supply voltage of 5 V as is often used recently, from the equation (1), Vomax is 1.5 Vp
p and a sufficient dynamic range cannot be secured. That is, lowering the power supply voltage causes signal waveform distortion and deterioration of SN characteristics, and there is a problem that it is difficult to achieve both a lower power supply voltage and a sufficient dynamic range. In terms of frequency characteristics, load resistance Ro and stray capacitance (mainly PN for constant current source)
LP composed of P transistor Q6's collector capacitance)
There is a problem that the level in the high frequency range is reduced by F and the Miller effect caused by the occurrence of the signal voltage amplitude at the collector of Q2 of the input differential pair at the time of differential input. [0007] An amplifier according to the present invention comprises an input differential pair having a pair of transistors to which an input signal is input, and an input differential pair between each emitter of the pair of transistors and ground. A pair of connected constant current sources, a first resistor connected between a collector and a power supply of one of the pair of transistors, and a collector connected to a collector of the one transistor. A first transistor having an emitter connected to ground via a resistor, a base connected to the collector of the first transistor, and a emitter connected to ground via a first constant current source. Two transistors, a second constant current source connected to the emitter of the second transistor via a constant voltage drop circuit, the second constant current source and the constant voltage drop circuit A second resistor connected between the base of the first transistor and a third constant current source connected between the base of the first transistor and ground; A third transistor having a base connected to the first transistor and having a load connected between the collector and a power supply for extracting an output signal;
It has. A collector is connected to a collector of one of a pair of transistors to which an input signal is inputted, and an emitter is connected to the ground via a resistor. The first transistor and the third transistor, whose bases are connected to each other, form a current mirror circuit. The current mirror circuit allows the connection point between the constant voltage drop circuit and the second constant current source and the third transistor to be connected. The DC operation level is reduced by the voltage drop due to the second resistor connected between the bases of the first transistor, and the dynamic range of the output is set large. FIG. 1 shows an embodiment of an amplifier according to the present invention. In this figure, the same circuit elements as those used in FIG. 7 are denoted by the same reference numerals. Dotted blocks (1) to (3) represent the same circuits as those in FIG. 7, and details of the internal circuit configuration are omitted. As shown, the amplifier circuit includes a constant current source transistor Qg and a diode ladder (4) connected to the collector side of the transistor Q1 in the input operation pair, a current mirror circuit (5), a constant current source transistor Qh, and the like. It is characterized in that it is provided. To explain the circuit operation, the emitter size of Qg is set to twice the emitter size of Qa in the dotted line block (2), and the resistance of Rg is set to the value of Ra in the dotted line block (2). By being set to ２, Qg operates as a constant current source through which a current of 2I flows. On the other hand, since the current of I + i according to the input signal to the base flows through Q1, as in the case of FIG. 7, the difference I−I between the two currents flows through the diode ladder (4).
i flows. This current is supplied to the current mirror circuit (5), and the current Ii flows through the transistor Qm. On the other hand, since the current I flows through the constant current source transistor Qh provided on the collector side of Qm due to the current mirror action with Qa in the dotted line block (2), the difference current i between these currents Flows into the load resistor Ro, and the resulting output voltage Vout (= Ro · i = Ro · V
in / Rin) is output from the emitter side of Q3. In this amplifier circuit, a diode D
The anode voltage of No. 1 is a value which is higher than the collector voltage of Qk by a forward voltage drop of two diodes, and
The collector-emitter voltage of 1 is set, but by changing the number of stacked diodes as necessary,
The collector-emitter voltage of Q1 can be set optimally.
Further, by making the value of Rk sufficiently smaller than the value of Rin, the fluctuation of the collector voltage of Qk due to the input voltage Vin is suppressed, the anode voltage of D1 is stabilized, and the generation of a signal voltage at the collector of Q1 is suppressed. Therefore, deterioration of the frequency characteristics due to the mirror effect can be avoided. Regarding the dynamic range, the maximum voltage amplitude Vomax appearing at the load of this amplifier circuit is shown.
Is the value obtained by subtracting the current mirror component in the dotted line block (5) and the voltage drop component (both about 1 V) in the constant current source transistor Qh from the operating voltage Vcc, so that Vomax = Vcc−2 (V). When the voltage is 5 V, a voltage amplitude of about 3 V is obtained. That is, as compared with 1.5 V of the conventional circuit of FIG.
A double dynamic range is obtained. As described above, in this amplifier circuit, no voltage amplitude is generated from the time when the input voltage Vin is converted to the current i in the differential pair to the time when the input voltage Vin is converted to the output voltage Vout in the load resistor Ro. The LPF is not formed due to the stray capacitance in the intermediate route, so that the deterioration of the frequency characteristic can be suppressed. Then, the output voltage is converted into the output voltage by the load resistor Ro capable of extracting the largest voltage amplitude, so that the dynamic range of the circuit can be widened and an output with excellent distortion characteristics and SN characteristics can be obtained. The diode ladder (4) may be constituted by a combination of transistors as shown in FIG. In this configuration, the current I from the collector of Q1
-I flows as the collector current of Qo and flows into the current mirror circuit (5) as the emitter current. And
The collector potential of Q1 is 2 Vbe higher than the collector potential of Qk.
(Approximately 1.4V) It is fixed to the increased voltage. In this configuration, as compared with the diode ladder (4) of FIG. 1, the influence of the third-order distortion of the current in the diode does not appear, so that the distortion characteristic is improved accordingly. In the current mirror circuit (5), the transistor Qm is replaced by a transistor Qp having an emitter size of n times, and the resistor Rm on the emitter side is replaced by a resistor Rp having a resistance value of 1 / n. The configuration may be changed as in the current mirror circuit (7) shown in FIG. 2B so that the current mirror circuit multiplies the current by n times. The emitter size is set to n of Qa so that the constant current source transistor Qr on the output side of the current mirror circuit (7) also flows n times the current nI.
The resistance value on the emitter side is set to 1 / n of Ra. With this configuration, it is possible to flow n times the signal current ni to the load resistor Ro, and the gain can be increased n times as compared with the case of FIG. In order to obtain the same gain as in the case of FIG.
/ N, the cutoff frequency of the LPF formed by Ro and the stray capacitance increases, and the frequency characteristics can be improved. In each of the circuit configurations described above, only one collector current of the input differential pair is used. Instead, the current efficiency is doubled by using both collector currents. Is also possible. An example of the configuration in this case will be described with reference to FIG. In this circuit configuration, currents I + i and I-i are drawn into the diode ladder from each collector side of the input differential pair, and the former current I + i is fed to Qk as a reference current of the current mirror circuit (5). A current I + i flows through the collector of Qm. A constant current source transistor Qw through which a current 2I flows is provided on the collector side of Qv of the current mirror circuit (8), and by connecting the collector of Qm and the collector of Qv, the current 2 is supplied to Qv.
Flow I-2i. This current is turned back by the current mirror function to cause the current 2I-2i to flow through Qu and the current 2I to flow through the constant current source transistor Qx on the collector side of Qu, thereby doubling the signal current 2i through the load resistance Ro. Flow. In this circuit, the same gain as in FIG. 1 can be obtained by reducing the value of Ro to １ ／, and the frequency characteristics can be improved as in [B] of FIG. By adopting the circuit configuration described above, a large dynamic range can be realized without deteriorating frequency characteristics due to stray capacitance, but in practice, when a relatively large current flows through the current source, for example, FIG. When the current flowing through the transistor Qg in 1 is set to about 1 mA, the influence of the stray capacitance cannot be ignored and the frequency characteristics deteriorate. That is, the current source circuit constituted by the PNP transistor is not suitable for a large current operation. Therefore, next, an embodiment in which such a current source using a PNP transistor is not used on the output side of the input differential pair will be described. FIG. 4 shows the circuit configuration of this embodiment. First, the DC operation of this circuit will be described. In a DC balanced state, half of the 2Ix current Ix supplied from the current source 2 flows to the current source 1 via the resistor Rq. Half of the current Ix is Qq and Qz
Flows through. On the other hand, since the current 2Ix flows through the current source 3, the current Ix also flows through Qb. That is, Q at equilibrium
Each of the emitter currents of b, Qz and Qq is Ix. If the DC current flowing through the resistor R1 at this equilibrium is Io, the DC current flowing through Qe is Io-I. Here, the DC potential at the base of Qb is V3,
Assuming that the DC potential of Qq is V4, V4 = R2 × (Io−I) + Vf (Qe) + Rq × Ix (1) V3 = Vcc−R1 × Io (2) (where Vf is the transistor This is a base-emitter voltage, and is expressed as Vf = (kT / e) ln (Is / Io) using Boltzmann constant k, electron charge e, absolute temperature T, junction saturation current Is, and emitter current Io. ). Also, V3 = V4−Vf (Qq) −Vf (Qz) + Vf (Qb) (3) always holds between V3 and V4. Then, by substituting the equations (1) and (2) into the equation (3), Vcc−R1 × Io = R2 × (Io−I) + Rq × Ix + Vf (Qe) −Vf (Qq) −Vf ( Qz) + Vf (Qb) (4) where Qb, Qz,
Since the emitter currents of Qq are equal, Vf (Qq) = Vf (Q
z) = Vf (Qb) holds, and the value of Vf (Qe) is also considered to be substantially equal to these values. Therefore, the DC current Io-I flowing through Qe can be calculated from the equation (4) as follows: Desired. Io−I = (Vcc−R1 × I−Rq × Ix) / (R1 + R2) (5) Each of the terms on the right side of the equation (5) is a constant term. Io-I can be adjusted freely. In this circuit, since the same resistor R2 is connected as the emitter-side resistor of Qe and Q3, Qe
And Q3 constitute a current mirror circuit. As a result, the DC voltage of the output Vout becomes Vcc-R3 × (Io-
By adjusting the DC current Io-I, the value of the DC voltage can be set to a value that can obtain a sufficiently large dynamic range. Further, since the output Vout in this circuit is of an NPN collector-out type, the same output characteristics as in a case where the output is directly obtained by direct collector-out in a normal differential amplifier composed of NPN transistors can be obtained. Note that the value of Vf (Qe) is strictly defined as Vf (Qe).
Since the DC current differs from the value of f (Qq) or the like, the DC current in equation (5) has a temperature fluctuation based on this error, but the emitter current Io-I of Qe is equal to the emitter current Ix of Qq or the like. If set, the above equation (5) can be strictly satisfied, and the temperature characteristics are stabilized. The condition for satisfying this is expressed by the following equation by setting the value of equation (5) as Ix. Ix = (Vcc-R1 × I) / (R1 + R2 + Rq) (6) The DC operation at the time of equilibrium has been described above. It can be understood that the operation converges to such an equilibrium state at the time of startup as follows. . For example, at startup, V4> V3 + Vf
If there is an unbalanced state such that
In the equilibrium state, V4 =
V3 + Vf holds), a current of Ix or more flows through Qq and Qz, and a current of Ix or less flows through Rq. As a result, the emitter current of Qe decreases, the current Io of R1 also decreases, and the base potential of Qb. V3 increases and approaches an equilibrium state. Further, if an unbalanced state is established such that V4 <V3 + Vf is satisfied, a current of Ix or more flows to Qb and a current of Ix or less flows to Qq and Qz. The current flows, the emitter current of Qe increases, and the current Io of R1 also increases. As a result,
The base potential V3 of Qb decreases and approaches an equilibrium state. Next, the AC operation will be described. With respect to the signal current i (= Vin / Rin) generated in the input differential pair Q1 and Q2 by the input signal Vin, the output voltage Vout
Is given by: Vout = Vcc−R3 × (Io−I + i) = Vcc−R3 × (Io−I) −Vin × R3 / Rin, so that the output signal is obtained as a signal whose gain is R3 / Rin and whose phase is inverted. . Strictly speaking, a voltage variation due to the signal current i occurs in V3 and V4, but the value of the voltage drop resistor Rq in this circuit is sufficiently larger than the values of the resistors R1 and R2. By setting, the above-mentioned variation becomes negligibly small. In FIG. 4 described above, the value of the current flowing through the current source 1 is set to 電流 of the value of the current flowing through the current source 2 in order to simplify the description of the operation. It is not necessary to limit, and more generally, each current value of the current sources 1 to 3 can be set as shown in FIG. If the current values of the respective current sources are set as shown in this figure, in an equilibrium state, the DC current flowing through Qq and Qz and the DC current flowing through Qb have the same value Is. In this circuit Io-
I is given by the following equation. Io-I = (Vcc-R1.times.I-Rq.times.It) / (R1 + R2) (7) Here, in order to eliminate the error relating to Vf, the value of Io-I may be set to Is. The condition that satisfies this is expressed by the value of It as follows. It = [Vcc−R1 × I− (R1 + R2) Is] / Rq (8) In FIG. 4, the current mirror circuit is formed by equalizing the resistances of the emitters of Qe and Q3 as described above. However, such a current mirror circuit is not necessarily required. In short, it is sufficient that the dynamic range of Vout can be set large by lowering the DC operation level of Q3 by the voltage drop due to Rq. Finally, an embodiment in which an operational amplifier is configured by applying the circuit of FIG. 3 will be described. FIG. 6 shows a circuit configuration of this embodiment. The circuit shown in this figure corresponds to the input resistance R in the circuit of FIG.
The gain as an operational amplifier is realized by setting in to “0” and making the load resistance Ro infinite (no connection). Like the amplifier described in FIGS. It is characterized by a wide operating frequency range, a large output dynamic range, and excellent distortion characteristics and SN characteristics. Note that C1 provided on the base side of the output transistor Q3 is a transmission preventing capacitor. As described above, according to the present invention, the collector is connected to the collector of one of the pair of transistors to which the input signal is input, and the emitter is connected to the ground via the resistor. A current mirror circuit including a first transistor and a third transistor having a base connected to each other provides a connection point between a constant voltage drop circuit and a second constant current source and a base of the first transistor. Since the DC operation level of the third transistor is reduced by the voltage drop due to the second resistor connected therebetween, and the dynamic range of the output can be set large, a large current flows on the output side of the input differential pair. PN not suitable for operation
With a configuration that does not use a current source using a P-transistor, an amplifier having a large dynamic range can be realized without deteriorating frequency characteristics due to stray capacitance.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing a first embodiment of an amplifier according to the present invention. FIG. 2 is a diagram illustrating another configuration example in the embodiment. FIG. 3 is a circuit diagram showing a second embodiment of the amplifier according to the present invention. FIG. 4 is a circuit diagram showing a third embodiment of the amplifier according to the present invention. FIG. 5 is a diagram showing another configuration example in the third embodiment. FIG. 6 is a circuit diagram showing an embodiment of the operational amplifier according to the present invention. FIG. 7 is a diagram showing a circuit configuration of a conventional amplifier. [Description of Signs] (1), (3): bias setting circuit, (2): current setting circuit for constant current source, (4): diode ladder,
(5), (7), (8) ... current mirror circuit,

────────────────────────────────────────────────── (5) References JP-A-60-196004 (JP, A) JP-A-64-49305 (JP, A) JP-A-5-267954 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) H03F 3/45 H03F 3/343

Claims (1)

(57) Claims: (1) An input differential pair including a pair of transistors to which an input signal is input; and (2) Between each emitter of the pair of transistors and ground. (3) a first resistor connected between the collector of one of the pair of transistors and a power supply; and (4) a collector of the one of the transistors. A first transistor whose collector is connected to the first transistor and whose emitter is connected to the ground via a resistor; and (5) a base is connected to the collector of the first transistor and the emitter is connected to the first constant current. A second transistor connected to ground via a source; (6) a second constant current source connected to the emitter of the second transistor via a constant voltage drop circuit; and (7) the second transistor. Constant current source and (8) a third resistor connected between the base of the first transistor and ground, and a second resistor connected between the connection point with the constant voltage drop circuit and the base of the first transistor. And (9) a third transistor having a base connected to the first transistor and a load connected between the collector and the power supply for extracting an output signal. An amplifier, comprising: