JPH04158555A - Chip carrier type semiconductor device - Google Patents

Chip carrier type semiconductor device

Info

Publication number
JPH04158555A
JPH04158555A JP2283915A JP28391590A JPH04158555A JP H04158555 A JPH04158555 A JP H04158555A JP 2283915 A JP2283915 A JP 2283915A JP 28391590 A JP28391590 A JP 28391590A JP H04158555 A JPH04158555 A JP H04158555A
Authority
JP
Japan
Prior art keywords
semiconductor
pellet
recess
glass epoxy
chip carrier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2283915A
Other languages
Japanese (ja)
Inventor
Masahide Murakami
村上　正秀
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2283915A priority Critical patent/JPH04158555A/en
Publication of JPH04158555A publication Critical patent/JPH04158555A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate

Landscapes

  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To enable reduction of the thickness of a chip carrier to about a half by a method wherein a semiconductor IC pellet is mounted on and connected to a board wherein recessed parts are formed in a stepped shape and epoxy resin is filled up in the part. CONSTITUTION:Recessed parts are formed in a stepped shape in a glass epoxy board 1 and the lower recessed part (second recessed part) is made in a depth being equal substantially to the thickness of a semiconductor IC pellet, while the upper recessed part (first recessed part) is formed to be deeper than the height of loops of Au wires 4. A semiconductor IC pellet 2 is mounted on the glass epoxy board 1 and bonding pads 3 formed on the peripheral part of the bottom surface of the upper recessed part and the semiconductor IC pellet 2 are connected by Au wires 4. The bonding pads 3 are led out to a side electrode 6. Besides, epoxy resin 5 is filled up so that it is as high as the surface of the glass epoxy board and has a flat surface.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、チップキャリア型半導体装置に関し、特にガ
ラスエポキシ基板上に半導体ＩＣペレットが搭載されて
形成されるチップキャリア型半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a chip carrier type semiconductor device, and particularly to a chip carrier type semiconductor device formed by mounting a semiconductor IC pellet on a glass epoxy substrate.

〔従来の技術〕[Conventional technology]

従来のチップキャリア型半導体装置は、第３図のように
ガラスエポキシ基板１上に半導体ＩＣペレット２が搭載
されて、Ａｕワイヤ４で半導体ＩＣペレットとガラスエ
ポキシ基板上のボンディングパッド３とを接続する。そ
の後でエポキシ樹脂５をポツテングにより半導体ＩＣペ
レットとＡｕワイヤを保護する為に覆うように塗布して
形成している。In a conventional chip carrier type semiconductor device, as shown in FIG. 3, a semiconductor IC pellet 2 is mounted on a glass epoxy substrate 1, and the semiconductor IC pellet is connected to a bonding pad 3 on the glass epoxy substrate with an Au wire 4. . Thereafter, an epoxy resin 5 is applied by potting to cover the semiconductor IC pellet and the Au wire in order to protect them.

または、第４図のようにガラスエポキシ基板１上に半導
体ＩＣペレット２を搭載して、Ａｕワイヤ４で半導体Ｉ
Ｃペレットとガラスエポキシ基板上のボンディングパッ
ド３とを接続する。その後、樹脂枠７を接着剤でガラス
エポキシ基板に貼り付けてエポキシ樹脂５を樹脂枠内に
充填して、半導体ＩＣペレットとＡｕワイヤを覆うこと
により形成している。Alternatively, the semiconductor IC pellet 2 is mounted on the glass epoxy substrate 1 as shown in FIG.
The C pellet and the bonding pad 3 on the glass epoxy substrate are connected. Thereafter, the resin frame 7 is attached to the glass epoxy substrate with an adhesive, and the epoxy resin 5 is filled into the resin frame to cover the semiconductor IC pellet and the Au wire.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来のチップキャリア型半導体装置では、カラ
スエポキシ基板の厚さ、半導体ＩＣペレットの厚さ、Ａ
ｕワイヤループとエポキシ樹脂の厚さの合計で全体の厚
さが決まる為、強度及び工程能力を考えると１．５ｍｍ
以下の厚さにすることは困難であり、最近の超薄型化に
対応できなくなるという問題点があった。また、半導体
ＩＣペレットの表面とガラスエポキシ基板上のボンディ
ングバット面と段差がある為、Ａｕワイヤのエッヂタッ
チを防ぐのにある程度半導体ＩＣペレットより距離をお
いてボンディングパッドを形成する必要があり、小型化
の防げになっていた。In the conventional chip carrier type semiconductor device described above, the thickness of the glass epoxy substrate, the thickness of the semiconductor IC pellet, and the
Since the total thickness is determined by the total thickness of the u-wire loop and the epoxy resin, it is 1.5 mm considering strength and process capacity.
It is difficult to reduce the thickness below, and there is a problem in that it cannot respond to the recent trend toward ultra-thinness. In addition, since there is a level difference between the surface of the semiconductor IC pellet and the bonding butt surface on the glass epoxy substrate, it is necessary to form the bonding pad at a certain distance from the semiconductor IC pellet to prevent the edge touch of the Au wire. This was to prevent it from becoming a problem.

〔課題を解決するための手段〕[Means to solve the problem]

本発明のチップキャリア型半導体装置は、第１の凹部、
前記第１の凹部の底部に設けられた第２の凹部および前
記第１の凹部の底部のうち前記第２の四部の設けられて
いない部分に設けられたボンディングパッドを有するガ
ラスエポキシ基板と、前記第２の凹部に搭載された半導
体ＩＣペレットと、前記ボンディングパッドと前記半導
体ＩＣペレットの接続端子との間を結ぶ金属ワイヤと、
前記第１．第２の凹部を埋めるエポキシ樹脂充填部材と
を含むというものである。The chip carrier type semiconductor device of the present invention includes a first recess;
a glass epoxy substrate having a second recess provided at the bottom of the first recess and a bonding pad provided at a portion of the bottom of the first recess where the second four parts are not provided; a metal wire connecting a semiconductor IC pellet mounted in a second recess, and the bonding pad and a connection terminal of the semiconductor IC pellet;
Said 1st. and an epoxy resin filling member that fills the second recess.

（実施例〕 次に本発明について図面を参照して説明する。(Example〕 Next, the present invention will be explained with reference to the drawings.

第１図（ａ）は本発明の第１の実施例を示す平面図で、
第１図（ｂ）は第１図（ａ）のＸ−Ｘ線断面図である。FIG. 1(a) is a plan view showing a first embodiment of the present invention.
FIG. 1(b) is a sectional view taken along the line X--X of FIG. 1(a).

ガラスエポキシ基板１は階段状に凹部が形成されており
、下の凹部（第２の凹部）は半導体ＩＣペレット２の厚
さとほぼ同じ深さたとえば０．４ｍｍで作られており、
上の凹部（第１の凹部）はＡｕワイヤ４のループの高さ
より深く、たとえば０．２ｍｍに形成されている。ガラ
スエポキシ基板１上に半導体ＩＣペレット２を搭載し、
上の凹部の底面の周辺部上に形成されたボンディングパ
ッド３と半導体ＩＣペレット２とをＡｕワイヤ４で接続
する。ボンディングパッド３はガラスエポキシ基板１の
内部配線により、外部との接続に使用される側面ｔｉ６
に引き出されている。又、エポキシ樹脂５がガラスエポ
キシ基板の表面と同じ高さで表面が平らになるように充
填されている。The glass epoxy substrate 1 has step-shaped recesses, and the lower recess (second recess) is made to have a depth that is approximately the same as the thickness of the semiconductor IC pellet 2, for example, 0.4 mm.
The upper recess (first recess) is deeper than the height of the loop of the Au wire 4, for example, 0.2 mm. A semiconductor IC pellet 2 is mounted on a glass epoxy substrate 1,
The bonding pad 3 formed on the periphery of the bottom of the upper recess and the semiconductor IC pellet 2 are connected with an Au wire 4. The bonding pad 3 is connected to the side surface ti6 used for connection with the outside by internal wiring of the glass epoxy substrate 1.
is being drawn out. Further, the epoxy resin 5 is filled so that the surface is flat and at the same height as the surface of the glass epoxy substrate.

第２図（ａ）は、本発明の第２の実施例を示す平面図で
、第２図（ｂ）は第２図（ａ）のＸ−Ｘ線断面図である
。FIG. 2(a) is a plan view showing a second embodiment of the present invention, and FIG. 2(b) is a sectional view taken along the line X--X of FIG. 2(a).

第２の実施例は、半導体ＩＣペレットを複数個搭載して
いる例で半導体ＩＣペレットを複数個搭載することによ
り、高機能化、高集積化が可能となる。The second embodiment is an example in which a plurality of semiconductor IC pellets are mounted, and by mounting a plurality of semiconductor IC pellets, higher functionality and higher integration are possible.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、階段状に四部が形成され
たガラスエポキシ基板状に半導体ＩＣペレットを搭載し
、金属ワイヤで接続を行い、エポキシ樹脂をガラスエポ
キシ基板の表面と同じ高さで表面が平らになるように、
充填することにより、金属ワイヤがエッヂタッチの心配
がなくなる為、金属ワイヤのループの高さを充填の１／
２〜１／３の約０．１ｍｍにおさえることができ、チッ
プキャリアの厚さを従来の約半分の０．８ｍｍにするこ
とが可能となる。又ボンディングパッドを半導体ＩＣペ
レットに近づけて形成することができる為、チップキャ
リアのサイズも従来と比較して面積比で１０％はど小さ
くできる。又、表面が平らに形成されているので実装基
板に自動搭載することも可能である。As explained above, in the present invention, semiconductor IC pellets are mounted on a glass epoxy substrate having four stepped parts, connected with metal wires, and the epoxy resin is placed on the surface at the same height as the surface of the glass epoxy substrate. so that it is flat,
By filling, there is no need to worry about the metal wire touching the edges, so the height of the metal wire loop should be reduced to 1/1 of the height of the filling.
The thickness of the chip carrier can be reduced to about 0.1 mm, which is 2 to 1/3 of the conventional thickness, and the thickness of the chip carrier can be reduced to 0.8 mm, which is about half of the conventional thickness. Furthermore, since the bonding pad can be formed close to the semiconductor IC pellet, the size of the chip carrier can be reduced by 10% in terms of area compared to the conventional method. Moreover, since the surface is formed flat, it is also possible to automatically mount it on a mounting board.

【図面の簡単な説明】[Brief explanation of drawings]

第１図（ａ）は本発明の第１の実施例を示す平面図、第
１図（ｂ）は第１図（ａ）のＸ−Ｘ線断面図、第２区（
ａ）は本発明の第２の実施例を示す平面図、第２図（ｂ
）は第２図（ａ）のＸ−Ｘ線断面図、第３図（ａ）は従
来例を示す平面図、第３図（ｂ）は第３図（ａ）のｘ−
Ｘ線断面図、第４図（ａ＞は従来例を示す平面図、第４
図（ｂ）は第４図（ａ）のｘ−Ｘ線断面図である６１・
・・ガラスエポキシ基板、２・・・半導体ＩＣペレット
、３・・・ボンディングパッド、４・・・Ａｕワイヤ、
５・・・エポキシ樹脂、６・・・側面電極、７・・・樹
脂“・　　　　　　　え、、Ａヶ、より原　晋茅　１　
図Ｃｂ＞ 第　２　圓（Ｌ） 箒　３　旧Ｃｂ） 第　＝７−　図Ｃｂ）FIG. 1(a) is a plan view showing the first embodiment of the present invention, FIG. 1(b) is a sectional view taken along the line X--X of FIG. 1(a), and FIG.
a) is a plan view showing the second embodiment of the present invention, FIG. 2(b)
) is a sectional view taken along the line X-X in FIG. 2(a), FIG. 3(a) is a plan view showing the conventional example, and FIG. 3(b) is a cross-sectional view taken along the
X-ray cross-sectional view, Figure 4 (a> is a plan view showing the conventional example, Figure 4
Figure (b) is a sectional view taken along the line x-X of Figure 4 (a).
...Glass epoxy substrate, 2...Semiconductor IC pellet, 3...Bonding pad, 4...Au wire,
5...Epoxy resin, 6...Side electrode, 7...Resin... Eh,, A, Shinkyo Yorihara 1
Figure Cb> 2nd circle (L) Broom 3 Old Cb) No. =7- Figure Cb)

Claims (1)

【特許請求の範囲】[Claims] 第１の凹部、前記第１の凹部の底部に設けられた第２の
凹部および前記第１の凹部の底部のうち前記第２の凹部
の設けられていない部分に設けられたボンディングパッ
ドを有するガラスエポキシ基板と、前記第２の凹部に搭
載された半導体ＩＣペレットと、前記ボンディングパッ
ドと前記半導体ＩＣペレットの接続端子との間を結ぶ金
属ワイヤと、前記第１、第２の凹部を埋めるエポキシ樹
脂充填部材とを含むことを特徴とするチップキャリア型
半導体装置。A glass having a first recess, a second recess provided at the bottom of the first recess, and a bonding pad provided at a portion of the bottom of the first recess where the second recess is not provided. an epoxy substrate, a semiconductor IC pellet mounted in the second recess, a metal wire connecting the bonding pad and the connection terminal of the semiconductor IC pellet, and an epoxy resin filling the first and second recesses. A chip carrier type semiconductor device comprising a filling member.
JP2283915A 1990-10-22 1990-10-22 Chip carrier type semiconductor device Pending JPH04158555A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2283915A JPH04158555A (en) 1990-10-22 1990-10-22 Chip carrier type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2283915A JPH04158555A (en) 1990-10-22 1990-10-22 Chip carrier type semiconductor device

Publications (1)

Publication Number Publication Date
JPH04158555A true JPH04158555A (en) 1992-06-01

Family

ID=17671844

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2283915A Pending JPH04158555A (en) 1990-10-22 1990-10-22 Chip carrier type semiconductor device

Country Status (1)

Country Link
JP (1) JPH04158555A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996025763A3 (en) * 1995-02-15 1996-11-07 Ibm Organic chip carriers for wire bond-type chips

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996025763A3 (en) * 1995-02-15 1996-11-07 Ibm Organic chip carriers for wire bond-type chips

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