JPH04157926A - Circuit for converting fixed length code into variable length code - Google Patents

Abstract

PURPOSE:To attain high speed processing by devising a circuit receiving a synthesis data of a couple of variable length codes sequentially and converting the data into a fixed length code of a prescribed length of bit number to be made efficient and simplified. CONSTITUTION:For example, the circuit converts a picture data comprising a Huffman code with a maximum bit length of 16-bit and an additional data with a maximum bit length of 11 bits into a fixed length data in 8-bit length. A 4-bit additional data is inputted from a ROM 24 to a shift circuit 28 via an FF 26, in which the data is shifted to high-order 4 bits and a data (c) is obtained by a selector SEa. A 10-bit picture data is outputted from a ROM 22 and synthesized with the data (c) via an FF 25, shifted to high-order bits by a shift circuit 27, the data (c) is obtained by a selector SEb and inputted to a shift circuit 30 via an FF 29. A preceding remaining bit number (6) is given to the circuit 30, and an output of a selector 31 receiving it is a data (f). High-order 8-bits in the data are outputted from a terminal 33, the rest is returned to the selector 31 as a remaining data (g). The clock of the FF 32 is fast.

Description

[Detailed Description of the Invention] [Objective of the Invention (Industrial Application Field) The present invention relates to a fixed-length conversion circuit for variable-length codes, and in particular, to a circuit for converting Huffman codes for image compression into fixed-length data. The present invention relates to a fixed length conversion circuit for variable long shot grain suitable for.

(Prior art) Recently, the progress of digital technology in electronic devices is remarkable.In the field of digital image processing technology, there has been remarkable progress in image compression technology. This technology is a technology that encodes images using a smaller bit ray in order to improve the efficiency of digital transmission and recording.This technology includes predictive encoding technology and orthogonal encoding technology. (Details in “TViillii (Elephant Multidimensional Signal Processing) by Takahiko Fukinuki, published by Hazama Kogyo Shimbunsha)” Q-
There is. Furthermore, even further image compression is possible by applying variable length encoding to the codes that cannot be compressed by these encoding methods. The variable length code fhi changes the width of the sign according to the frequency of occurrence of the sign, and compared to the fixed J1; Can be made smaller.

Next, a method for generating a Huffman code as an example of a variable length code will be explained with reference to FIG. FIG. 12(a) shows the Huffman code generation process, and FIG. 12(1)) shows the Huffman code tree.

Now, one fixed length code S1, S2,...,S
Let t be converted into a Huffman code. Figure 12 is L
-6 is shown as an example. First, these codes S
1 to S6 are arranged in descending order of occurrence frequency (occurrence probability). The occurrence probabilities of codes S1 to s6 are shown in Fig. 12(a).
As shown in , respectively, 035°0.20.0.15.0.
15.0.10.0.05, code sl to S6
are arranged in order. Next, the two codes with the lowest probability of occurrence are set as a set, and their combined probability (phase of the two probabilities of occurrence) is determined.

In FIG. 12, the occurrence probabilities of symbols S6 and S5 are small;
Its composite probability is 0.15.

Next, this set of codes and the other codes are rearranged in descending order of probability of occurrence (or composite probability). Next, the occurrence? i
7. The one with the smallest I rate (or composite probability) is then set as a new 1 silk, and the composite probability is determined. Thereafter, these processes are repeated until the combined probability becomes 1, as shown in FIG. 12(a).

Next, based on Figure 12 (a, ), Figure 12 ([)
) Create the code tree shown in Then, 0'' and ``]'' are assigned according to the branching of this code tree.The first
In Figure 2(b), the upper branch is 0''' and the lower branch is ''.
] ”.A Huffman code is obtained along this branching.For example, fixed-length code S4 passes through the “o” technique and the “ ] ” technique, as shown by the thick line in Figure 12. , and finally by passing through the branch of ``0'''', ``O''
] O"'. The Huffman codes of codes S1 to S6 thus obtained are shown in Table 1 below.

Table 1 As shown in Table 1, when the probability of occurrence is high, it is converted into a Huffman code with a short bit length, and when the probability of occurrence is low, it is converted into a Huffman code with a long bit length. As a result, the bit ray 1~ can be reduced overall.

Incidentally, recently, standardization of image data compression methods is being considered. According to this standard image compression technique, the first
As shown in FIG. 3, after image data is Huffman encoded, additional data is added to its lower bits. Additional data includes only valid bits. For example, the number of bits in binary representation is different for 1'° in decimal representation and '15' (1 bit, 4 bits). Additional data composed only of effective bits is similar to Huffman code. This is a variable-length code. Since the lower bits of the additional data are valid bits, the additional data is added to the Huffman code in LSB (least significant bit) first order.

When recording such variable length encoded data,
It is necessary to convert variable-length encoded data into fixed-length data based on the input format of the recording element before recording. For example, when an IC card is used as a recording element, input/output is performed in units of 1 byte, and encoded data must be converted to a fixed length of 8 bits.

Figure 14 shows such variable length Huffman code data
FIG. 117772 shows a conventional variable length code fixed length conversion circuit that converts bits into fixed length data. In addition, the first
FIG. 4 also shows the signal states of each part, where M indicates the MSB (most significant bit) and L indicates the LSB. In addition, valid data is indicated by diagonal lines.

Input terminals 1 and 2 are input with independently generated Huffman code data and additional data, respectively. Huffman code data is given to the Huffman code register 3 for storage, and additional data is given to the additional data register 4 for storage. The Huffman code register 3 has a bit width capable of storing a Huffman code of the maximum bit length, and the additional data register 4 has a bit width capable of storing additional data of the maximum bit length.

Therefore, invalid data 6 is stored in each register 3, 4 in addition to valid data 5 shown by diagonal lines in FIG.

The outputs of each register 3 and 4 are combined as shown in signal 7 and applied to serial conversion shifter 8.

After serially converting the valid data of the additional data, the serial conversion shifter 8 shifts the valid data so that it is continuous with the valid data of the Huffman code. This shift requires information on the number of effective bits of the additional data, and the serial conversion shifter 8 subtracts the number of effective bits from the maximum number of bits of the additional data to obtain the shift amount. The serial conversion shifter 8 converts the additional data into 7-serial data and then shifts it bit by bit according to the clock, and the conversion process requires time equal to the number of bits to be shifted.

From the serial conversion shifter 8, as shown in the shaded area of the signal 9, the output data string has data with added data and effective bits of the Huffman code formed in the center, and invalid bits formed on the LSB and MSB sides. is output. This data is sent to the fixed length conversion circuit 1 via the remainder bit addition circuit 10.
Give to 1. The fixed length conversion circuit 11 converts the sequentially input serial data into 8-bit parallel fixed length data and outputs it from the output terminal 12. If the data obtained by parallel conversion is less than 8 bits, the fixed length conversion circuit 11 outputs each bit of this data (hereinafter referred to as a remainder bit) to the remainder bit adding circuit 10.

For example, if the total number of bits of the Huffman code and additional data manually entered into the fixed length conversion circuit 11 is 26 bits I, then the fixed length conversion circuit 11 outputs three sets of 8 bits 1. Fixed length data is output to the output terminal 12,
The remaining bit of 2 bits is the remaining bit i.1 addition circuit 1 ()
The remainder bit addition circuit 10 adds the remainder bits 1 to 14 of the previous data to the beginning of the effective bits of the next data, as shown by the double hatched part of the signal 13, and converts the remaining bits into a fixed length conversion circuit. It is given to 11. In this way, the fixed length conversion circuit 11 sequentially outputs 8-bit parallel data regardless of the number of bits of the Huffman code and additional data. The beginning of the predetermined fixed length data output from the output terminal 12 is determined by calculating the length from the effective bits to the number, the remainder bits to the number, and the maximum bit of the Huffman code.

By the way, in order to simplify the processing, the serial conversion shifter 8 converts the input data into serial data when shifting the valid bits of the additional data.

Therefore, fixed length conversion processing takes a long time. Therefore, when used for compressing image data in an electronic still camera, for example, it takes a long time to write to the memory card, so there is a problem that continuous shooting cannot be performed at a comparatively fast speed. there were.

(Problems to be Solved by the Invention) -1,1-- As described above, in the conventional fixed-length conversion circuit for variable-length codes mentioned above, there is a problem that the conversion process takes a long time. :.

The present invention has been made in view of such problems, and includes:
An object of the present invention is to provide a fixed-length conversion circuit for variable-length codes that can perform high-speed processing.

[Structure of the Invention] (Means for Solving the Problems) A fixed-length conversion circuit for variable-length codes according to the claims of the present invention converts composite data of a pair of parallel variable-length codes sequentially input into predetermined bits to a number of bits. In a variable length code fixed length conversion circuit that converts the variable length code into a parallel fixed length code and outputs it, the pair of °
A shifting means [shifting one of the variable length codes and combining it with the other variable length code to obtain a combination in which both effective bits are continuous];
71~ Shifting the synthesis bits from the means based on the number of invalid fillers of the other variable length code, the effective bits of the 1 '2 - synthesized data are arranged on the upper bit side. 2, the input data is divided into upper predetermined bits and other lower order bits and outputted in parallel, and the number of bits of the other lower order bits is greater than the bit number of the upper predetermined bits. an output means for outputting information from the bits to the number by using the other lower bits as surplus bits when the number of bits decreases; The number of bits of the composite data is this remainder bit (′)
a third shifting means for shifting to the lower bit side; and a third shifting means for selectively supplying the other lower bits to the output means until the surplus bit is generated; The variable length code fixed length conversion circuit according to claim 2 of the present invention is provided with a selection means added to the upper bit side of the output of the shift means and applied to the output f-stage. , instead of the first shifting means, the effective bits of the pair of variable length codes are arranged on the upper bit side (, and the effective bits of one variable length code and the effective bits are arranged on the lower bit side). and the other variable length code to obtain composite data in which both effective bits are continuous, and provide the obtained composite data to the second shifting means. The fixed-length conversion circuit for variable-length codes according to claim 3 is the fixed-length conversion circuit for variable-length codes according to claim 2, in which, in place of the first combining means and the second shifting means, the pair of variable length The variable-length code whose valid bits are arranged on the ``-'' bit side is shifted based on the number of invalid bits of the other variable-length code whose valid bits are arranged on the ``-'' bit side. the variable length code according to claim 4 of the present invention, further comprising a second combining means for combining the variable length code with the other variable length code and applying it to the third shifting means after performing In the fixed length conversion circuit for a variable long shot-bow according to claim 2, the fixed length conversion circuit replaces the second and third shifting means with the other 14 variable length code of the pair of variable long shot. The shift based on the number of invalid bits and the number of remaining bits (1:
or the first synthesis means.

A fourth shifter shifts the composite data of 1.1 and supplies it to the selection means.
It is equipped with a shifting means.

(Operation) In claim 1 of the present invention, one of the pair of parallel variable length codes is shifted and combined with the other by the first shift stage, and a combined take or a combination in which the effective bits of both are continuous is generated. and is applied to the second shifting means. The second shifting means shifts the valid bits to the third-order bit side, and the third shifting means shifts the effective bits to the lower bit side by the number of bits of the remaining bits. The output of the third shift means is applied to the output means via the three-option means, and the output means outputs the upper predetermined bits as a fixed length code. The remaining lower bits are fed back to the output means via the selection means, and are sequentially converted into a fixed length code of predetermined bits and output. The head of the effective bit l ~ output from the third shift means is shifted to the lower bit side by the remaining bit I, and the remaining bit from the output means is added to the upper bit of the next data by the selection means and j1 bla) Ijλ falls into three means. The first to third shifters 1 and 5 and the selection means shift the effective bits of the composite data to the beginning of the data without serial conversion, and the time required for fixed length conversion is short.

n of the present invention! In the 'I requirement 2, the first combining means generates continuous combined data of both effective bits and supplies it to the second shifting means. This eliminates the need for the first shift means and reduces the circuit scale.

In claim 3 of the present invention, the second combining means shifts the variable length code No. 11 on the one side and combines it with the other variable length code, so that the effective bits of both sides are continuous and the effective bit of the second one is shifted. The synthesized take arranged on the high-order bit side is omitted and given to the third shift means. As a result, the circuit scale is reduced by omitting the means for the first synthesis stage and the second shift stage.

In claim 4 of the present invention, the fourth shift means adjusts the number of invalid bits and the number of remaining bits of the other variable length code;
-J shifts the synthesis data from the first synthesis means-
By doing so, an output similar to the output of the third shift means is obtained. This reduces the circuit scale by omitting the second and third shifting means.

(Example) Hereinafter, an example of the present invention will be described in detail based on the drawings. FIG. 1 is a block diagram showing a fixed length conversion circuit for variable length codes according to a first embodiment of the present invention. This example describes an example in which image data consisting of a Huffman code with a maximum bit length of 6 bits and addition data with a maximum bit length of 11 bits is converted into parallel fixed-length data with a maximum bit length of 8 bits. It shows.

The ROM 22 stores Huffman codes and the bit lengths of the Huffman codes, and an address is designated by image data input through the input terminal 21, and the image data is converted into a Huffman code and output.

Further, variable length additional data is stored in R, 0M24, and the data input through the input terminal 23 is converted into variable length additional data and output. The output of R,0M22 is connected to a flip-flop (hereinafter referred to as FF)25.
-Well, FF25 is the clock CK input to the clock end.
Shift the output of ROM 22 at timing 1] 7
−1 to output to circuit 27; On the other hand, the output of the ROM 24 is given to the FF 26, and the FF 2G outputs the output of the R, OM 24 to the shift circuit 28 at the timing of the clock CK1 input at the clock end.

The shift circuit 28 includes 1-bit shifters Sa1 to 10-bit shifters 5alO and these shifters Sa1 to Sal.
It is constituted by a selector S Ea which outputs the output of o in one choice. Shift concave i? The fi28 outputs the data from the FF2G as is, or shifts 1 to 10 bits to the MSB side based on the control signal and outputs the data. In addition, the Schiff l-circuit 27 has one hit l.
- shifters Sb1 to 13 - shifter Sb13 and a selector SEL that selectively outputs the outputs of these shifters Sbi to SIN3. The shift circuit 27 outputs the input take as it is, or outputs it based on the control signal.
The output is shifted to the side.

Figure 2 is the 1-th 21772 diagram explaining the jitter and 41 totak that constitute each shift to circuit in Figure 1.
A 5-bit shift circuit is shown. Each shift circuit in FIG. 1 has the same structure as the shift circuit in FIG. 2.

The input terminals 40 to 44 have data MSB to 1, respectively.
,, given SB. Selector 4 for Ohi”
5 has input terminals 40 to 44, MSB to LS
Enter all data of B. The selector 46 for the first bit selects the lower fourth bits 1 to LS B from the terminals 41 to 44.
Input the lower 4 bits of . 1st bit selector 46
converts the input data of 4 bits 1 to 4 bits into data of the upper 4 bits, adds LSB of 0"', and outputs it. The selector 47 of the 2nd bit is connected to the input terminals 42 to 4. Input the lower 3 bits of the input data from 44,
Convert this data to the upper 3 bits and
SB and the second lower bit are added and output. Similarly, the third bit selector 48 inputs the lower two bits I of the input data, converts this data to the upper two bits, adds "0" (-1) to the lower three bits 1 and outputs it. In addition, the selector 49 of the 4th bit I takes in the LSB of the input data, converts this cheater], 9 --- to MSB, adds O°' to the lower 4 bits, and outputs it. It has become.

A control signal is applied to each selector 45 to 49, and the output of the selector based on this control signal is selectively output. For example, when the 2-bit L1 selector 47 is selected by the control signal, the lower 3 bits of the input data are converted to the upper 3 bits by the 2nd bit selector 47, and the lower 2 bits are 0'' or ( =J is added and output.The data input from the inputs 42 to 44 are shifted according to the 2 hit 1-M S B 1 rule and output.

Control A: By selecting each selector according to τ, input data can be shifted from 0 to 4 bits to the MSB side.

Selector St? of shift circuit 28 in FIG. a has ROM
From 24, manually input the data indicating the number of I=J addition data to J'3 (Indication omitted), selector S E a
Based on this data, 1 hit 1-shifter Sai to 1
Selectively outputs one of the outputs 0, 1 to 1 to 1, S alo. 1, ), the valid bits of the added data are shifted to the MSB side, and the output of the selector SEa is combined with the output of the FF 25 and given to the shift circuit 27. The shift circuit 27 is F
The F25 output is taken in as upper 6-bit data, and the selector SEa output is taken in as lower 11 bits, and the valid bits of the FF25 output and the valid bits of the selector SEa output are in a continuous state.

Shift to circuit 27 1-bit shifter S old to] 3 bit y
The l shifters 51113 each shift the input 27-bit data by 1 to 13 bits toward the MSB side and output the shifted data to the selector SEb. Selector SEb has ROM
22 to the effective bits of the Huffman code, and the selector SEb selectively outputs the outputs of shifters Sb1 to Sb13 based on this data, thereby converting the effective bits of the Huffman code and additional data to the MSB. It is supposed to shift to the side. Shift circuit 2
FI the output of 7? 29 to the shift circuit 30. FF29 is the clock input to the clock end.
= 21 - so that the outputs of the shift I to concave 1 heat 27 are output to the shift circuit 28 at a timing of 1.

The shift circuit 30 is composed of 1-bit shifters SC1 to 7-bit shifters SC7 and a selector SEC that selectively outputs the outputs of these shifters Sc1 to SC7. 1-bit shifter SC1 to 7-bit shifter Sc7 convert input data into 1-bit to 7-bit 1. Schiff L-L on the SB side. and outputs it to selector SEc. The selector 3EC is given information on the remaining bits, and based on this information, the shifter S (:1 to SC7
Shift b based on the remainder bits by selecting
3) It is designed to shift the FF29 output to the LSB side. The 34-bit output from the shift circuit 30 is given to the selector 31 as data 1. selector 3
1 is given to FF32, and Fl"-"32 receives a clock CK with a shorter period than the clock CKI at the clock end.
0 is input, and at the timing of this clock CKO, the upper 8 bits of the output of the selector 31 are outputted to the output terminal 33, and the lower 26 bits are set as 2 and output to the selector 3.
1 (, I will return this JQ.

The third item 1 is the specific configuration of the selector 31 in FIG.
2:) is a block diagram showing the system.

The selector 31 is composed of selection circuits SEI to 5E34. The MSB to LSB of the data 1 from the shift circuit 30 are applied to the input terminals 0 of each selection amount i\8s Ei to S1Σ34 of the selector 31, and the input terminals 1 of the selection circuits S11 to 5E26 are Each Fl-″32
Data ■2 MSB to LSB are given.

The selection circuits SEl to SE7 are controlled by a control signal ssO based on the remainder bit, and the selection circuits S1': 8 to 5
E34 is controlled by a control signal ssl based on the remainder bit. The selection circuits SEl to 5E34 receive the control signal s
so, ssl, when the control signal input terminal S becomes high level (hereinafter referred to as "H"), select the input terminal],
When it goes to low level (hereinafter referred to as I7''), the input terminal becomes 0.
You can now choose.

Next, the operation of the fixed J (conversion circuit) of the variable length code configured in this way will be explained with reference to the explanatory diagram of FIG. It shows the state of data appearing at points a to 11 in the middle.
In the figure, valid bits are indicated by broken lines.

The ROM 22 converts image data input through the input terminal 21 into Huffman codes and outputs the Huffman codes to the FF 25 . Also, the ROM 24 stores the I-1 addition data Fl? to be added to the Huffman code from the ROM 22. Output to 26. I・'F2
．． The clock CK1 is applied to the clock ends of '+ and 26, and the clock ends of [F25 and 26 are the timing of the clock CK i', and the Huffman codes shown in FIGS. 4(a) and (b), respectively. Outputs Ichiyo and I/1 addition data. Note that the effective bits of the Huffman code data from the ROM 22 are set to the lower 0 bits, and the effective bits of the additional data from the ROM 24 are set to the lower 4 bits.

FF2G to σ)(-1 added data is given to the shift circuit 28.
1 is loaded with data indicating the number ("7") from the ROM 24, and the selector SF, a selectively outputs the output of the 7-bit shifter sa7. . Thus, as shown in Part 4 (c).
The valid bits are the MSB and the output of the selector SEa is combined with the output of the 7-bit shift FF25 and the output of the selector SEa, and as shown in FIG. 4(d), the Huffman code data is generated. and the valid bits of the additional data are supplied to the shift circuit 27 in a continuous state. The selector SEb of the shift circuit 27 has R. Data indicating the number of invalid bits ("6") of Huffman code data is given from 0M22, and selector SEb is 6 bits) and shifter S.
Select the output of b6. In this way, the data is shifted to the 6-bit MSB side in the shift circuit 27, and the first bit of the valid bits of the Huffman code data becomes the MSB and is applied to the FF 29 (FIG. 4(e)).

17F29 outputs 27 bits of data input at the timing of clock CK1 to shift circuit 30.

Thus, R. 0M22. The output of 24 is transferred to shift circuit 30. The selector SF]C of the shift circuit 30 is given the data of the number of remaining bits, and the selector SEc is supplied with the data of the number of remaining bits.
Select CI to SC7. Now, as shown in the satin pattern in Fig. 4 (f>), it is assumed that the remainder of the previous data is 1 2 5 - 1 to 6 or 1 to 6. In this case, the selector SIC is set to the 0 bit shifter ScG. The shift circuit 30 selects the output of the 6-bit L
．． S: Shift to the 13 side and output to the selector 31.

The selector 31 selects the control input terminals of the selection circuits S f=: i to S E G by the control signals SSO and SSI.
l-pi, and the selection circuit SP. Is it the control input terminal of 7 or SE34? ■, °':・te, remainder of acid data Bi・)
1 to 1, and the output of the shift circuit 30 is set to the upper 7 bits to 1. To'F32 as S l-1
The output is fixed (Fig. 4(f)).

FI? Clock C manually operated at the 17th end of the 32 beam
The 8 bits of the tenth place (Fig. 41 (h)) of the data inputted to 34 hit 1 at the timing of KO are output to the output terminal 33, and the lower 26 bits (Fig. 4 (g)) are sent to the selector 31.
is returned as data 12. The selector 31 selects the selection amount b'! by the control signals sso, ss+. f. S
The control input terminals of F 1 to S E 34 become redundant,
Data ■ The other valid bit of t11212 bits
-Yu and Toi 22 hit 1, h) "effect) - Ichiyuki FF32
Output to. The FF 32 feeds back the valid data of the 1st and 8th bits 1 to 1 and the lower 26 bits to the selector 31 at the timing of the clock CKO. As a result, the remaining 4 bits are fed back to the selector 31.

At the next timing, the shift circuit 30 supplies the selector 31 with data 11 indicating the valid bits starting from the fifth most significant bit. Selector 31 is shift circuit 3
The remainder bit is added to the upper bit of the 0 output and output. In this way, at the timing of the next clock CKO
8-bit parallel fixed-length data is output from F32 to output terminal 33.

As described above, in this embodiment, the output of R,0M22.24 is shifted by a predetermined amount of -1t at the timing of the clock CK1 and is transferred, and is output as 8-bit fixed length data at the timing of the clock CKO. The time required to convert long code data to fixed length data can be significantly reduced.

FIG. 5 is a block diagram showing a variable length code fixed length conversion circuit according to a second embodiment of the present invention. Components in FIG. 5 that are the same as those shown in FIG.

This embodiment differs from the first embodiment in that the shift ~ circuit 2
8 is omitted and 170M51 is used instead of ROM24. R, OM 51 stores additional data, and outputs (=J addition data) to the shift circuit 27 via FF2G based on the data input via the input terminal 23.Additional data from the ROM!il The upper bit side is the valid bit, and the lower bit side is the invalid bit.

See FIG. 6 for the operation of the embodiment configured with TFI in this way! ! 9 Explain. FIG. 6(a),(b>.

(cl) to (11) respectively show the states of data present at points a, b, d to l1 in FIG. In FIG. 6, valid bits are indicated by diagonal lines.

In FIG. 6, the number of effective bits of Huffman code data is 10 bits 1 to 1, and the number of effective bits of additional data is 4 bits 1.

In this embodiment, the output of R,0M51 is output from the FF26 at the timing of the clock OK1.

The effective bits of the additional data from the ROM 51 are arranged on the upper bit side, and from the FF2B, as shown in Fig. 6 (1)
), additional data is output in which the upper 4 bits are valid bits and the lower 7 bits are invalid bits. This data is the same as the output of the shift circuit 28 in FIG. 1 (see FIG. 4(c)), and the subsequent operation is the same as in the embodiment shown in FIG.

This embodiment has the advantage that the shift circuit 28 can be eliminated and the circuit configuration can be simplified.

FIG. 7 is a block diagram showing a variable length code fixed length conversion circuit according to a third embodiment of the present invention. In FIG. 7-1, the same components as in FIG. 5 are designated by the same reference numerals and their explanations are omitted.

The ROM 52 stores Huffman code data, has an address designated by image data input through the input terminal 21, and outputs Huffman code data based on this image data. The Huffman code data from R, 0M52 has the upper bits ~ side as valid bits, and the
side is an invalid bit. FF output of ROM52
25 to the synthesis circuit 54 as data 3.

On the other hand, additional data with a maximum length of 11 bits from the ROM 51]? It is applied to the shift circuit ;)3 via F26.

The shift circuit 53 has the same configuration as the shift circuit shown in FIG.
The output of the code 26 is shifted to the MSB side by the number of invalid bits of the Huffman code data and output to the synthesis circuit 54. As a result, additional data of 27 bits is supplied from the shiso1 circuit 53 to the synthesis circuit il'854 as data 14.

FIG. 8 is a block diagram showing a specific configuration of the synthesis circuit 54 in FIG. 7.

The synthesis circuit 54 is composed of selection circuits Se1 to Se16. The MSB of the Huffman code data from the FF25 is input to the input terminal 0 of the selection circuit Selno1jse1G.
to L S 13 (Top 16 hits 1 to 1) are given.

Further, MSP3 to upper 16th bit) and (lower 12th bit) of the additional data from the shift circuit 53 are applied to the input terminals 1 of the selection circuits Sel to 5e16, respectively.

A control signal ss based on the effective number of bits of the Huffman code data is applied to the control input terminals S of the selection circuits SOL to 5e16, and the selection circuits Sel to SelG have the input terminals Select 1 and press “r
When it reaches 7''', input terminal 0 is selected.

Thereby, the combining circuit 54 combines the valid bits of the Huffman code data from the FF 25 and the additional data from the shift circuit 53. In this way, the synthesis circuit 54 outputs data to the FF 29, in which the outputs of the selection circuits Se1 to qSelG are the upper 16 bits, and the lower 11 bits 1 of the output of the shift circuit 53 are the lower bits.

Next, the operation of the third embodiment configured as described above will be explained with reference to FIG. 9. Figures 9(a, ) to (
c), (e) to (h) are a, b, c, and e in Figure 7, respectively.
It shows the state of data appearing at points. The shaded areas in FIG. 9 indicate valid bits. In addition, FIG. 9 shows an example in which the effective bits of the Huffman code are 10 bits, and the effective bits of the addition data are 4 bits.

The Huffman code data and the I' addition data from R and OM 52 and 51 are outputted via FFs 25 and 26, respectively.

These data are shown in Figures 9(a) and (b),
Valid bits are arranged on the MSB side.

In order to obtain the take shown in FIG. 9(e) from these data, first, the I' addition data is supplied to the shift circuit 53 and shifted. Of course, the shift circuit 53 receives the invalid bit number data ('6''') of the Huffman note month data, shifts the additional data to the MSB side by () bits, and fills the lower bits with invalid data. A and 1 are added to the 27-bit take 4, which is output to the synthesis circuit 54.

A control signal ss based on the effective number of Huffman code data is supplied to the synthesis circuit 54. As a result, the control input terminals S of the selection circuits Se1 to S elo of the synthesis circuit 54 become "l-"', and the jπ selection circuits Sel to 5010 select the input terminal O, and the selection circuits S ell to S elG
The control input terminal S becomes "'IT'" and the selection circuit S
ell to SelG select input terminal 1. That is, the effective bits of the Huffman code data from the FF 25 are output from the ) A 1-added theta is output. In this way, Figure 9 (e
) is given to the ITF 29 from the synthesis circuit 54.

The subsequent operation is similar to that of the second embodiment.

In this embodiment, the same effect as in the second embodiment can be obtained, and it is only necessary to shift the additional data.
There is an advantage that the 14-layer structure can be downsized.

FIG. 10 is a block diagram showing a variable length code fixed length conversion circuit according to a fourth embodiment of the present invention.

In FIG. 10, the same components as in FIG. 5 are given the same reference numerals, and their explanations will be omitted.

This embodiment differs from the second embodiment in that a shift circuit 60 is used in place of the shift circuit 27 of the second embodiment, and the shift circuit 30 is omitted. In the second embodiment, after the shift circuit 27 shifts the effective bits of the Huffman code data and i=J addition data to the MSB side, the shift circuit 30 shifts the remaining bits to the LS13 side.
In this embodiment, the shift circuit 60 shifts the remaining bits by 17 Jt and shifts them to the MSB side. The shift circuit 60 has the same configuration as other shift circuits, and receives data in which Huffman "1-" data and valid "1-" data are successive from the FFs 25 and 26. 1 is given, and the shift circuit GO subtracts the number of remaining bits from the number of invalid bits of the Huffman code data to obtain the shift l- amount, and converts the input data to the MSB side (if the shift amount is negative). In addition, the shift circuit 60 adds an invalid bit to the LSB side of the shifted data and outputs 3/l bit data to the F29. There is.

The operation of the fourth embodiment, which is completed in 1:U Kl li4, will be explained with reference to the 11th and 1 explanatory diagrams.

Figure 11<21), (t)), (d) to (11) are H, b, cl to ' in 1st and OU21, respectively.
4J, shows the evening state that appears at point h. In the 11th rs; the shaded area indicates the high effect.

As shown in FIG. 11(a), the effective bit of FF25 is L.
Output the Huffman code data arranged on the S B side,
The FF 26 outputs additional data in which the effective bits are arranged on the MSEI side as shown in FIG. 11(b). These data are combined and input to the shift circuit 60 (FIG. 11(d)). The shift circuit 60 subtracts the number of remaining bits from the number of invalid bits of the Huffman code data to obtain a shift amount, and shifts the input data by this shift amount (FIG. 11(e)). is output to the selector 31 at the timing of clock CK1. The subsequent operation is similar to that of the second embodiment.

This embodiment has the same effect as the second embodiment, and has the advantage that the circuit configuration can be further simplified by omitting the shift circuit.

[Effects of the Invention] As explained above, the present invention has the effect of enabling high-speed processing and reducing the circuit scale.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a variable length code fixed length conversion circuit according to the first embodiment of the present invention, FIG. 2 is a block diagram for explaining a shift circuit, and FIG. 3 is a concrete diagram of the selector 31. FIG. 4 is an explanatory diagram for explaining the operation of the first embodiment, and FIG. 5 shows a fixed-length conversion circuit for variable-length codes according to the second embodiment of the present invention. A block diagram, FIG. 6 is an explanatory diagram for explaining the operation of the second embodiment, and FIG. 7 is a block diagram showing a fixed length conversion circuit for a variable length code according to a third embodiment of the present invention. 8 is a block diagram showing a specific configuration of the synthesis circuit 54 in FIG. 7, FIG. 9 is an explanatory diagram for explaining the operation of the third embodiment, and FIG.
The figure does not show a fixed length conversion circuit for variable length codes according to the fourth embodiment of the present invention, but FIG. 11 is an explanatory diagram for explaining the operation of the fourth embodiment, and FIG. FIG. 13 is an explanatory diagram for explaining the code, FIG. 13 is an explanatory diagram without image data, and FIG. 14 is a block diagram showing a conventional fixed-length conversion circuit for variable-length codes. 22, 24...ROM, 25.26, 29.32...FF, 27, 28.30 Shift~circuit, 31...Selector. −～η dimension Inψ

Claims (4)

[Claims] (1) In a variable-length code fixed-length conversion circuit that converts the combined data of a pair of parallel variable-length codes that are sequentially input into a parallel fixed-length code with a predetermined number of bits and outputs the same, all effective bits are on the lower bit side. a first shifting means for obtaining composite data in which both effective bits are continuous by shifting one of the pair of arranged variable length codes and combining it with the other variable length code; and from the first shifting means. a second shifting means for arranging the valid bits of the composite data on the upper bit side by shifting the composite data based on the number of invalid bits of the other variable length code; and other lower bits and output them in parallel, and if the number of bits of the other lower bits is less than the number of upper predetermined bits, the other lower bits are output in parallel. output means for outputting information on the number of bits as bits; and a second shift means for shifting the composite data from the second shifting means to the lower bit side by the number of bits of the remainder bits based on the information on the number of bits of the remainder bits. 3 shift means; and until the surplus bit is generated, the other lower bits are selectively supplied to the output means, and when the surplus bit is generated, the surplus bit is transferred to the upper bit side of the output of the third shift means. A fixed length conversion circuit for a variable length code, further comprising a selection means for supplying the output means to the output means. (2) Instead of the first shifting means, one of the pair of variable length codes has effective bits arranged on the upper bit side, and the other variable length code has effective bits arranged on the lower bit side. 2. The variable length code according to claim 1, further comprising a first combining means which obtains combined data in which both effective bits are continuous by combining the variable length code with the variable length code and supplies the obtained data to the second shifting means. Fixed length code conversion circuit. (3) Instead of the first synthesizing means and the second shifting means, use one of the pair of variable length codes in which the effective bits are arranged on the upper bit side. and a second combining means which synthesizes the variable-length code with the other variable-length code after shifting by a shift amount based on the number of invalid bits of the other variable-length code arranged in the second variable-length code and supplies the same to the third shifting means. 3. The variable length code fixed length conversion circuit according to claim 2. (4) Instead of the second and third shifting means, the first synthesis is performed by a shift amount based on the number of invalid bits and the number of surplus bits of the other variable length code of the pair of variable length codes. 3. The fixed length conversion circuit for variable length codes according to claim 2, further comprising fourth shifting means for shifting the composite data from said means and applying it to said selection means.