JPH0415763A - Still picture processor - Google Patents

Abstract

PURPOSE:To simplify the circuit constitution at a picture data fetching part by providing a picture data output means and a timing signal generation means which secures the synchronization of a frame buffer memory. CONSTITUTION:A frame buffer memory 21 is used in place of a DRAM to write the picture data equivalent to one frame at a high speed and in the order of input picture elements with no designation required for a memory address despite the small memory capacity. Thus the digital picture signals that undergone the A/D conversion through an A/D conversion part 2 can be stored directly in the memory 21 in sequence and in the fast timing with no intervention of a shift register circuit, etc., that are necessary to the DRAM and without designating any memory address. As a result, the circuit constitution is simplified and miniaturized at a picture data fetching part.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a still image processing device that performs image processing of still images.

[Conventional technology]

As a conventional image processing device of this type, for example,
There is one described in FIG. 1 of Publication No. 1-55785.

This has a configuration as shown in FIG.

That is, in FIG. 3, numeral 1 is a television camera that images a subject and outputs an analog video signal.

Reference numeral 2 denotes an analog/digital converter (hereinafter referred to as A/D) which converts the video signal output from the television camera 1 into analog/digital and outputs digital image data. Reference numeral 3 denotes an image memory (hereinafter referred to as FM) for storing image data output from this A/D 2, and has a capacity for one screen. Reference numeral 7 denotes a digital/analog conversion section (hereinafter referred to as D/A) which converts the image data read from the FM 3 into digital/analog and outputs an analog video signal for image display. 8 is a monitor television that displays images using the video signal output from this D/A 7. Reference numeral 9 denotes a write/read control unit that performs hardware control of writing/reading of the FM3. 10 is the above FM
This is a magnetic disk device for recording image data stored in 3. 11 is the above TV camera 1
．． A/D2. D/A? and an oscillator (hereinafter referred to as 08C) that generates and supplies an operating clock to the write/read control unit 9. 12 is a programmable computer equipped with various general-purpose arithmetic processing functions, information storage, and input/output functions, and is capable of inputting/outputting image data between the FM 3 and the magnetic disk device 10 and performing various processing of the image data. Do it programmatically. Reference numeral 13 denotes a computer interface of the FM3, which is located between the computer 12 and the FM3 and performs input/output operations for image data and the like. Reference numeral 14 denotes an operation unit for instructing the computer 12 about input/output and processing of image data.

FIG. 4 is a block diagram clearly showing the image data capturing section of this image processing apparatus. In this figure, 1
Reference numeral 5 denotes a speed converter, which converts the digital signal into an analog/digital signal by the A/D 2 into a very high-speed signal, and since it cannot be directly input into the FM3, it converts the high-speed serial signal into a very high-speed signal. It is provided to convert it into a parallel signal and convert it to a timing speed that can be taken into FM3. Additionally, in order to perform the above series of operations in real time, 03CII uses television cameras 1.
A/D2. Speed converter 15. Provided for synchronizing FM3.

With the above configuration, the analog image data from the television camera 1 is converted from analog to digital by the A/'D2, and the converted digital signal is once stored in the speed converter 15 for speed conversion, and then converted to the memory in the FM3. The line in which the address is specified is memorized (.

Note that a circuit using DRAM is well known as FM3. In that case, since the access speed of DRAM is slow, it is necessary to perform serial/parallel conversion. FIG. 5 is a block diagram of the main part of the circuit, and 16 is, for example, 8
a plurality of first shift register circuits of bits; 17 is a first shift register circuit;
A clock frequency divider 18 is a DRAM, 19 is a plurality of second shift register circuits of, for example, 8 bits, and 20 is a second clock frequency divider. Note that the data bus between the DRAM 18 and each shift register circuit 16, 19 is composed of eight lines.

The input image data is serially transferred to the first shift register circuit 16 pixel by pixel at clock timing. The input data for eight pixels is latched into the latch circuit of the first first shift register circuit 16 at the timing of the clock frequency divided by eight by the first clock frequency divider 17. This latched 8
The data for pixels is sequentially transferred to the first shift register 16 on the rear side, and all the first shift registers 16, 16 .・・・
..., the data for those 8 pixels is sequentially transferred to the first shift register 16 on the rear side.
Each pixel data is transferred in parallel to DRAM1.
8 is written. By repeating this operation, image data is written using serial/parallel conversion.

Also, in reading, contrary to writing, image data is transferred in parallel for 8 pixels from the DRAM 18 to all the second shift register circuits 19, 19 . ..., and then serially transferred one pixel at a time from the first second shift register circuit 19 and read out. that time,
The data for eight pixels in each second shift register 19 is sequentially transferred to the second shift register 19 on the front side.

[Problem to be solved by the invention]

However, in the conventional image processing apparatus described above, in order to store image data in the FM3 in real time, the television camera 1. A/D2. The timing of the synchronization clock of the speed converter 15° FM3 must be adjusted, and when storing data, memory addresses must be designated and stored sequentially, making the adjustment complicated. Furthermore, when DRAM2S is used for FM3, the timings of upper and lower address transfer signals are different, so an address switching circuit is required and timing alignment becomes very complicated. Further, in the case of a configuration using serial/parallel conversion as described above, peripheral circuits such as shift register circuits 16 and 19 are also required. Also, if SRAM is used for FM3, the timing adjustment is somewhat reduced compared to DRAM18, but since the capacity is smaller than DRAM8, more SRAM is required to store image data, which makes the device larger. It ends up.

In particular, systems that handle still images only need to be able to store a few frames worth of image data, so simply using an image processing device with real-time processing capability for video as described above would be wasteful and unsuitable. It is.

SUMMARY OF THE INVENTION In view of the above-mentioned problems, it is an object of the present invention to provide a still image processing device in which the circuit configuration of an image data capture section is simplified and the device is compact.

[Means and effects for solving the problems] A still image processing device according to the present invention includes means for outputting digital image data, a frame buffer memory for storing the output signal, and a link between the image data output means and the frame buffer memory. The image forming apparatus may include a timing signal generating means for synchronizing, a monitoring means for receiving an output signal from the frame buffer memory and displaying an image, and a processing means for processing image data in the frame buffer memory. It is a feature.

That is, as shown in FIG. 1, which is a block diagram of the image data importing section of the apparatus of the present invention, instead of using DRAM as a memory, image data for one frame is input to each input pixel without specifying a memory address, although it has a small capacity. Since the frame buffer memory 21, which can be sequentially written at high speed, is used, the digital image signal converted from analog to digital by the A/D 2 is further stored in the memory without passing through the shift register circuit required in the case of DRAM. It is possible to directly sequentially store data in the frame buffer 21 at a fast timing without specifying an address. Therefore, the circuit configuration of the image data importing section becomes simple and compact.

It goes without saying that this also applies to the case where the image data is transmitted and received between the frame buffer 21 and the computer 12 via the interface when the image data in the frame buffer 21 is processed by the computer 12. In other words, since image data can be exchanged through a parallel interface,
The circuit configuration of this part also becomes simpler and smaller.

〔Example〕

Hereinafter, the present invention will be described in detail based on the illustrated embodiment, with the same reference numerals assigned to the same members as in the above-mentioned conventional example.

FIG. 2 is a block diagram of a still image processing device for a microscope, which is an embodiment of the present invention. In the figure, 22 is a microscope for observing specimens. 23 is a switch circuit, A/
This is for selecting either the digital signal sent from D2 or the arithmetic processed digital signal and inputting it to the frame buffer memory 21 side. 24 and 25 are first and second latch circuits that temporarily hold each data; 26
is a 3-state buffer for input/output switching; and 27 is a switch circuit 23 based on the signal from the computer 12. Frame buffer 21. Latch circuit 24.25.3 This is a control logic circuit that sends control signals and tarok signals to the state buffer 26.

Since this embodiment is configured as described above, the microscope 22
The resulting image is captured by a television camera l, and the image data is input to the A/D 2 as an analog signal. The data is then converted into digital signal data by the A/D 2 and stored in the frame buffer 21 via the switch circuit 23 in accordance with a clock signal synchronized with the A/D 2. In this way, data for one still image frame is stored in the frame buffer 21.

When displaying this image directly, the control logic circuit 27 sends an OUT signal to the frame buffer 21.
A read permission signal is sent from (output) 2, and as a result, image data is sent from UT 2 to monitor television 8 and displayed.

In addition, when performing arithmetic processing such as binarization and edge emphasis on the stored image data, the control logic circuit 27 sends a read permission signal from 0UTI to the frame buffer 21, and as a result, the image data is read from 0UTI. The signal is output and latched by the first latch circuit 24. Next, in order to store the image data in the memory section in the computer 12, a signal is sent from the control logic circuit 27 so that the 3-state buffer 26 becomes an input on the computer side, and as a result, the image data is passed through the buffer 26 and transferred to the above-mentioned computer via the parallel interface. imported into the memory section. Next, all arithmetic processing is performed within the computer 12, and then a signal is sent from the control logic circuit 27 so that the buffer 26 becomes the computer data output side, and as a result, the processed image data is output from the computer 12. It is latched by the second latch circuit 25. The latched image data is sequentially stored in the frame buffer 21 by switching the switch circuit 23 to the arithmetic processed signal input side in response to a signal from the control logic circuit 27.

This means that the data for the processed frame has been newly stored.

Display is performed by outputting from 0UT2 and displaying on monitor television 8 in the same manner as above.

Thus, according to this embodiment, the frame buffer memory 21, which has a small capacity but can write image data for one frame at high speed in the order of input pixels without specifying a memory address, is used instead of DRAM as the memory. Therefore, the digital image signal converted from analog to digital by the A/D2 is quickly sent directly to the frame buffer 21 without passing through the shift register circuit required in the case of DRAM, and without further memory addressing. It can be stored sequentially at the right time. Therefore, the circuit configuration of the image data importing section becomes simple and compact.

Further, when image data in the frame buffer 21 is processed by the computer 12, the image data can be exchanged via the parallel interface, so the circuit configuration of this part becomes simpler and smaller.

〔Effect of the invention〕

As described above, the still image processing device according to the present invention has the practically important advantage that the circuit configuration of the image data capture section is simple and compact.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an image data capturing section of a still image processing device according to the present invention, FIG. 2 is a block diagram of an embodiment of the still image processing device according to the present invention, and FIG. 3 is a block diagram of a conventional example. Figure 4 is a block diagram of the image data capture unit of the above conventional example, and Figure 5 is a block diagram of the image data capture unit of the above conventional example.
FIG. 3 is a block diagram of main parts of an image data importing section when using the image data capturing section. ■...Television camera, 2...Analog/digital conversion section, 7...Digital/analog conversion section, 8.
...Monitor TV, 11...Oscillator, 12.
... Computer, 21 ... Frame buffer memory 22 ... Microscope, 23 ... Switch circuit, 24 ... First latch circuit, 25 ... Second latch circuit, 26 ... ...3 state battle < 27...
...Control logic circuit.

Claims (1)

[Claims] means for outputting digital image data; a frame buffer memory for storing the output signal; a timing signal generating means for synchronizing the image data output means and the frame buffer memory; and receiving the output signal of the frame buffer memory. A still image processing device comprising: a monitor means for displaying an image; and a processing means for processing image data in the frame buffer memory.