JPH0415702U - - Google Patents
Info
- Publication number
- JPH0415702U JPH0415702U JP5410990U JP5410990U JPH0415702U JP H0415702 U JPH0415702 U JP H0415702U JP 5410990 U JP5410990 U JP 5410990U JP 5410990 U JP5410990 U JP 5410990U JP H0415702 U JPH0415702 U JP H0415702U
- Authority
- JP
- Japan
- Prior art keywords
- abnormal state
- signal
- state signal
- time
- detection means
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000002159 abnormal effect Effects 0.000 claims description 11
- 238000001514 detection method Methods 0.000 claims description 11
- 230000005856 abnormality Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Safety Devices In Control Systems (AREA)
Description
第１図は本考案による負荷駆動装置の制御装置
の基本構成を示すブロツク図、第２図は本考案及
び従来の負荷駆動装置の制御装置のハード構成の
実施例を示すブロツク図、第３図は本考案による
制御装置の第２図中のＣＰＵが行う仕事の内容を
示すフローチヤート、第４図及び第５図は本考案
による制御装置の第２図中の各部の状態を示すタ
イミングチヤート、第６図は従来の装置の第２図
中の各部の状態を示すタイミングチヤート、第７
図はスマートパワーＩＣの構成例を示すブロツク
図である。
１……負荷駆動装置（スマートパワーＩＣ）、
１２……駆動手段（パワーＭＯＳＦＥＴ）、１４
……異常検出手段、１４ａ……電圧検出回路、１
４ｂ……電流検出回路、１４ｃ……過熱検出回路
、２１ａ……制御信号出力手段（ＣＰＵ）、２１
ｂ……異常状態信号出力手段（ＣＰＵ）、２１ｃ
……初回検出手段（ＣＰＵ）、２１ｄ……制御手
段（ＣＰＵ）、ＳＷ１……スイツチ、ＲＬ……負
荷。
FIG. 1 is a block diagram showing the basic configuration of a control device for a load driving device according to the present invention, FIG. 2 is a block diagram showing an embodiment of the hardware configuration of a control device for a load driving device according to the present invention and a conventional one. is a flow chart showing the content of the work performed by the CPU in FIG. 2 of the control device according to the present invention; FIGS. 4 and 5 are timing charts showing the states of each part in FIG. 2 of the control device according to the present invention; Figure 6 is a timing chart showing the state of each part in Figure 2 of the conventional device;
The figure is a block diagram showing an example of the configuration of a smart power IC. 1...Load drive device (smart power IC),
12... Drive means (power MOSFET), 14
... Abnormality detection means, 14a ... Voltage detection circuit, 1
4b...Current detection circuit, 14c...Overheat detection circuit, 21a...Control signal output means (CPU), 21
b... Abnormal state signal output means (CPU), 21c
... Initial detection means (CPU), 21d ... Control means (CPU), SW 1 ... Switch, RL ... Load.
Claims (1)
る異常検出手段とを備え、外部制御信号の入力時
に前記異常検出手段により異常状態が検出される
と負荷の駆動を停止すると共に、異常状態信号を
外部に出力し、前記外部制御信号が入力されなく
なつたときに前記異常状態信号の発生を停止する
ように構成された負荷駆動装置の制御装置におい
て、 前記外部制御信号を出力する制御信号出力手段
と、 前記異常状態信号を検出する異常状態信号検出
手段と、 該異常状態信号検出手段にて検出された異常状
態信号が最初のものであることを検出する初回検
出手段と、 該初回検出手段によつて異常状態信号が初回で
あることが検出されたとき、前記制御信号出力手
段に対して、前記異常状態信号の入力時から所定
時間外部制御信号の出力を停止させ、その後再度
出力させる制御を行う制御手段とを備える、 ことを特徴とする負荷駆動装置の制御装置。[Claims for Utility Model Registration] The invention comprises a drive means for driving a load and an abnormality detection means for detecting an abnormal state, and when an abnormal state is detected by the abnormality detection means at the time of inputting an external control signal, the drive of the load is started. A control device for a load driving device configured to output an abnormal state signal to the outside at the same time as stopping the external control, and to stop generating the abnormal state signal when the external control signal is no longer input. control signal output means for outputting a signal; abnormal state signal detection means for detecting the abnormal state signal; and initial detection for detecting that the abnormal state signal detected by the abnormal state signal detection means is the first one. means, when the first time detection means detects that the abnormal state signal is the first time, the control signal output means stops outputting the external control signal for a predetermined period of time from the time when the abnormal state signal is input. 1. A control device for a load driving device, comprising: a control device that performs control to output the output again after that.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5410990U JPH0415702U (en) | 1990-05-25 | 1990-05-25 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5410990U JPH0415702U (en) | 1990-05-25 | 1990-05-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0415702U true JPH0415702U (en) | 1992-02-07 |
Family
ID=31575881
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5410990U Pending JPH0415702U (en) | 1990-05-25 | 1990-05-25 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0415702U (en) |
-
1990
- 1990-05-25 JP JP5410990U patent/JPH0415702U/ja active Pending
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