JPH0167574U - - Google Patents
Info
- Publication number
- JPH0167574U JPH0167574U JP1987163916U JP16391687U JPH0167574U JP H0167574 U JPH0167574 U JP H0167574U JP 1987163916 U JP1987163916 U JP 1987163916U JP 16391687 U JP16391687 U JP 16391687U JP H0167574 U JPH0167574 U JP H0167574U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- phase
- gate
- voltage
- significant
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000001514 detection method Methods 0.000 claims description 4
- 230000016507 interphase Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
- 230000002159 abnormal effect Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
Landscapes
- Electronic Switches (AREA)
- Testing Electric Properties And Detecting Electric Faults (AREA)
- Keying Circuit Devices (AREA)
Description
第１図はこの考案の一実施例を、コンタクタの
制御信号入力回路および異常信号出力回路と併せ
て示した回路図、第２図は同実施例を適用する他
の主回路系統図、第３図ａ，ｂは同実施例をこの
系統に適用した場合の設置状態を示すブロツク図
、第４図ａ〜ｉは同実施例の動作を説明するため
の波形図である。
２Ｒ，２Ｓ，２Ｔ：主回路素子、３：トリガ回
路、１０，２０：故障検出回路、ＯＩＲ，ＯＩＳ
，ＯＩＴ，ＯＩＯ：フオトカプラ、Ａ１，Ａ２，
Ａ３：ナンドゲート、Ｂ１，Ｂ２，Ｂ３：エクス
クルーシブオアゲート。なお、各図中、同一符号
は同一又は相当部分を示す。
Fig. 1 is a circuit diagram showing an embodiment of this invention together with a contactor control signal input circuit and an abnormal signal output circuit, Fig. 2 is another main circuit system diagram to which the same embodiment is applied, and Fig. 3 Figures a and b are block diagrams showing the installation state when the same embodiment is applied to this system, and Figures 4a to 4i are waveform diagrams for explaining the operation of the same embodiment. 2R, 2S, 2T: Main circuit element, 3: Trigger circuit, 10, 20: Failure detection circuit, OIR, OIS
, OIT, OIO: Photocoupler, A 1 , A 2 ,
A3 : NAND gate, B1 , B2 , B3 : Exclusive or gate. In each figure, the same reference numerals indicate the same or equivalent parts.
Claims (1)
いてオン、オフ制御される主回路素子の故障を検
出するものにおいて、第１乃至第３相の前記主回
路素子の端子間電圧、第１相の前記主回路素子の
入力側と第３相の前記主回路素子の出力側との相
間電圧をそれぞれ検出し、実質的に電圧が零のと
き有意信号を出力する電圧検出手段と、検出され
た第１相および第３相の端子間電圧信号の否定積
信号を得る第１のゲートと、検出された第１相お
よび第３相の端子間電圧信号のうち一方が有意に
なつたとき両方が有意になつたものとして否定積
信号を得る第２のゲートと、検出された第２相の
前記主回路素子の端子間電圧信号と前記第１のゲ
ートの出力信号の排他的論理和信号を得る第３の
ゲートと、前記第２のゲートの出力信号と前記制
御入力信号の排他的論理和信号を得る第４のゲー
トと、この第４のゲートの出力信号および検出さ
れた前記相間電圧信号のうち有意の側を一方入力
、前記第３のゲートの出力信号および検出された
前記相間電圧信号のうち有意の側を他方入力とし
て否定積信号を得る第５のゲートとを備え、この
第５のゲートから出力された有意の信号を故障検
出信号とすることを特徴とする故障検出回路。 In a device that detects a failure in a main circuit element that is provided in each phase of a three-phase power supply and is controlled on and off based on a control input signal, the voltage between the terminals of the main circuit element of the first to third phases, the voltage detection means for detecting interphase voltages between the input side of the main circuit element of one phase and the output side of the main circuit element of the third phase, and outputting a significant signal when the voltage is substantially zero; a first gate that obtains a negative product signal of the detected terminal voltage signals of the first phase and the third phase, and when one of the detected terminal voltage signals of the first phase and the third phase becomes significant; a second gate that obtains a negative product signal assuming that both have become significant; and an exclusive OR signal of the detected voltage signal between the terminals of the main circuit element of the second phase and the output signal of the first gate. a third gate that obtains an exclusive OR signal of the output signal of the second gate and the control input signal; and an output signal of the fourth gate and the detected phase-to-phase voltage. a fifth gate which receives a significant side of the signal as one input and receives a significant side of the output signal of the third gate and the detected phase-to-phase voltage signal as the other input to obtain a negative product signal; A failure detection circuit characterized in that a significant signal output from the gate No. 5 is used as a failure detection signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16391687U JPH0611489Y2 (en) | 1987-10-27 | 1987-10-27 | Fault detection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16391687U JPH0611489Y2 (en) | 1987-10-27 | 1987-10-27 | Fault detection circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0167574U true JPH0167574U (en) | 1989-05-01 |
| JPH0611489Y2 JPH0611489Y2 (en) | 1994-03-23 |
Family
ID=31449071
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16391687U Expired - Lifetime JPH0611489Y2 (en) | 1987-10-27 | 1987-10-27 | Fault detection circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0611489Y2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04326616A (en) * | 1991-04-26 | 1992-11-16 | Aida Eng Ltd | Load drive controller for ac power supply system |
-
1987
- 1987-10-27 JP JP16391687U patent/JPH0611489Y2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04326616A (en) * | 1991-04-26 | 1992-11-16 | Aida Eng Ltd | Load drive controller for ac power supply system |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0611489Y2 (en) | 1994-03-23 |
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