JPH04156636A - Data processor - Google Patents

Abstract

PURPOSE:To improve the speed of an operation means and to improve the processing capacity of a data processor by providing a means detecting the presence or absence of data which the operation means processes and a means detecting the presence or absence of data which is rewritten in a main memory for an auxiliary memory. CONSTITUTION:The auxiliary memory 20 detects whether data which the operation means 2 reads/writes is stored or not by the first detection means 23 and detects whether data rewritten in the main memory 4 is stored or not by the second detection means 24. An auxiliary memory control means 25 executes the read/write operation of data in response to the outputs of the first and second detection means. While a rewrite operation is executed in response to the second detection means, the operation means cannot read/write data in the auxiliary memory but it can arbitrarily execute the read/write operation of the auxiliary memory at time excepting the case. Then, the processing capacity of the data processor is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a data processing device called a workstation equipped with a plurality of CPUs (Central Processing Units).

BACKGROUND OF THE INVENTION FIG. 2 is a block diagram showing the basic configuration of a workstation 1, which is a processing device. Workstation 1
is configured to include a plurality of (two in this embodiment) CPUs 2 and 3, a main memory 4, a peripheral device 5, and a data bus 6. The CPU 2.3, the main memory 4, and the peripheral device 5 are connected via a data bus 6, and can exchange data with each other. The peripheral devices 5 include, for example, a display device 7, a hard disk device 8, and an input device 9.
including. In the workstation 1, in accordance with instructions from the input device 9, the CPTJs 2 and 3 perform various processing operations based on data or instructions read into the main memory 4 from an external storage device such as a hard disk device 8 or an auxiliary storage device. Execute.

Normally, the CPUs 2 and 3 each access the main memory 4 to read/write data.
Compared to the internal processing speed of U, the processing speed of reading and writing data to the main memory 4 is several times to several tens of times slower, and the instructions and data necessary for processing are transferred from the main memory 4 each time an instruction is executed. It is difficult to achieve high-speed processing if the data is read. Therefore, a part of the contents of the main memory 4 is read in advance to a dedicated memory that can perform data read/write processing at high speed, and instructions or data necessary for the processing are read from this dedicated memory. By doing so, it is possible to increase the processing speed. This high-speed dedicated memory is the cache memory 50.51.

Here, the operation of the cache memory 50 will be explained. Note that the cache memory 51 has the same configuration as the cache memory 50 and performs the same operation. First, part of the data in the main memory 4 is read into the cache memory 50 in advance. The CPU 2 accesses the cache memory 50 when necessary instructions or data are stored in the cache memory 50. Then, the main memory 4 is accessed only when the necessary instruction or data is not stored in the cache memory 50.

FIG. 6 is a circuit diagram showing the basic configuration of a conventional cache memory 50. The cache memory 50 includes a data memory 12, a cache monitoring device 13, and a cache control device 14. The data memory 12 is divided into a plurality of (four in this case) storage areas, and each storage area stores data or instructions read out from the data memory 4 in units of predetermined data blocks. The cache monitoring device 13 also includes a tag memory 15.
A plurality of storage areas corresponding to each storage area of the data memory 12 are set in the tag memory 15, and address data corresponding to data or instructions stored in the data memory 12 is stored. has been done.

When the CPU 2 reads necessary data or instructions, it first provides address data to the cache control device 14 .

The cache control device 14 provides the given address data to the terminal Ta of the cache monitoring device 13. Terminal T
The address data input from a is sent to comparators 16a to 1
The address data stored in the tag memory 15 is applied to one input of each of the comparators 16a to 16d, and the other input of each of the comparators 16a to 16d is applied.

The comparators 16a to 16d compare the address data given from the CPU 2 and the address data in the tag memory 15, and output, for example, a high level signal if they match. Each output of the comparators 16a to 16d is
It is applied to an OR (logical sum) circuit 17. Therefore, when the addresses match, the OR circuit 17 outputs a high level signal to the cache control device 14. This allows the cache control device 14 to know that the data or instruction that the CPU 2 attempts to access is stored in the data memory 12. Thereafter, the cache control device 14 reads data or instructions corresponding to the address data given by the CPU 2 from the data memory 12 and provides them to the CPU 2.

Problems to be Solved by the Invention As mentioned above, in the workstation 1 having a plurality of CPUs 2 and 3, each CPU has a cache memory 50.51.
is provided. Therefore, it is necessary to maintain consistency (coherence range) between the contents of the cache memories 50 and 51 corresponding to each CPU and the contents of the main memory 4. Therefore, when the contents of the cache memory are rewritten, the corresponding contents of the main memory 4 must also be rewritten. Such a memory rewriting method is called a write-through method.

In a workstation equipped with only one CPU, consistency between the cache memory and the main memory is maintained by implementing the write-through method. However, in a workstation equipped with a plurality of CPUs, even if the write-through method is implemented, consistency among memories is not necessarily maintained.

That is, in FIG. 2, the contents of the CPU 3 or the cache memory 51 are rewritten, and at the same time the contents of the corresponding main memory 4 are rewritten.
Assume that the contents of are also rewritten.

At the time of 2, the contents of this rewritten main memory 4,
If it is stored in the cache memory 50 of the CPU 2, consistency will no longer be maintained between the cache memory 50 and the main memory 4. Therefore, the data in the cache memory 50 also needs to be rewritten.

Here, referring to the above-mentioned FIGS. 2 and 6, the CPU 3
Assume that the user rewrites the contents of the cache memory 51. The CPU 3 rewrites data corresponding to a specific address in the cache memory 51. The address data and data from the CPU 3 are also given to the main memory 4, and the data is similarly rewritten in the main memory 4 as well.

At this time, address data from the CPU 3 is provided via the data bus 6 to the cache monitoring device 13 in the cache memory 50 via the terminal Ta.

The cache monitoring device 13 compares the address data from the data bus with the address data stored in the tag memory 15 to determine whether there is an identical address. If there is an identical address, the data at the corresponding address in the data memory 12 is rewritten. If there is no identical address, data will not be rewritten.

Accessing the cache memory 50 for rewriting data in this manner is called cache snooping.

In this way, the cache monitoring device 13 in the cache memory 50 is given address data from the cache control device 14 and address data from the data bus 6. Therefore, when address data is being input to the cache monitoring device 13 from the data bus 6, address data may also be provided to the cache monitoring device 13 from the cache control device 14. This phenomenon is called contention access.

When such conflicting access occurs, the cache memory 50 is
Data or instructions cannot be read from CPU2.
There is a problem that the processing speed of Furthermore, C.P.
As the number of accesses to the main memory 4 by U3 or the peripheral device 5 increases, the number of accesses to the cache monitoring device 13 (charash snoop) also increases, thereby further reducing the processing speed of the CPU 2.

Some of the workstations 1 described above are equipped with a disk cache device in conjunction with the hard disk device 8. The disk cache device is a memory having the same function as the cache memory 50, 51 described above.

In other words, when reading and/or writing data to the hard disk of the hard disk device 8, compared to dynamic RAM or static RAM, mechanical operations are involved, so it is difficult for the CPU to access directly. is too late. Therefore, by storing necessary data on the hard disk in advance in a disk cache device and reading/writing data to/from this disk cache device, it is possible to shorten the processing time required for reading/writing data. can.

In a workstation that has such a disk cache device, when the power supply to the workstation is cut off due to a power outage, for example, it is necessary to record the contents stored in the disk cache device to the hard disk for backup purposes. There is. However, the larger the memory capacity of the disk cache device, the larger the corresponding recording area on the hard disk.Furthermore, the recording area corresponding to the data stored in the disk cache device is usually not set contiguously, so the hard disk When recording on top, there is a problem in that the processing time is long, including seek time (the time required to find the recording area to be read into). Furthermore, when performing the above processing, a battery is required, and there is also the problem that the battery for bulk up becomes large.

An object of the present invention is to provide a data processing device in which the processing speed of the processing device does not decrease even if the number of accesses to a cache memory, which is a secondary memory, increases.

Another object of the present invention is to provide a data processing device that can quickly back up the contents of an auxiliary memory to a recording medium in the event of a power outage.6 Means for Solving the Problems The present invention provides a plurality of arithmetic means that perform arithmetic processing based on given data and output the arithmetic results, data to be given to the plurality of arithmetic means, and arithmetic results from the plurality of arithmetic means are stored. a main memory, which is provided for each of the plurality of calculation means, stores part of the data stored in the main memory, and has a data read/write speed faster than a data read/write speed in the main memory; and a plurality of sub-memories, and the calculation means performs data read/write processing to and from the sub-memories, and when the necessary data is not stored in the sub-memory, it reads the necessary data from the main memory. After data is read to the secondary memory, data is read and written, and when the data in one of the plurality of secondary memories is rewritten, the data in the corresponding main memory and the rewritten data are transferred to the other secondary memories. In a data processing device that rewrites data when it is stored in a memory, the secondary memory includes a first detection unit that detects whether or not data that the calculation unit attempts to read/write is stored. a second detection means for detecting whether rewritten data is stored in the main memory; and a sub-detection means for performing data read/write processing in response to the output of the first detection means or the second detection means. A data processing device characterized in that it includes a memory control means.

The present invention includes: a recording medium in which data is recorded in each predetermined unit recording area; and an auxiliary memory in which a part of the data recorded on the recording medium is stored in each unit recording area; In a data processing device that reads data from an auxiliary memory, performs arithmetic processing, and writes the arithmetic results to the auxiliary memory, when the power supply to the data processing device is cut off, the data stored in the auxiliary memory is The data processing apparatus is characterized in that data is recorded in a continuous recording area that is set in advance on a recording medium and has a capacity larger than the storage capacity of the auxiliary memory.

Function According to the present invention, the calculation means basically performs data read/write processing to the secondary memory, performs calculation processing based on the given data, and writes the calculation result to the secondary memory. . Since the data read/write speed in the secondary memory is faster than the data read/write speed in the main memory, the processing speed of the arithmetic means can be increased.

Here, when the data in the secondary memory is rewritten, the corresponding data in the main memory is also rewritten.

In the data processing device of the present invention, a plurality of sets of sub-memories corresponding to calculation means are provided. Therefore, if the data in the corresponding secondary memory is rewritten by a specific calculation means, and the data in the main memory is also rewritten at the same time, if the rewritten data is also stored in other secondary memories, Data also needs to be rewritten.

In the secondary memory, the first detection means detects whether data to be read/written by the arithmetic means is stored, and the second detection means detects whether data rewritten in the main memory is stored. Detect. The sub memory control means performs data read/write processing in response to the output of the first detection means or the second detection means. Therefore, while the data is being paraphrased in response to the output of the second detection means, the calculation means cannot read or write data to the secondary memory; The arithmetic means can arbitrarily read and write data to and from the submemory.

Here, when compared with conventional data processing devices, in conventional data processing devices, the calculation means reads and writes data that is to be processed. Since it was detected by a single detection means, even during the period of detecting whether or not rewritten data is stored in the main memory, the calculation means does not write to the secondary memory. Read/write processing could not be performed for the data.

In contrast, in the data processing device of the present invention, by providing two detection means, even during the period of detecting whether or not rewritten data is stored in the main memory, the calculation means is Read/write operations can be performed on the secondary memory. Thereby, the calculation processing speed of the calculation means can be significantly improved, and thereby the processing speed of the data processing device can be improved.

Further, according to the present invention, when the power supply to the data processing device is cut off, the data stored in the auxiliary memory is stored in a recording medium in advance in a continuous recording area having a capacity larger than the storage capacity of the auxiliary memory. recorded in

The data stored in the auxiliary memory is read from an arbitrary unit recording area on the recording medium and stored. Therefore, the read unit recording areas are not necessarily set consecutively on the recording medium. For this reason, for example, when the power supply is cut off due to a power outage and it is necessary to perform backup processing, if you try to record data in the auxiliary memory in the read unit storage area, the read unit storage area on the recording medium Time to search for the location (seek time)
Therefore, there is a problem that the time required for buffer/Vp processing becomes long, and the power supply for backup processing becomes larger accordingly.

In contrast, in the data processing device of the present invention, data in the auxiliary memory is recorded in a continuous recording area set in advance on the recording medium, thereby reducing the time required for hacking up the auxiliary memory. Furthermore, the power supply for backup processing can also be made smaller.

Embodiment FIG. 1 shows a cache memory 2 which is an embodiment of the present invention.
FIG. 2 is a circuit diagram showing the basic configuration of the workstation 1, which is a processing device. FIG. The workstation 1 includes a plurality of (two in this embodiment) CPUs 2.3, a main memory 4, peripheral devices 5, and a data bus 6. CPU2
．． 3, main memory 4, and peripheral device 5 are connected via a data bus 6, and can mutually transmit and receive data.

Peripheral device 5 includes, for example, a display device 7, a hard disk device 8, and an input device 9. Workstation 1
In accordance with instructions from the input device 9, C
The PUs 2 and 3 execute various processing operations.

Normally, the CPUs 2 and 3 each access the main memory 4 to read/write data.
Compared to the internal processing speed of the PU, the processing speed for reading and writing data to the main memory 4 is several times to several tens of times slower, and the instructions and data necessary for processing are transferred from the main memory 4 each time an instruction is executed. It is difficult to achieve high-speed processing if the data is read. Therefore, a part of the contents of the main memory 4 is read in advance to a dedicated memory that can perform data read/write processing at high speed, and instructions or data necessary for the processing are read from this dedicated memory. By doing so, the processing speed can be increased. These high-speed dedicated memories are cache memories 20 and 21.

Here, the operation of the cache memory 20 will be explained. Note that the cache memory 21 is the same as the cache memory 20.
It has the same configuration and performs the same operation.

First, part of the data in the main memory 4 is read into the cache memory 20 in advance. The CPU 2 accesses the cache memory 20 if necessary instructions or data are stored in the cache memory 20. Then, the main memory 4 is accessed only when the necessary instruction or data is not in the cache memory 20.

With reference to FIGS. 1 and 2, cache memory 20
The configuration and operation of the system will be explained. The cache memory 20 includes a data memory 22, first and second cache monitoring devices 23 and 24, and a cache control device 25. The data memory 22 is divided into a plurality of storage areas (four in this embodiment), and each storage area corresponds to one predetermined data block in the main memory 4. Also, the first and second cache monitoring devices 23.
The first and second tag memories 26 and 27 in 24 correspond to the storage areas 22a, 22d of the data memory 22,
Storage areas 26a to 26d; 27a to 27d, respectively
It is divided into. The storage contents of the first and second tag memories are the same, and address data corresponding to data or instructions stored in the data memory 22 is stored in each storage area 22a to 22d of the data memory 22.

The first cache monitoring device 23 stores the data corresponding to the address data given from the CPU 2 in the data memory 22.
This is a device to monitor whether or not the data is stored in the . Further, the second cache monitoring device 24 is connected to the data bus 6.
This function is used to monitor whether the rewritten data is stored in the data memory 22 when the contents of the main memory 4 are rewritten by the address data given by the CPU 3 or the peripheral device 5 (during cache starvation). It is a device.

When the CPU 2 accesses the data memory 22, it first gives address data to the cache control device 25. The cache control device 25 provides the applied address data to the terminal T1 of the first cache monitoring device 23. Address data input from terminal T1 is applied to one input of each of comparators 28a to 28d. Further, each other input of the comparators 28a to 28d is connected to a first tag memory 26.
Atsushi data output from each of the storage areas 26a to 26d is provided, respectively. The comparators 28a to 28d are
The address data given from the CPU 2 and the address data in the first tag memory 26 are compared, and if there is an identical address, a high level signal is output, for example. Each output of the comparators 28a to 28d is provided to an OR (logical sum) circuit 30.

Therefore, if the address data match, OR
A high level signal from the circuit 30 is sent to the cache control device 2.
given to 5. As a result, the cache control device 2
5 can know that the data that the CPU 2 is trying to access is stored in the data memory 22.

Thereafter, the cache control device 25 controls the data memory 22
The data or command corresponding to the address data given from the CPU 2 is read out and given to the CPU 2.

Alternatively, the data corresponding to the given address data is rewritten. If data is rewritten,
The cache controller 25 outputs address data corresponding to the rewritten data to the data bus 6. As a result, the data in the main memory 4 is rewritten and, if corresponding data exists, the data in the cache memory 21 is rewritten.

Next, assume that the data in the main memory 4 is rewritten by the CPU 3 or the peripheral device 5. In this case, address data of the rewritten data is given to the cache memory 20 from the data bus 6 via the terminal T2 to the second cache monitoring device 24. Address data applied from terminal T2 is applied to one input of each of comparators 29a to 29d. Further, the other inputs of the comparators 29a to 29d are connected to the respective storage areas 27a to 27a of the second tag memory 27.
Address data output from 27d is given to each of them. The two comparators a to 29d compare the address data given from the data bus 6 and the address data output to the second tag memory 27, and if they match, for example, go high and send a help message. Outputs the signal. Comparator 29a
Each output of 29d to 29d is given to an OR (logical sum) circuit 31.

Therefore, if the address data match, a high and low signal is output to the cache control device 25.

This allows the cache control device 25 to know that the same data as the data in the main memory 4 rewritten by the CPU 3 or the peripheral device 5 is stored in the data memory 22 .

Thereafter, based on the address data given from the data bus 6 and the rewritten data, the cache control device 25 selects the data in the storage area having the corresponding address in the data memory 22 and the address in the tag memory 26, 27. Rewrite data.

By using two cache monitoring devices 23 and 24 in this way, it is possible to avoid conflicting accesses. However, if the addresses match due to read access or write access from C, P U 2 or read access or write access from CPU 3 or peripheral device 5, it is necessary to change the contents of data memory 22. Conflict access occurs while this rewriting operation is being performed.

Here, the operation of the cache memory 20 will be explained for each of the two modes adopted to maintain memory consistency in the workstation 1.

■Write-through mode In write-through mode, cache memory 20
uses the second cache monitoring device 24 to monitor only write accesses. During write access from the data bus 6, if the addresses do not match, no processing is performed. If the addresses match, the cache memory 20 cannot be accessed from the CPtJ2 during operations such as invalidating the data memory 22, but in other cases, no conflicting access occurs; CPU 2 can access cache memory 20 .

■Copy back mode In copy hack mode, cache memory 2
0 uses the second cache monitoring device 24 to monitor both read accesses and write accesses from the data bus 6. If the addresses do not match, no processing action is taken. If the addresses match, the CPU 2 cannot access the cache memory 20 while performing operations such as supplying or fetching data in response to read accesses and write accesses, but in other cases CPU without contention access.
2 can access the cache memory 20.

In this way, the contents of the main memory 4 are rewritten by the CPU 3 or the peripheral devices, and this causes a character cache snoop to the cache memory 20 (whether data corresponding to the data rewritten in the main memory 4 is stored in the data memory 22). As long as the number of accesses to the cache memory 20 (to determine whether the address is correct or not) increases, the access operation from the CPU 2 to the cache memory 201\ is not affected as long as the addresses do not match.

As a result, CPU2 in workstation 1
The processing speed and operating efficiency of the system can be significantly improved. In addition, a cache memory 21 corresponding to the CPU 3
Since the configuration of the cache memory 20 is the same, the CP
The processing speed and operating efficiency in U3 are also significantly improved.

FIG. 3 is a block diagram showing the configuration related to the hard disk device 8. As shown in FIG. A disk cache device 35 is interposed between the data bus 6 and the hard disk device 8. The disk cache device 35 is provided for the same purpose as the cache memory 20.21 described above.)
Ru.

The processing speed of data read/write control from bar 1 to disk device 8 is faster than the processing speed of data read/write in dynamic/remote RAM, state/reram, etc. The more you do, the slower it becomes.

In the past, data that is expected to be relatively necessary for each process performed on the workstation 1 is stored in advance in the child cache device 35. In such a case, the disk cache device 35 is first accessed, and if there is a necessary seek, data read/write control is performed in the disk cache device 35. This makes it possible to significantly shorten the time required to control the reading and writing of data in the hard disk device 8.

FIG. 4 is a flowchart for explaining the processing operation of the disk cache device 35 when the power supply is cut off, and FIG. 5 is a diagram for explaining the data writing operation to the hard disk 36 when the power supply is cut off. be. In step a1, it is determined whether the power supply to the workstation 1 has been cut off due to a power outage or the like. When the power supply is cut off, the contents stored in the disk cache device 35 in step a2 are
The data is written in a continuous recording area CN set in advance on the hard disk 36. At this time, position information (2) representing the recording areas PA to PD where each of the stored contents A to D should originally be recorded is also written to the continuous recording area CN.

In step a3, it is determined whether the power supply has been restored. When the power supply is restored, in step a4, the hard disk device 8 writes the contents A to D recorded in the continuous recording area CN to the recording areas PA to PD where they should originally be written based on the position information I.

As a result, the time required for backing up the contents stored in the disk cache device 35 when the power supply is cut off such as when a power outage occurs can be reduced compared to the conventional method. That is, by writing the contents of the disk cache device 35 into the predetermined continuous recording area CN, the time equivalent to the seek time required when searching for a recording area on the hard disk 36 can be shortened. This makes it possible to reduce the capacity of the backup buffer.

Effects of the Invention As described above, according to the present invention, the arithmetic means does not operate on the sub-memories except during the period when data in the sub-memory is being rewritten in order to maintain consistency between the main memory and a plurality of sub-memories. Data can be arbitrarily read/written to the memory, and the calculation speed of the calculation means is improved. Thereby, the processing speed of the data processing device can be improved.

Further, according to the present invention, the time required for backup processing of the auxiliary memory can be shortened, and thereby the capacity of the backup power source can be reduced.

[Brief explanation of drawings]

FIG. 1 shows a cache memory 2 which is an embodiment of the present invention.
FIG. 2 is a circuit diagram showing the basic configuration of the workstation 1 as a processing device equipped with the cache memory 20 shown in FIG. 1, and FIG.
4 is a flowchart for explaining the operation of the hard disk device 8. FIG. 5 is a diagram for explaining the operation of the hard disk device 8 when power supply is cut off. , FIG. 6 is a circuit diagram showing the basic configuration of a conventional cache memory 50. 1...Workstation, 2.3-cpU, 4 Main memory, 5 Peripheral device, 6...Data bus, 8 Hard disk device, 20.21 Kya nosh memory,
22 data memory, 23...first cache monitoring device, 24...second cache monitoring device, 25...cash monitoring device;
Soshu control device, 26 - 1st tag memory, 27... 2nd tag memory, 28a - 28d; 29a - 29d - Comparator, 30. 31 OR circuit, 35 Disk cache device! , 36 ・Hard disk agent Patent attorney Number of strokes Keibe 1st figure jllZ Figure 3 Figure 6

Claims (2)

[Claims] (1) A plurality of arithmetic means that perform arithmetic processing based on given data and output the arithmetic results, and a main body that stores the data given to the plurality of arithmetic means and the arithmetic results from the plurality of arithmetic means. a memory, provided for each of the plurality of calculation means, in which a part of the data stored in the main memory is stored, and a data read/write speed is faster than a data read/write speed in the main memory; and a plurality of sub-memories, the calculation means performs data read/write processing with the sub-memories, and when the necessary data is not stored in the sub-memories, the necessary data is transferred from the main memory to the sub-memories. When data is read/written after being read to the main memory and the data in one of the plurality of submemories is rewritten, the data in the corresponding main memory and the rewritten data are stored in the other submemory. In the data processing device, the data processing device rewrites the data when the data is being read/written, and the sub memory includes: a first detection means for detecting whether data to be read/written by the calculation means is stored; a second detection means for detecting whether rewritten data is stored in the memory; and a sub-memory control means for performing data read/write processing in response to the output of the first detection means or the second detection means. A data processing device comprising: (2) A recording medium in which data is recorded in each predetermined unit recording area, and an auxiliary memory in which a part of the data recorded on the recording medium is stored in each unit recording area, and a part of the data recorded in the recording medium is stored in each unit recording area, and In a data processing device that reads data, performs arithmetic processing, and writes the arithmetic results to an auxiliary memory, when the power supply to the data processing device is cut off, the data stored in the auxiliary memory is transferred to the recording medium. A data processing device characterized in that recording is performed in a continuous recording area that is set in advance and has a capacity larger than the storage capacity of the auxiliary memory.