JPH04155926A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH04155926A JPH04155926A JP28248390A JP28248390A JPH04155926A JP H04155926 A JPH04155926 A JP H04155926A JP 28248390 A JP28248390 A JP 28248390A JP 28248390 A JP28248390 A JP 28248390A JP H04155926 A JPH04155926 A JP H04155926A
- Authority
- JP
- Japan
- Prior art keywords
- wirings
- aluminum wirings
- aluminum
- interlayer insulating
- dummy
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 25
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 25
- 239000011229 interlayer Substances 0.000 claims abstract description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 8
- 229920005591 polysilicon Polymers 0.000 abstract description 8
- 239000000758 substrate Substances 0.000 abstract description 5
- 238000006073 displacement reaction Methods 0.000 abstract description 4
- 238000007789 sealing Methods 0.000 abstract 3
- 238000005538 encapsulation Methods 0.000 description 4
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置に関し、特に、微細化パターンを
必要とする半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device requiring a fine pattern.
従来の半導体装置は、第２図に示すように、長いアルミ
ニウム配線１−１．・・・の下方に図示しない層間絶縁
膜を介してポリシリコン膜２−１．・・・を設け、コン
タクト孔５−１．・・・部でアルミニウム配線とポリシ
リコン膜を接続することにより、モールド封入時の応力
による、アルミニウム配線のずれ、切れ、短絡の防止を
図っていた。As shown in FIG. 2, a conventional semiconductor device has long aluminum wiring lines 1-1. . . . below the polysilicon film 2-1 through an interlayer insulating film (not shown). ... are provided, and the contact hole 5-1. By connecting the aluminum wiring and the polysilicon film at the .
この従来の半導体装置では、モールド封入時の応力によ
るアルミニウム配線のずれ、切れ、もしくは短絡防止の
目的で下部にポリシリコン膜を配置しコンタクトをとっ
ているため、その部分で幅が広くなるため、アルミニウ
ム配線間隔を狭くする上で障害となり、最小寸法間隔パ
ターンの実現ができないという問題点があった。In this conventional semiconductor device, a polysilicon film is placed at the bottom to make contact in order to prevent the aluminum wiring from shifting, breaking, or shorting due to stress during mold encapsulation, so the width becomes wider at that part. This poses a problem in that it becomes an obstacle to narrowing the aluminum wiring spacing, making it impossible to realize a pattern with the minimum dimension spacing.
本発明の半導体装置は、隣接する２本のアルミニウム配
線で挟まれた領域の下方に層間絶縁膜を介してダミー配
線が配置されているというものである。In the semiconductor device of the present invention, a dummy wiring is arranged below a region sandwiched between two adjacent aluminum wirings with an interlayer insulating film interposed therebetween.
次に本発明について、図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図（ａ）は本発明の一実施例の半導体装置の平面図
、第１図（ｂ）は第１図（ａ ） ｆ） Ｘ −Ｘ線断
ＷＩ図である。FIG. 1(a) is a plan view of a semiconductor device according to an embodiment of the present invention, and FIG. 1(b) is a sectional view taken along line X--X in FIGS. 1(a) to 1(f).
半導体基板に素子などを形成したものを基板４とし、そ
の上にポリシリコン膜からなるダミー配線３−１．３−
２１．・・・が設けられている。更に層間絶縁膜６を介
してアルミニウム配線１−１゜１−２．・・・が設けら
れている。そうして、ダミー配線は、隣接するアルミニ
ウム配線の間の領域の下方に配置されている。又、ダミ
ー配線間の層間絶縁膜の凹部にアルミニウム配線がきて
いる。A substrate 4 is a semiconductor substrate on which elements and the like are formed, and dummy wiring 3-1.3- made of a polysilicon film is formed on the substrate 4.
21. ...is provided. Furthermore, aluminum wiring 1-1°1-2. ...is provided. The dummy wiring is then placed below the region between adjacent aluminum wirings. Further, the aluminum wiring is placed in the recessed part of the interlayer insulating film between the dummy wirings.
従来例のようにポリシリコン膜とのコンタクト領域を持
っていないため、アルミニウム配線とアルミニウム配線
の間隔を、最小寸法とすることができる。Since it does not have a contact region with the polysilicon film unlike the conventional example, the interval between the aluminum wirings can be set to the minimum dimension.
また、アルミニウム配線が層間絶縁膜の凸部によって挟
まれているので、モールド封入時の応力に強くなってお
り、モールド封入時の応力におけるアルミニウム配線の
ずれ、切れ、あるいは短絡を防止できる。Furthermore, since the aluminum wiring is sandwiched between the convex portions of the interlayer insulating film, it is strong against stress during mold encapsulation, and it is possible to prevent displacement, breakage, or short circuit of the aluminum wiring due to stress during mold encapsulation.
以上説明したように本発明は、ダミー配線を隣接するア
ルミニウム配線の間の領域の下方に設けることにより、
アルミニウム配線間隔を最小寸法にし、かつモールド封
入時における応力によるアルミニウム配線のずれ、切れ
あるいは短絡を防止し、かつ最小寸法間隔パターンを実
現できるという効果を有する。As explained above, the present invention provides dummy wiring below the area between adjacent aluminum wirings.
This has the effect of minimizing the aluminum wiring spacing, preventing displacement, breakage, or short circuit of the aluminum wiring due to stress during mold encapsulation, and realizing a minimum dimension spacing pattern.
第１図（ａ）は本発明の一実施例の平面図、第１図（ｂ
）は第１図＜ａ）のＸ−Ｘ線断面図、第２図は従来例の
平面図である。
Ｈ，１−２，１−３，１−４・・・アルミニウム配線、
２−１．２−２．２−３・・・ポリシリコン膜、３−１
．３−２１．３−２２．・・・、・・・ダミー配線、４
・・・基板、５−１．５−２．５−３・・・コンタクト
孔、６・・・層間絶縁膜。FIG. 1(a) is a plan view of an embodiment of the present invention, and FIG. 1(b) is a plan view of an embodiment of the present invention.
) is a sectional view taken along the line X--X of FIG. 1<a), and FIG. 2 is a plan view of the conventional example. H, 1-2, 1-3, 1-4... aluminum wiring,
2-1.2-2.2-3...Polysilicon film, 3-1
．． 3-21.3-22. ..., ...dummy wiring, 4
. . . Substrate, 5-1.5-2.5-3 . . . Contact hole, 6 . . . Interlayer insulating film.
Claims (1)
方に層間絶縁膜を介してダミー配線が配置されているこ
とを特徴とする半導体装置。A semiconductor device characterized in that a dummy wiring is arranged below a region sandwiched between two adjacent aluminum wirings with an interlayer insulating film interposed therebetween.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2282483A JP2674872B2 (en) | 1990-10-19 | 1990-10-19 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2282483A JP2674872B2 (en) | 1990-10-19 | 1990-10-19 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04155926A true JPH04155926A (en) | 1992-05-28 |
| JP2674872B2 JP2674872B2 (en) | 1997-11-12 |
Family
ID=17653027
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2282483A Expired - Lifetime JP2674872B2 (en) | 1990-10-19 | 1990-10-19 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2674872B2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63240045A (en) * | 1987-03-27 | 1988-10-05 | Matsushita Electric Ind Co Ltd | Semiconductor device |
| JPH01108748A (en) * | 1987-10-21 | 1989-04-26 | Nec Corp | Semiconductor device having multilayer interconnection structure |
-
1990
- 1990-10-19 JP JP2282483A patent/JP2674872B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63240045A (en) * | 1987-03-27 | 1988-10-05 | Matsushita Electric Ind Co Ltd | Semiconductor device |
| JPH01108748A (en) * | 1987-10-21 | 1989-04-26 | Nec Corp | Semiconductor device having multilayer interconnection structure |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2674872B2 (en) | 1997-11-12 |
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