JPH04155909A - Manufacture of solid electrolytic capacitor - Google Patents

Manufacture of solid electrolytic capacitor

Info

Publication number
JPH04155909A
JPH04155909A JP28159790A JP28159790A JPH04155909A JP H04155909 A JPH04155909 A JP H04155909A JP 28159790 A JP28159790 A JP 28159790A JP 28159790 A JP28159790 A JP 28159790A JP H04155909 A JPH04155909 A JP H04155909A
Authority
JP
Japan
Prior art keywords
valve metal
layer
metal foils
metal foil
semiconductor layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP28159790A
Other languages
Japanese (ja)
Inventor
Kazumi Naito
一美 内藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Resonac Holdings Corp
Original Assignee
Showa Denko KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Showa Denko KK filed Critical Showa Denko KK
Priority to JP28159790A priority Critical patent/JPH04155909A/en
Publication of JPH04155909A publication Critical patent/JPH04155909A/en
Pending legal-status Critical Current

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  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

PURPOSE:To prevent a capacity from getting into an unstable condition due to splashes of solution by covering a valve metal foil of an element with another valve metal foil. CONSTITUTION:One end of a valve metal foil 2 in the longitudinal direction is coated with a protective valve metal foil 1 which prevents influences of splashes of solution from occurring. The ends of the valve metal foils 2 coated with the valve metal foils 1 are connected to a long side 3a of a rectangular metal sheet 3 at fixed intervals so that the valve metal foils 1, 2 may be at right angles with the side 3a. With a part 5 of the end of the valve metal foil 2 coated with the valve metal foil 1 being undone, a semiconductor layer 7 and conductor layer 8 are deposited in sequence on a part of the valve metal foils 1, 2 which is under a line 6. Then, the valve metal foils 1 and 2 are separated from each other to obtain a solid electrolytic capacitor element 10 which is composed of the valve metal foil 2. A lead wire is mounted to a part of the valve metal foil part of the element on which no semiconductor layer 7 is deposited and to a part on which the conductor layer 8 is formed.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、希望する容量のものが安定して量産できる固
体電解コンデンサの製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing solid electrolytic capacitors that can be stably mass-produced with a desired capacity.

〔従来の技術〕[Conventional technology]

近時電子機器の軽小化はとどまることなく進み、すべて
の電気部品の小形化が要求されている。
BACKGROUND OF THE INVENTION In recent years, electronic devices have been becoming lighter and smaller, and all electrical components are required to be smaller.

固体電解コンデンサにおいては、誘電体酸化被膜層の上
に半導体層を形成した内部素子によって、その容量を引
出しているが、内部素子の寸法を可能なかぎり小さくす
ることによって、上記小型化に対する要求に応えようと
している。
In solid electrolytic capacitors, the capacity is derived from an internal element that has a semiconductor layer formed on a dielectric oxide film layer, but by reducing the dimensions of the internal element as much as possible, it is possible to meet the demand for miniaturization. I'm trying to respond.

しかし、内部素子の寸法が小さくなると、半導体層を形
成する際に、半導体層を形成する液がはね上り、目的と
する容量の固体電解コンデンサを安定して製造すること
ができない欠点があった。
However, as the dimensions of the internal elements become smaller, the liquid used to form the semiconductor layer splatters, making it impossible to stably manufacture solid electrolytic capacitors with the desired capacity. .

これを解決するものとして、シリコーン、ポリアミド、
弗素樹脂系などの絶縁塗料を所定部分に塗布し、絶縁樹
脂皮膜を形成して半導体層形成時の液のはね上りにより
、上部に付着するのを防止する方法(特開昭59−13
2614号公報)等が提案されている。
Silicone, polyamide,
A method of applying an insulating paint such as a fluororesin to a predetermined area to form an insulating resin film to prevent the liquid from adhering to the upper part due to splashing during the formation of a semiconductor layer (Japanese Patent Laid-Open No. 59-13
No. 2614) and the like have been proposed.

〔発明か解決しようとする課題〕・ しかしながら、絶縁塗料を塗布する場合、塗料の粘度か
高すぎると、絶縁樹脂皮膜を形成することか困難であり
、また粘度が低すぎると塗料のしみ込みによってかえっ
て作製した素子の容量を不安定化する不都合が生じる。
[Problem to be solved by the invention]- However, when applying insulating paint, if the viscosity of the paint is too high, it is difficult to form an insulating resin film, and if the viscosity is too low, the paint may seep into the coating. On the contrary, the problem arises that the capacitance of the manufactured element becomes unstable.

特に工業的な規模で多数個の素子の絶縁樹脂皮膜を形成
するには、絶縁塗料の粘度管理が極めて難しくなる。
In particular, when forming insulating resin films for a large number of devices on an industrial scale, it becomes extremely difficult to control the viscosity of the insulating paint.

そのため、絶縁塗料を塗布して絶縁樹脂皮膜形成する代
りに粘着性の樹脂テープを付着させる方法も考えられう
るが、誘電体酸化皮膜層と粘着性樹脂テープとの接着は
、半導体層形成時の誘電体酸化皮膜層の劣化を修復する
ために行う後化成時や、導電体層を形成するために導電
ペースト槽に浸漬した際に、溶媒によってはがされ易い
。また、絶縁樹脂には、絶縁樹脂を作製した時の触媒や
各種添加剤か多数含まれているため、後化成溶媒や導電
ヘースト溶媒に溶は出してフンテンサ素子に悪影響を及
ぼし信頼性を損う不都合かあった。
Therefore, instead of applying an insulating paint to form an insulating resin film, a method of attaching an adhesive resin tape may be considered, but the adhesion between the dielectric oxide film layer and the adhesive resin tape is difficult to achieve during the formation of the semiconductor layer. It is easily peeled off by a solvent during post-chemical formation to repair deterioration of the dielectric oxide film layer or when immersed in a conductive paste bath to form a conductive layer. In addition, insulating resin contains a large number of catalysts and various additives used during the production of insulating resin, which may be dissolved in post-forming solvents and conductive heaste solvents, adversely affecting the Funtensa element and impairing its reliability. There was some inconvenience.

本発明は上記の事情に鑑みてなされたもので、半導体層
を形成する液のはね上りにより、容量か不安定化するの
を防止し、また絶縁樹脂塗料等を用ないので、これらに
含まれる触媒や、各種添加剤の影響がなく、しかも量産
に適した固体電解コンデンサの製造方法を提供すること
を目的とする。
The present invention has been made in view of the above circumstances, and prevents the capacitance from becoming unstable due to splashing of the liquid forming the semiconductor layer, and does not use insulating resin paint, etc. The purpose of the present invention is to provide a method for manufacturing solid electrolytic capacitors that is free from the effects of catalysts and various additives and is suitable for mass production.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の固体電解コンデンサの製造方法においては、 弁金属層1によって長手方向の一方の端部が挟持された
狭幅長方形の弁金属層2の複数枚を、少なくとも直線状
の一辺を有する金属板3の上記一辺に対して直角となる
ように、上記弁金属層1によって挟持された一方の端部
を接続して並列に取付け、これら弁金属層1.2の表面
に誘電体酸化皮膜層を形成し、次いで、弁金属1.2の
一方の端部側を残して順次半導体層、導電体層を形成し
た後、上記弁金属層1.2の半導体層か形成されていな
い部分て、弁金属層1および2を切断分離する工程を有
せしめることを問題解決の手段とした。
In the method for manufacturing a solid electrolytic capacitor of the present invention, a plurality of narrow rectangular valve metal layers 2 having one end in the longitudinal direction sandwiched by the valve metal layer 1 are replaced by a metal plate having at least one linear side. One end sandwiched by the valve metal layer 1 is connected and attached in parallel so as to be perpendicular to the one side of the valve metal layer 1.2, and a dielectric oxide film layer is formed on the surface of the valve metal layer 1.2. Then, after sequentially forming a semiconductor layer and a conductor layer except for one end side of the valve metal layer 1.2, the portion of the valve metal layer 1.2 where the semiconductor layer is not formed is used to form a valve. The solution to this problem was to include a step of cutting and separating the metal layers 1 and 2.

この場合、弁金属層1,2として表面に誘電体皮膜が形
成された弁金属層を用い、これに順次半導体層、導電体
層を形成してもよい。
In this case, valve metal layers having a dielectric film formed on their surfaces may be used as the valve metal layers 1 and 2, and a semiconductor layer and a conductor layer may be sequentially formed thereon.

〔作用〕[Effect]

本発明の方法は上記の構成となっているので弁金属層2
の一方の端部は、弁金属層1によって被覆保護され、液
のはね上りの影響が発生しない。
Since the method of the present invention has the above structure, the valve metal layer 2
One end of the valve is covered and protected by the valve metal layer 1, so that the influence of liquid splashing does not occur.

〔実施例〕〔Example〕

第1図ないし第5図は、本発明の固体電解コンデンサの
製造方法の一実施例を示すもので、図中符号1は、誘電
体層を形成する液のはね上りの影響が発生するのを防止
する保護用の長方形の弁金属層である。この弁金属層1
によって、狭幅長方形の弁金属層2の長手方向の一方の
端部が挟持被覆される。
1 to 5 show an embodiment of the method for manufacturing a solid electrolytic capacitor according to the present invention, and the reference numeral 1 in the figures indicates the effect of splashing of the liquid forming the dielectric layer. It is a protective rectangular valve metal layer that prevents. This valve metal layer 1
Thus, one longitudinal end of the narrow rectangular valve metal layer 2 is sandwiched and covered.

上記弁金属層1の弁金属層2によって挟持被覆されてい
る一方の端部は、長方形の金属板3の長手辺3aに、辺
3aに対して弁金属層1.2か直角となるように、所定
の間隔をおいて並列に接続される。
One end of the valve metal layer 1 that is sandwiched and covered by the valve metal layer 2 is attached to the long side 3a of the rectangular metal plate 3 so that the valve metal layer 1.2 is perpendicular to the side 3a. , are connected in parallel at a predetermined interval.

上記弁金属の表面には、誘電酸化皮膜層4か形成される
か、この場合、予め誘電酸化皮膜層4か形成されている
弁金属層1,2を用いることによってこの操作を省略し
てもよい。
A dielectric oxide film layer 4 may be formed on the surface of the valve metal, or in this case, this operation may be omitted by using the valve metal layers 1 and 2 on which the dielectric oxide film layer 4 has been formed in advance. good.

次いて弁金属層lによって挟持されている一方の端部側
の一部(以下基部という)5を残して、線6より下の部
分の弁金属層1,2に順次半導体層7、導電体層8か積
層される。
Next, a semiconductor layer 7 and a conductor are sequentially applied to the valve metal layers 1 and 2 below the line 6, leaving a part (hereinafter referred to as the base) 5 on one end side sandwiched by the valve metal layer l. Layer 8 is laminated.

これを上記線6より上の部分である線9て切断するか、
或いは、金属板3と接続されている部分を分離すると、
弁金属層1と2が離れ、弁金属層2よりなる固体電解コ
ンデンサ素子(以下素子という)10が得られる。これ
ら素子10の半導体層7が形成されていない弁金属箔部
分と導電体層8が形成されている部分にそれぞれリード
線(図示せず)が取付けられる。
Either cut this at line 9, which is the part above line 6, or
Or, if the part connected to the metal plate 3 is separated,
The valve metal layers 1 and 2 are separated, and a solid electrolytic capacitor element (hereinafter referred to as element) 10 made of the valve metal layer 2 is obtained. Lead wires (not shown) are attached to the valve metal foil portions of these elements 10 where the semiconductor layer 7 is not formed and to the portions where the conductor layer 8 is formed.

本発明に使用される弁金属層1.2としては、アルミニ
ウム、タンタル、ニオブ、チタンあるいはこれらを基質
とする合金等弁作用を有する金属箔がいずれも使用でき
る。
As the valve metal layer 1.2 used in the present invention, any metal foil having a valve action such as aluminum, tantalum, niobium, titanium, or an alloy having these as a substrate can be used.

これら弁金属層1,2は表面がエツチングされていても
よい。エツチング方法としては、電気化学的にエツチン
グする等公知の方法が用いられる。
The surfaces of these valve metal layers 1 and 2 may be etched. As the etching method, a known method such as electrochemical etching may be used.

また、上記弁金属層1,2は、表面に予め誘電体酸化皮
膜層4が形成されているものを用いてもよい。
Furthermore, the valve metal layers 1 and 2 may have a dielectric oxide film layer 4 formed on their surfaces in advance.

弁金属層2を覆い挟持する弁金属層1の形状は、少なく
とも直線状の対向する二辺を有する形状であり、幅は前
記狭幅長方形状の弁金属層2の幅より大きいことが肝要
で、特に長方形のものが好ましい。上記弁金属層1は、
これに覆い挟持された弁金属層2に、半導体層形成時に
弁金属層2の端部から半導体層がはい上がることを防ぐ
だけの幅が有ればよく一般に弁金属層2より数av幅の
大きなものが用いられる。
It is important that the shape of the valve metal layer 1 that covers and sandwiches the valve metal layer 2 is a shape having at least two linear opposing sides, and that the width is larger than the width of the narrow rectangular valve metal layer 2. , especially rectangular ones are preferred. The valve metal layer 1 is
It is sufficient that the valve metal layer 2 covered and sandwiched therein has a width sufficient to prevent the semiconductor layer from creeping up from the end of the valve metal layer 2 during the formation of the semiconductor layer. Large ones are used.

また、弁金属層1で弁金属層2を覆う部分の大きさは、
作製するコンデンサの容量によって異なり、一定の希望
容量を得るために弁金属層1の半導体層を形成する部分
を除いて覆われる。
Furthermore, the size of the portion of the valve metal layer 1 that covers the valve metal layer 2 is as follows:
The capacitance varies depending on the capacitance of the capacitor to be manufactured, and in order to obtain a certain desired capacitance, the valve metal layer 1 is covered except for the portion where the semiconductor layer is to be formed.

また、弁金属層lが弁金属層2を覆う方法として、2枚
の弁金属層1で表裏から弁金属層2を覆う方法および、
1枚の弁金属層1を折りたたんで弁金属層2にかぶせて
覆う方法等があり、いずれを用いてもよい。
Further, as a method of covering the valve metal layer 2 with the valve metal layer 1, a method of covering the valve metal layer 2 from the front and back with two valve metal layers 1, and
There are methods of folding one valve metal layer 1 and covering the valve metal layer 2, and any of these methods may be used.

上記、弁金属層lで挟持被覆された弁金属層2が接続さ
れる金属板3は、弁金属層を接続できる機能と強度を有
し、かつ弁金属層を接続してもたわまなければ特に制限
は無く、例えば、ステンレス、鋼、銅、鉄、アルミニウ
ム等があげられる。
The metal plate 3 to which the valve metal layer 2 sandwiched and coated with the valve metal layer l is connected must have the function and strength to connect the valve metal layer, and must not bend even when the valve metal layer is connected. There are no particular limitations, and examples include stainless steel, steel, copper, iron, and aluminum.

金属板3は所定の長さの直線状の一辺を有すればよいが
、通常長方形のものが用いられその長さは弁金属層1の
幅と接続する個数と、間隔によって決まる。金属板3の
厚みは必要とする上記長さによるたわみを防止するため
、長い場合には厚くされるが、通常0.1a+m〜数■
の厚さのものが用いられる。
The metal plate 3 only needs to have one linear side of a predetermined length, but usually a rectangular one is used, and its length is determined by the width of the valve metal layer 1, the number of connected plates, and the spacing. The thickness of the metal plate 3 is increased if it is long in order to prevent deflection due to the above-mentioned required length, but it is usually 0.1a+m to several inches thick.
A material with a thickness of .

上記金属板3と弁金属層1および弁金属層2との接続方
法は、溶接、半田づけ、ボルト締め、スボ、ト溶接等、
従来公知の電気的、機械的方法が用いられる。
The method of connecting the metal plate 3 to the valve metal layer 1 and the valve metal layer 2 includes welding, soldering, bolting, groove welding, etc.
Conventionally known electrical and mechanical methods are used.

本発明において弁金属苗土に形成される誘電体酸化皮膜
層(以下酸化皮膜層という)4は、弁金属自体の酸化皮
膜層であっても、あるいは、弁金属苗土に設けられた、
他の誘電体の酸化物からなる酸化皮膜層であってもよい
が、特に弁金属自体の酸化物からなる酸化皮膜層か好ま
しい。上記いずれの場合においても、酸化皮膜層4を形
成する方法としては、従来公知の方法を用いることがで
きる。例えば、弁金属層として、アルミニウムを用いる
場合、アルミニウム箔の表面を電気化学的にエツチング
し、さらにほう酸およびほう酸アンモニウムの水溶液、
リン酸とリン酸アンモニウムの水溶液、アジピン酸アン
モニウム水溶液、或いは修酸と修酸アンモニウム水溶液
中などで電気化学的に処理すればアルミニウム箔上にア
ルミナ銹電体からなる酸化皮膜層が形成される。
In the present invention, the dielectric oxide film layer (hereinafter referred to as oxide film layer) 4 formed on the valve metal seedling soil may be an oxide film layer of the valve metal itself, or may be an oxide film layer provided on the valve metal seedling soil.
Although an oxide film layer made of an oxide of another dielectric substance may be used, an oxide film layer made of an oxide of the valve metal itself is particularly preferable. In any of the above cases, a conventionally known method can be used to form the oxide film layer 4. For example, when aluminum is used as the valve metal layer, the surface of the aluminum foil is electrochemically etched, and an aqueous solution of boric acid and ammonium borate is added.
When electrochemically treated in an aqueous solution of phosphoric acid and ammonium phosphate, an aqueous ammonium adipate solution, or an aqueous solution of oxalic acid and ammonium oxalate, an oxide film layer made of an alumina electrolyte is formed on the aluminum foil.

また、本発明に使用される半導体層7の組成および形成
方法は、特に制限ないが、コンデンサの性能を高めるに
は、本出願人が先に提出した二酸化鉛と硫酸鉛を主成分
とする半導体層を化学的析出法によって形成する方法(
特開昭63−51621号公報)、あるいは二酸化鉛を
主成分とする半導体層を電、気化学的析出法によって形
成する方法(特開昭62−185307号公報)を用い
るのが好ましい。
The composition and formation method of the semiconductor layer 7 used in the present invention are not particularly limited; A method in which the layer is formed by chemical deposition (
It is preferable to use a method of forming a semiconductor layer containing lead dioxide as a main component by electrochemical deposition (Japanese Patent Application Laid-open No. 62-185307).

上記半導体層7の表面に形成される導電体層8は、例え
ば導電ペーストを塗布固化させる方法、メツキ、金属蒸
着、耐熱性の導電樹脂フィルムの積層など公知の方法に
よって形成される。
The conductor layer 8 formed on the surface of the semiconductor layer 7 is formed by a known method such as applying and solidifying a conductive paste, plating, metal vapor deposition, or laminating a heat-resistant conductive resin film.

マタ、導電ペーストとしては、金属粉、導電性ポリマを
主成分とする公知のものが採用できる。
As the conductive paste, any known paste containing metal powder or conductive polymer as a main component can be used.

上記のようにしてつくられリード線が取付けられた素子
10は、樹脂モールド、樹脂ケース、金属製の外装ケー
ス、樹脂のデツピング、ラミネートフィルムによる外装
などによって、各種用途の汎用コンデンサ製品が得られ
る。
The element 10 made as described above and having lead wires attached thereto can be molded into a resin mold, a resin case, a metal exterior case, resin dumping, exterior with a laminate film, etc. to obtain a general-purpose capacitor product for various uses.

なお、上記説明では、素子IOを金属板3か本分離した
後、リード線を接続して外装を施したズリード線を接続
してから素子10を金属板3か1分離しても、さらに外
装を施してから金属板かし分離してもよい。
In the above explanation, even if the element IO is separated by three metal plates, the lead wires are connected and the lead wires are connected, and the element 10 is separated by three or one metal plates, the outer part is further removed. The metal plates may be separated after applying this process.

〔実施例1〕 長さ101m、幅7III11、厚さ0.1mmのアル
ミニウム二ノチング化成箔(約45μF/cm″)を中
央で2つ折りにして長さ5IIIII+にした間に、長
さ8m幅3麟m、厚さO,1mmのアルミニウムエラチ
ンづ化成箔(約45μF/cm”)の長手方向の一方の
端部を奥までさし込み、両箔の中心線が一致するJうに
揃えたものを40個用意した。次に厚さ0゜51、幅2
0m5、長さ400t+eのステンレス製諭属板に、上
記40個の化成箔の挟持部の端部を(れぞれ2mmの間
隔をおいて他方の端部を揃え、スポット溶接で接続した
[Example 1] A double-notched aluminum foil (approximately 45μF/cm'') with a length of 101m, a width of 7III11, and a thickness of 0.1mm was folded in half at the center to make a length of 5III+, while a length of 8m and a width of 3 Insert one longitudinal end of a 1mm thick aluminum elatin chemical foil (approximately 45μF/cm") all the way to the end, and align the center lines of both foils to match. We prepared 40 pieces. Next, thickness 0゜51, width 2
The ends of the sandwiching portions of the 40 chemically formed foils were connected to a stainless steel metal plate measuring 0 m5 and 400 t+e in length (with the other end aligned at an interval of 2 mm) by spot welding.

上記化成箔の他方の端部から6mm部分をりん酎および
りん酸アンモニウム水溶液に浸漬し、再什成した。さら
に、酢酸鉛三水和物2.4モル/Qの水溶液と過硫酸ア
ンモニウム4モル/Qの水溶I<、  液との混合液に
化成箔の他方の端部より3mmの部分を浸漬して600
C,1時間反応させ、二酸化鉛25wt%、硫酸鉛75
wt%からなる半導体層を形成した。ついて上記溶液で
後化成した。
A 6 mm portion from the other end of the chemically formed foil was immersed in phosphorous liquor and an aqueous ammonium phosphate solution to refinish. Furthermore, a portion 3 mm from the other end of the chemically formed foil was immersed in a mixture of an aqueous solution of 2.4 mol/Q of lead acetate trihydrate and an aqueous solution of ammonium persulfate of 4 mol/Q.
C, react for 1 hour, lead dioxide 25wt%, lead sulfate 75%
A semiconductor layer consisting of wt% was formed. This was followed by post-chemical conversion using the above solution.

この半導体層形成および後化成操作を2回くり返した後
、カーボンペースト槽、銀ペースト槽に順次浸漬して、
半導体層上に導電体層を形成した。
After repeating this semiconductor layer formation and post-chemical forming operation twice, the semiconductor layer is sequentially immersed in a carbon paste tank and a silver paste tank.
A conductor layer was formed on the semiconductor layer.

鴎、  次いで他方の端部から5InLllの部分で切
断し、素子′  を作製した。この段階で全数の素子が
幅3mmの化成箔を基にした部分が残り、半導体層が形
成されていない部分との境界は鮮明であった。
Then, a portion of 5 InLll was cut from the other end to produce a device. At this stage, all the elements had a portion based on the chemically formed foil with a width of 3 mm, and the boundary with the portion on which the semiconductor layer was not formed was clear.

これら素子に、用意された幅3 mm、長さ5 mm。These elements were prepared with a width of 3 mm and a length of 5 mm.

゛  厚さ0.1amの2枚の鉄系の箔を、上記素子の
導°  電体層、および誘電体層のみ存在する部分にの
せ、前者は銀ペーストで、後者はスポット溶接で、電気
的、機械的に接続し、これを樹脂封口してコンゝ  デ
ンサを作製した。
゛ Two iron-based foils with a thickness of 0.1 am were placed on the parts of the above element where only the conductor layer and dielectric layer were present, and the former was applied with silver paste and the latter with spot welding. A capacitor was fabricated by mechanically connecting them and sealing them with resin.

これら40個のコンデンサの特性値を測定し、その平均
値とバラツキを第1表に示した。
The characteristic values of these 40 capacitors were measured, and their average values and variations are shown in Table 1.

第1表 但し*12〇七での値 H100にセ /l ***tOV  〃 〔発明の効果〕 以上説明したように、本発明に係る固体電解コンデンサ
の製造方法によれば、特に半導体層の形成の過程で別の
弁金属箔によって覆い挟持するように素子の弁金属箔が
保持されているので、容量が安定し、しかも作業性が良
好で、量産に適している。さらに作製したコンデンサは
優れた特性を有する等の長所を有する。
In Table 1, however, the value H100 at *1207 is set /l ***tOV [Effects of the Invention] As explained above, according to the method for manufacturing a solid electrolytic capacitor according to the present invention, especially the semiconductor layer Since the valve metal foil of the element is held so as to be covered and sandwiched by another valve metal foil during the formation process, the capacity is stable, workability is good, and it is suitable for mass production. Furthermore, the manufactured capacitor has advantages such as excellent characteristics.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図ないし第5図は、本発明の方法の一実施例を示す
もので、第1図は金属板に一部が保護用弁金属箔によっ
て挟持された弁金属箔を接続した状態を示す平面図、第
2図は第1図の■−■線矢視図、第3図は弁金属箔に半
導体層を設ける位置および切断位置を示す図、第4図は
第1図の■−■線矢視断面図、第5図は上記手順によっ
て製作した固体電解コンデンサ素子の斜視図である。 l・・・弁金属箔(保護用)、2・・・弁金属箔、3・
・・金属板、3a・・長手辺、4・・・誘電酸化皮膜層
(酸化皮膜)、訃・・一方の端部側の一部(基部ン、6
・・・線、7・・・半導体層、8・・導電体層、9・・
・線、10・・・固体電解コンデンサ素子(素子)。
Figures 1 to 5 show an embodiment of the method of the present invention, and Figure 1 shows a state in which a valve metal foil, a part of which is sandwiched between protective valve metal foils, is connected to a metal plate. A plan view, FIG. 2 is a view taken along the line ■-■ in FIG. 1, FIG. 3 is a diagram showing the position where the semiconductor layer is provided on the valve metal foil and the cutting position, and FIG. 4 is a view taken along the line ■-■ in FIG. A sectional view taken along the line, and FIG. 5 is a perspective view of a solid electrolytic capacitor element manufactured by the above procedure. l... Valve metal foil (for protection), 2... Valve metal foil, 3...
...Metal plate, 3a...Longer side, 4...Dielectric oxide film layer (oxide film), end...Part of one end side (base, 6
... line, 7 ... semiconductor layer, 8 ... conductor layer, 9 ...
- Line, 10...Solid electrolytic capacitor element (element).

Claims (2)

【特許請求の範囲】[Claims] (1)弁金属箔1によって、長手方向の一方の端部が挟
持された狭幅長方形の弁金属箔2の複数枚を、少なくと
も直線状の一辺を有する金属板3の上記一辺に対して直
角となるように、上記弁金属箔1によって挟持された一
方の端部を並列に接続し、これら弁金属箔1,2の表面
に誘電体酸化皮膜層を形成し、次いで、弁金属箔1,2
の一方の端部側を残して順次半導体層、導電体層を形成
した後、上記弁金属箔1,2の半導体層が形成されてい
ない部分で、弁金属箔1および2を切断分離する工程を
有することを特徴とする固体電解コンデンサの製造方法
(1) A plurality of narrow rectangular valve metal foils 2 with one longitudinal end held between the valve metal foils 1 are placed at right angles to the one side of the metal plate 3 having at least one linear side. One end sandwiched by the valve metal foils 1 is connected in parallel so that a dielectric oxide film layer is formed on the surfaces of these valve metal foils 1 and 2, and then the valve metal foils 1 and 2 are connected in parallel. 2
After sequentially forming a semiconductor layer and a conductor layer except for one end side, cutting and separating the valve metal foils 1 and 2 at the portions where the semiconductor layer is not formed. A method for manufacturing a solid electrolytic capacitor, comprising:
(2)弁金属箔1,2として、表面に誘電体酸化被膜層
が形成されている弁金属箔1,2を用い、これに弁金属
箔1,2の一方の端部側を残して順次半導体層、導電体
層を形成する請求項(1)記載の固体電解コンデンサの
製造方法。
(2) As the valve metal foils 1 and 2, use the valve metal foils 1 and 2 on which a dielectric oxide film layer is formed on the surface, and sequentially leave one end side of the valve metal foils 1 and 2 The method for manufacturing a solid electrolytic capacitor according to claim 1, wherein a semiconductor layer and a conductor layer are formed.
JP28159790A 1990-10-19 1990-10-19 Manufacture of solid electrolytic capacitor Pending JPH04155909A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28159790A JPH04155909A (en) 1990-10-19 1990-10-19 Manufacture of solid electrolytic capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28159790A JPH04155909A (en) 1990-10-19 1990-10-19 Manufacture of solid electrolytic capacitor

Publications (1)

Publication Number Publication Date
JPH04155909A true JPH04155909A (en) 1992-05-28

Family

ID=17641368

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28159790A Pending JPH04155909A (en) 1990-10-19 1990-10-19 Manufacture of solid electrolytic capacitor

Country Status (1)

Country Link
JP (1) JPH04155909A (en)

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