JPH04155690A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To complete refreshing in a short time and to accelerate accessing by forming a transistor of a transfer gate in a depletion type. CONSTITUTION:Transistors Q5, Q6 of a transfer gate 2 are formed in P-type channel depletion type. If a control signal PHITG becomes a power source voltage V level, Trs Q5, Q6 in which drains are connected to digit lines DL1, DL2, are turned OFF, and the lines DL1, DL2 are insulated from nodes N1, N2. Here, an activated signal PHISAP becomes the power source voltage, an activated signal PHISAN becomes a ground level, a sense amplifier 1 is activated, and a differential potential of the nodes N1, N2 is amplified. In this case, since the potential of the node N2 is raised, the TrQ6 conducts, and the level of the line DL2 is raised from before refreshing, the refreshing is completed in a short time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and more particularly to a MOS dynamic RAM type semiconductor memory device equipped with a sense amplifier that amplifies a signal between a pair of digit lines.

[Conventional technology]

In recent years, with the expansion of the field of use of this type of semiconductor memory device due to its low price, there has been a demand for faster access time and shorter cycle time. Conventional semiconductor memory devices that meet these demands include -
As an example, there is a circuit as shown in FIG.

This circuit consists of a pair of first and second digit lines DL.
I, DL2 and the first and second word lines WLI, WL2
and one of the source and drain is set to the first digit 1lD.
an N-channel enhancement type first transistor Q connected to L1 and having its gate connected to the first word line WLI;
7, and a first memory cell MCI having a capacitor C1 whose one end is connected to the other of the source and drain of this transistor Q7, and one of whose source and drain is connected to a second digit line DL2 and whose gate is connected to the second digit line DL2. Word 1lWL
2, and a second memory cell MC2 having a capacitor C2 whose one end is connected to the other of the source and drain of this transistor Q8, and whose gate and drain are cross-connected to each other. N-channel enhancement type third
and fourth transistors Ql, Q2, P-channel enhancement type transistor Q3 . Q4, and the drains of these transistors Q1 to Q4 are used as first and second input/output terminals Nl and N2, respectively, and an activation signal ΦSAP lΦ
When the SAN is at the activation level, the first and second input/output terminals N
A flip-flop type sense amplifier 1 that amplifies the signals of L and N2, and fifth and sixth N-channel enhancement type transistors Ql2゜Q13 that input a control signal Φ↑GX to their gates. digit 1 of
It includes a transfer gate 2A that controls the connection between DL1, DL2 and the first and second input/output terminals Nl, N2 of the sense amplifier 1, and N-channel enhancement type transistors Q9 to Qll. The configuration includes a precharge circuit 3 that performs precharge control on lines DLI and DL2.

Next, the operation of this circuit will be explained.

FIG. 4 is a waveform diagram of various signals for explaining the operation of this circuit.

First of all, in the inactive state, the precharge signal ΦP and the control signal ΦTGX are at the power supply voltage VCC level, and the input/output terminals N1 and N2 (hereinafter referred to as nodes Nl and N2) of the sense amplifier 1 and the digit lines DLI and DL
2 is a transistor Q5. Q6, and the transistor QIO
, Qll, the nodes Nl, N2 and the digit lines DLI, DL2 are both at the same potential as the signal HVC1 (usually V cc/ 2 ).

Also, the activation signal Φ5A2. ΦSAN is also the signal HVC1
is charged to the same potential as

Next, when activated, the precharge signal ΦP goes to the ground level, and the digit line DLI.

DL2 is isolated from signal HVC1.

Next, the level of the selected word line (WLI) (
When ΦWLI) becomes high level, digit line DLI and capacitor C1 are connected via transistor Q7, and the potential of digit@DLI changes depending on the potential of capacitor C1. At this time, since the digit line DLI and the node N1 are connected through the transistor Q12, the node N1 also has the same potential as the digit line DLL.

Next, when the control signal ΦDing GX goes to the ground level, the digit lines DLI and DL2 and the nodes Nl and N2 are insulated, and when the activation signal ΦSAP goes to the power supply voltage VCC level and the activation signal ΦSAN goes to the ground level, the node Nl , N2 is amplified by sense amplifier 1, and first node N
1 is at a lower potential than the node N2, the node N1 becomes the ground level and the node N2 becomes the power supply voltage VCC level. At this time, the potentials of the digit lines DLI and DL2 are at the node Nl,
It does not change because it is insulated from N2.

Next, when the control signal ΦTGX becomes high level, the node Nl
, N2 and digit lines DLI, DL2 are connected, digit line DLI is at ground level, and digit line DL2 is connected to ground level.
becomes the power supply voltage VCC level. At this time, capacitor C
1 is connected to digit line DL1, memory cell MCI is refreshed to the ground level, which is the same potential as digit line DLL.

Next, when the level of the word line WLI (ΦWLI) becomes the ground level and the precharge signal Φ2 goes to the power supply voltage VCC level, the capacitor C1 is insulated and holds that potential, and the digit lines DLL and DL2 have the same potential as the signal HVC1. becomes. Note that the signal HVC2 is at the same potential as the signal HVC1.

In this circuit, sense amplifier 1 is connected to nodes N1, N2
When amplifying the potential difference between the nodes Nl and N2 and the digits MDL1. Since the sense amplifier 1 is insulated from the DL2, the capacitive load on the sense amplifier 1 is reduced, and high-speed amplification operation is possible.

[Problem to be solved by the invention]

The conventional semiconductor memory device described above has a digit line DLI.
, DL2 are disconnected from the nodes Nl, N2, the sense amplifier 1 is activated to rapidly amplify the potential difference between the nodes Nl, N2, and then the control signal ΦTGX is set to high level to connect the digit lines DLI, DL2 and the nodes N1 . Since the configuration is such that the memory cell MC1 is refreshed by connecting the digit line DLI to the digit line DLI when the control signal ΦTGX rises.

Both DL2 levels are precharge level (Vcc/2
), which must be set to the power supply voltage VCC level and ground level, which takes time and has the disadvantage that access time cannot be shortened.

An object of the present invention is to provide a semiconductor memory device that can speed up access.

[Means to solve the problem]

In the semiconductor memory device of the present invention, a pair of first and second digit lines, first and second word lines, and one of a source and a drain are connected to the first digit line, and a gate is connected to the first digit line. A first memory cell includes a first enhancement-type transistor connected to a word line No. 1, a first capacitor whose one end is connected to the other of the source and drain of the first transistor, and one of which is connected to the second digit line, and the gate is connected to the second digit line.
a second memory cell having an enhancement-type second transistor connected to the word line of the second transistor, and a second capacitor having one end connected to the other of the source and drain of the second transistor; The third and fourth enhancement type transistors are cross-connected, and the drains of the third and fourth transistors are used as first and second input/output terminals, respectively, and when the activation signal is at the activation level, the first and fourth transistors are connected to each other. a flip-flop type sense amplifier that amplifies the signal at the second input/output terminal; and depletion type fifth and sixth transistors that input a control signal to the gates of the first and second digit lines and the sense amplifier; and a transfer gate that controls open connection with the first and second input/output terminals of the amplifier.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

This embodiment differs from the conventional semiconductor memory device shown in FIG. 3 in that the fifth and sixth transistors Q5. Q6 is of the P-channel depression type, and the level relationship of the control signal ΦTG is reversed.

Next, the operation of this embodiment will be explained.

FIG. 2 is a waveform diagram of various signals for explaining the operation of this embodiment.

First of all, in the inactive state, the control signal ΦT
This is the same as the conventional example except that G is the ground level.

Next, when the precharge signal ΦP reaches the ground level and becomes activated, the level of the selected word line WL1 (Φ
IILI) becomes high level, and the level of digit line DLI changes depending on the memory cell MCI.

Next, when the control signal ΦTG reaches the power supply voltage Vcc level, each drain is connected to the digit 1DL1. P-channel depletion type transistors Q5 and C6, which are connected to DL2 and whose sources are connected to nodes Nl and N2, are turned off because their gates are at the power supply voltage VCC level and their source and drain potentials are approximately Vcc/2. Digit lines DLL and DL2 and nodes Nl and N2 are insulated.

Here, the activation signal ΦSAP becomes the power supply voltage vc0, the activation signal ΦSAN becomes the ground level, the sense amplifier 1 is activated, and the difference potential between the nodes Nl and N2 is amplified.

At this time, if node N2 has a higher potential than node N1, the potential of node N2 increases and that potential becomes power supply voltage V. When the potential becomes higher than 0 minus the threshold voltage of transistor Q6, transistor Q6 becomes conductive.
Unlike the conventional example, the level of digit line DL2 starts rising before entering the refresh period.

Next, when the refresh period begins and the control signal ΦG reaches the ground level, the nodes Nl and N2 and the digit line DLI,
It is connected to DL2 and has the same potential, but the digit line DL
2 has already started to rise in level, the charging and discharging current required during the refresh period is very small compared to the conventional example, and the refresh can be completed in a short time. Therefore, access speed can be increased.

C Effects of the Invention As explained above, in the present invention, by making the transfer gate transistor a depletion type, charging (or discharging) of the digit line is started before entering the refresh period. This has the effect of shortening the time it takes for the level of the digit line to become static after the digit line has changed, that is, the time it takes for refresh to be completed, thereby speeding up access.

[Brief explanation of the drawing]

1 and 2 are circuit diagrams showing an embodiment of the present invention and waveform diagrams of signals of various parts to explain the operation of this embodiment, and FIGS. 3 and 4 are diagrams of a conventional semiconductor memory device, respectively. FIG. 2 is a circuit diagram showing an example, and a waveform diagram of signals of various parts for explaining the operation of this semiconductor memory device. 1...Sense amplifier, 2,2A...Transfer gate, 3...Precharge circuit, C1, C2...Capacitor, DLL, DL2...Digital line, MC1
, MC2...memory cell, Q1-Q13...transistor, WLI, WL2...word line.

Claims (1)

[Scope of Claims] 1. A pair of first and second digit lines, a first and second word line, and one of the source and drain is connected to the first
digit line and a gate connected to the first word line; and a first capacitor having one end connected to the other of the source and drain of the first transistor. a second enhancement type transistor having one of its source and drain connected to the second digit line and its gate connected to the second word line; and one end connected to the source of the second transistor. , a second memory cell having a second capacitor connected to the other of the drains, and third and fourth enhancement type transistors having their gates and drains cross-connected to each other. A flip-flop type sense amplifier whose drains serve as first and second input/output terminals, respectively, and which amplifies signals at the first and second input/output terminals when an activation signal is at an activation level; and a gate having a control signal. a transfer gate comprising fifth and sixth input transistors of depletion type and controlling connections between the first and second digit lines and the first and second input/output terminals of the sense amplifier; A semiconductor memory device characterized by: 2. The semiconductor memory device according to claim 1, wherein the first and second transistors are each of N-channel type, the third and fourth transistors are each of N-channel type, and the fifth and sixth transistors are each of P-channel type. .