JPH04154392A - Video tape recorder - Google Patents

Abstract

PURPOSE:To suppress the deterioration of a reproducing image such as color slippage on a screen by always detecting phase difference between a reproduced C signal and a Y signal, and adjusting the phase of the Y signal so that the phase difference can go to zero. CONSTITUTION:The DC output voltage of a low-pass filter 14 in a Y-C phase difference detection circuit(YC) 7 goes to 1/2 the source voltage when an ideal timing of the reproducing C signal for the Y signal can be obtained and no phase difference exists. Also, when the phase of the reproducing C signal leads that of the Y signal i.e., the former is located before the latter ideally, a lower voltage is outputted, and when the former lags the latter, a higher voltage is outputted. The phase difference between the Y signal and the C signal generated in reproduction can be compensated by selecting the delay characteristic of a variable delay line 6 so that delay time can be extended when an applied DC voltage is high, and also, a ratio of the applied voltage to the change of delay can be set at an inverse to the detection characteristic of the circuit 7.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a video tape recorder.

[Conventional technology]

2. Description of the Related Art Conventionally, video tape recorders (hereinafter abbreviated as VTR) have various formats including those for broadcasting and for consumer use. Among these, video cameras such as VH5, Beta, and 8mm, which are widely used all over the world for consumer use,
All tape recorders separate the luminance signal (hereinafter abbreviated as Y signal) and chroma signal (hereinafter abbreviated as C signal) in the video signal, the Y signal is FM modulated, and the C signal is a low frequency signal. A so-called color-under one method is used in which the data is converted and recorded on tape.

In a VTR that separately processes these Y and C signals, the Y and C signals are processed in completely separate signal processing circuits and recorded on the same tape. Further, during reproduction, the Y signal and C signal taken out from the tape are output after being processed in an independent signal processing circuit.

[Problem to be solved by the invention]

In the conventional video tape recorder mentioned above, Y
Since the signal and C signal pass through independent signal processing circuits,
A phase difference occurs between the Y signal and the C signal, and a timing shift between the two signals is likely to occur.

This phase difference is managed by optimizing the group delay characteristics of the filter in the signal processing circuit. However, in reality, this management differs for each set and manufacturer, and although the phase difference is optimized for recording and playback of the same set, it is not possible for compatible playback with other sets. , in reality, phase differences often occur. This phase difference between the Y signal and the C signal appears as color blurring on the playback screen, and has the disadvantage that it is a factor in deteriorating the playback image quality of the VTR.

[Means to solve the problem]

In the VTR of the present invention, the luminance signal is detected via a phase difference detection signal outputted from the C phase difference detection means before the YC phase difference detection means for detecting the phase difference between the luminance signal and the chroma signal included in the reproduced video signal. and a phase compensation means for compensating the phase of the signal and the chroma signal so that they are in the same phase.

〔Example〕

Next, the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of the present invention. As shown in FIG. 1, this embodiment has an image head l;
A regenerative amplifier 2, a filter 3, a Y signal processing circuit 4,
It is configured to include a C signal processing circuit 5, a variable delay line 6, and a YC phase difference detection circuit 7. FIG. 2 is an internal block diagram showing an embodiment of the YC phase difference detection circuit 7, and the YC phase difference detection circuit 7 includes a synchronous separation section 8, a reference pulse generation circuit 9, and a blanking circuit. - Consisting of a pulse generation circuit 10, a rectifier circuit 11, a waveform shaping circuit I2, an output gate 13, and a low-pass filter 14.

In FIG. 1, a reproduced video signal reproduced by a video heater 1 is amplified by a reproduction amplifier 2, and separated into a Y signal and a C signal by a filter 3. These separated signals are input to a Y signal processing circuit 4 and a C signal processing circuit 5, respectively, where they are processed and output as a baseband Y signal and a subcarrier-modulated C signal.

Generally, the C signal is delayed compared to the Y signal, so the Y
A delay line is used for signal output. Here, the delay line is represented as a variable delay line 6. In the YCC phase difference detection circuit 7, the phase difference between the Y signal and the C signal is converted into a DC voltage, and this I output is sent to the variable delay line 6.

The variable delay line 6 is configured so that the amount of delay changes according to the applied DC voltage, and provides a delay amount to the Y signal so as to compensate for the phase difference between both the Y and C signals. It operates to remove phase differences in signals.

FIG. 2 is an internal block diagram showing one embodiment of the YC phase difference detection circuit 7. As shown in FIG. The Y signal 101 is input to the synchronization separator 8 and only the synchronization signal of the Y signal 101 is extracted, and this synchronization signal 102 is input to the reference pulse generation circuit 9 and the blanking pulse generation circuit 10. The reference pulse generation circuit 9 consists of a pulse delay circuit with a fixed delay amount, and the rising edge of the reference pulse 103 that is the output thereof is set to be placed at the center of the ideal burst signal position of the NTSC signal. has been done. Further, the falling edge is set slightly wider so that it falls within the effective screen period of the reproduced Y signal.

On the other hand, the C signal 104 is rectified in the rectifier circuit 11, and its rectified output 105 is input to the waveform shaping circuit 12. The waveform shaping circuit 12 receives a blanking pulse 106 sent from the blanking pulse generating circuit 10.
are input at the same time. This blanking - pulse 1
06 is a pulse generated by delaying the synchronization signal 102 inputted from the synchronization separation unit 8, and is the old pulse in the horizontal blanking portion of the reproduced Y signal. The waveform shaping circuit 12 operates only during the period in which this blanking pulse 106 is old, and converts the signal within this period into a pulse. C signal 1 within the blanking period
The component of 04 is only the burst signal, and as a result, the output of the waveform shaping circuit 12 becomes a pulse having the same width and occurring at the same position as the burst signal.

Hereinafter, this pulse will be referred to as a burst pulse 107.

This burst pulse 107 and reference pulse 103 are
Both are input to the output game (output game) 13. What is shown in FIG. 3 is a circuit diagram showing an example of the output gate 13. As shown in FIG. 3, the output gate 13 is connected to an inverter 15,
It is composed of a NAND circuit 16, a NOR circuit 17, a PMO3) transistor and an NMO8) transistor 18, and when the burst pulse is Lo, the output is always high impedance. Further, when the burst pulse is Hi and the reference pulse is old, the output becomes Hi, and similarly, when the reference pulse is Lo, the Lo pulse is output. When the burst signal in the reproduced C signal 104 is at an ideal position, the rise of the reference pulse 103 will be located at the center of the burst signal in the C signal 104, and the creation force and Lo ratio output width will be equal.

Figure 4 (a), (b), (c), (d), (e
), (f), (g), (h) and (i) show timing charts of each signal corresponding to the operation of the above-mentioned YC phase difference detection circuit 7, and FIG. 4(a) teeth,
It represents a waveform diagram of an ideal NTSC signal.

The signal 10g output from the output gate 13 is input to the low-pass filter 14, where the alternating current component is removed and a direct current voltage is output.

As is clear from the above explanation, when the timing of the reproduced C signal with respect to the Y signal is ideal and there is no phase difference, the DC output voltage of the low-pass filter 14 is 1
It becomes 1/2 degree. Also, if the reproduced C signal is ahead in phase compared to the Y signal, that is, if it is ideally in front of the position, a lower voltage will be output, and if it is behind, a higher voltage will be output. is output.

As a result, the YC phase difference detection circuit 7 detects that (the phase difference is O
A linear DC output voltage is output based on the phase difference, with the output voltage at the time of ) = (1/2 voltage of the power supply voltage) as the center.

Considering the above, the delay characteristics of the variable delay line 6 are set so that the delay time becomes longer when the applied DC voltage is high, and the ratio of the applied voltage to the delay amount change (sec /V) to be the reciprocal of the detection characteristic (V/5ec) of the YC phase difference detection circuit 7, a feedback loop is established to compensate for the phase difference between YC signals that occurs during reproduction. Can be configured.

FIG. 5 is a diagram showing a second embodiment of the present invention. As shown in FIG. 5, this embodiment includes a video heater 1, a regenerative amplifier 2, a filter 3, a Y signal processing circuit 4, a C signal processing circuit 5, a variable delay line 6, and a YC signal processing circuit 4. It is configured to include a phase difference detection circuit 7 and a fixed delay line 20.

As is clear from FIG. 5, the differences between this embodiment and the first embodiment are the Y signal processing circuit 4 and the YC phase difference detection circuit 7.
A fixed delay line 20 is inserted between the two, and the phase difference detection in the YC phase difference detection circuit 7 targets the phase of the previous stage of the variable delay line 6.

In FIG. 5, the reproduced Y signal output from the Y signal processing circuit 4 is input to the YC phase difference detection circuit 7 via a fixed delay line 20 having a standard delay amount. The characteristics of the YC phase difference detection circuit 7 are the same as those of the first embodiment described above, and the DC output voltage of the YC phase difference detection circuit 7 is input to the variable delay line 6 to control the amount of delay. do. Therefore,
The reproduced Y signal output from the Y signal processing circuit 4 and input to the variable delay line 6 is delayed in phase by the variable delay line 6 and output.

In this second embodiment, the delay amount correction is a feedford, and the DC output voltage of the YC phase difference detection circuit 7 is 1/2 of the power supply voltage, that is, the Y signal and the C signal which have undergone a fixed delay amount. The delay amount of the variable delay line 6 when the phase difference of

〔Effect of the invention〕

As explained above, the present invention constantly detects the phase difference between the reproduced Y signal and C signal, and controls and adjusts the phase of the Y signal so that this phase difference becomes zero. Even if there is a phase difference between the Y and C signals on the tape pattern due to a defect, these phase differences are automatically corrected and both the Y and C signals are always output at the ideal timing. This has the effect of suppressing deterioration of reproduced images such as color shift on the screen.

[Brief explanation of the drawing]

1 and 5 are block diagrams of the first and second embodiments of the present invention, respectively, FIG. 2 is a block diagram of a YC phase detection circuit, FIG. 3 is a circuit diagram of an output gate, and FIG. 4 is a block diagram of a YC phase detection circuit. (a
), (b), (c), (d), (e), (f)
,(g). (h) and (i) are timing charts of each signal in the YC phase difference detection circuit. In the figure, 1... image head, 2...
・Regenerative amplifier, 3・−・−・・filter, 4・・・・・
・Y signal processing circuit, 5...C signal processing circuit, 6
...--Variable delay line, 7...3.・YC phase difference detection circuit, 8... Synchronization separation circuit, 9... Reference pulse generation circuit, 10... Blanking pulse generation circuit, 11-...・Rectifier circuit, 12...
...Waveform shaping circuit, 13-...Output gate, 1
4...--low-pass filter, 15...--inverter, 16...--NAND circuit, 17...--
・NOR circuit, 18... PMO3) - transistor, 19... NMO3) - transistor, 20...
...Fixed delay line.

Claims (1)

[Claims] 1. YC phase difference detection means for detecting a phase difference between a luminance signal and a chroma signal included in a reproduced video signal; and a phase difference detection signal outputted from the YC phase difference detection means. , a phase compensation means for compensating the phases so that the luminance signal and the chroma signal are in the same phase. A video tape recorder comprising: 2. The phase compensation means includes variable delay means that is controlled by the phase difference detection signal and acts to delay the phase of the luminance signal, and the YC phase difference detection means is controlled by the phase difference detection signal. 2. The video tape recorder according to claim 1, wherein the video tape recorder is configured to detect a phase difference between the luminance signal and the chroma signal. 3. The phase compensation means includes a variable delay means that is controlled by the phase difference detection signal and acts to delay the phase of the brightness signal, and a variable delay means that acts to delay the phase of the brightness signal by a predetermined phase amount. fixed delay means, YC
2. The video tape recorder according to claim 1, wherein the phase difference detection means is configured to detect a phase difference between the luminance signal output from the fixed delay means and the chroma signal.