JPH04151866A - Manufacture of semiconductor storage device - Google Patents

Abstract

PURPOSE:To manufacture a semiconductor storage device of large operation margine, by forming a cavity on a storage node of a capacitor element, by a side wall spacer on a step-difference part formed by the gate electrode of a transistor. CONSTITUTION:Laminated conductive films 23, 25 across a step-difference part formed by the gate electrode 15 of a transistor, and a side wall spacer 24 sandwiched by the conductive films 23, 25 on the step-difference part is formed. The conductive films 23, 25 are worked into a pattern of a storage node 27 of a capacitance element. The side wall spacer 24 exposed by the above working is eliminated. As the result, a cavity 26 is formed between the conductive films 23, 25. Also on the inner surface of the cavity, a dielectric film is formed, so that the surface areas of the conductive films 23, 25 being a storage node 27 are large and cell capacitance is large, although the step-difference of the gate electrode is small. Thereby a semiconductor storage device of large operation margine can be manufactured while the increase of process is restrained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory in which a memory cell is composed of a transistor and a capacitive element, particularly a stacked capacitive DRAM.
The present invention relates to a method of manufacturing a semiconductor memory called ``.

[Summary of the invention]

The present invention provides a semiconductor memory manufacturing method as described above, in which a cavity is formed in a storage node of a capacitive element using a sidewall spacer in a stepped portion formed by a gate electrode of a transistor. This makes it possible to manufacture semiconductor memories.

[Conventional technology]

Conventionally, in order to ensure a predetermined cell capacitance and an operating margin even when the stacked capacitor DRAM is miniaturized, the step difference between the gate electrodes of the transistors has been increased.

That is, when the step difference caused by the gate electrode of the transistor is increased, the surface area of the storage node that extends from above the source/drain region of the transistor to above the gate electrode becomes large, thereby increasing the cell capacitance.

[Problem to be solved by the invention]

However, in large-scale memories, in order to reduce pattern steps, it is becoming necessary to reduce the size in the vertical direction along with the reduction in the horizontal direction.

For this reason, the conventional technique of increasing the surface area of a storage node by increasing the step difference caused by the gate electrode of a transistor is no longer applicable.

[Failure to solve the problem]

In the method for manufacturing a semiconductor memory according to the present invention, a plurality of conductive films 23.25 are stacked on each other across a step portion formed by a gate electrode I5 of a transistor, and a plurality of conductive films 23.25 are sandwiched between the plurality of conductive films 23.25 at the step portion. forming sidewall spacers 24 that are exposed by this process, processing each layer of the plurality of conductive films 23 and 25 into a pattern of a storage node 27 of a capacitive element;
4 is sequentially repeated to form a dielectric film on the surfaces of the plurality of conductive films 23 and 25 subjected to the processing.

[Effect]

In the method for manufacturing a semiconductor memory according to the present invention, by removing the sidewall spacer 24 sandwiched between the plurality of conductive films 23, 25, a cavity 26 is formed between the plurality of conductive films 23, 25, and a conductive film 23, 25 is formed. A dielectric film is also formed on the inner surface of the cavity 26 of the film 23.25.

Therefore, even if the step caused by the gate electrode 15 is small, the surface area of the conductive film 23.25, which is the storage node 27, is large.
Large cell capacity.

Moreover, the stacking of a plurality of conductive films 23, 25, the formation of sidewall spacers 24, the processing of these conductive films 23, 25, and the removal of sidewall spacers 24 only need to be repeated in sequence.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

In this embodiment, as shown in FIG. 1A, a SiO□ film 12 (FIG. 2) for element isolation is formed on the surface of the S+ substrate 11 by LOCO.
A gate oxide film of SiO□ is formed on the surface of the element formation region 13 surrounded by this SiO□ film 12.
Membrane 14 membrane type 4.

Then, a polycide film 15 and a SiO□ film 16 are sequentially deposited on the SiO□ film 12.14, and these StO□
The film 16 and the polycide film 15 are processed into a pattern of a gate electrode of a transistor.

Thereafter, n-type impurities are ion-implanted into the Si substrate 11 at a low concentration using the polycide film 15 and the SiO□ film 12.16 as masks, thereby n-
A diffusion layer 17 is formed.

Then, a 5iOz film 21 is deposited on the entire surface by CVD, and the SiO□ film 21 is etched back by RIE. As a result, sidewall spacers are formed on the sides of the polycide film 15 and the 5i02 film 16, one pair of the SiO□ film 21. In addition, during RIE of 21 SiO□ films,
The 5in2 film 14 is also etched at the same time.

Next, the polycide film 15 and the SiO□ film 12.16.2
1 as a mask, n-type impurities are ion-implanted into the Si base vi and Il at a high concentration.
3, an n diffusion layer 22 is formed.

This n-diffusion layer 22 and the previously mentioned n-diffusion layer 17 become the source/drain regions of the transistor, and these diffusion layers 22.17 and the polycide film 15, which is the gate electrode, form an L
A transistor with a D D structure is completed.

Thereafter, a polycrystalline Si film 23 doped with n-type impurities, ie, a DOPO3 film, is deposited over the entire surface. This deposition brings the n' diffusion layer 22 and the polycrystalline Si film 23 into contact.

Next, as shown in FIG. 1B, a SiO□ film 24 is deposited on the entire surface by CVD, and the Sho□ film 24 is etched back by RIE. As a result, the polycrystalline S in the six step portions on the polycide film 15 and the SiO2 film 16 is
A side wall spacer having a SiO□ film 24 and a film strip 4 is formed on the side of the i film 23.

Then, a polycrystalline Si film 25 doped with n-type impurities, that is, a DOPO3 film, is deposited again on the entire surface.

Through this deposition, the polycrystalline Si film 25 is laminated on the polycrystalline Si film 23, and the SiO□ film 24
Sandwiched between membranes 23.25.

After that, a resist film (not shown) is formed on the polycrystalline Si film 25.
This resist film is processed into a pattern of storage nodes.

Next, as shown in FIG. 1C, RIB is performed on the polycrystalline Si film 25 using the above-mentioned resist film as a mask. As a result, the polycrystalline Si film 25 is patterned so as to straddle the six step portions on the polycide film 15 and the SiO□ film 16.

When polycrystalline 5ill125 is buttered, it becomes 5in2
This time, the exposed 5iO7 is removed until the membrane 24 is exposed.
Film 24 is removed by wet etching.

By this wet etching, the S of the portion located below the polycrystalline Si film 25 remaining after patterning is removed.
The iO□ film 24 film strip 4 is formed.

As a result, a tunnel-shaped cavity 26 that crosses the storage node pattern is formed between the polycrystalline Si film 25 of the storage node pattern and the polycrystalline Si film 23 remaining on the entire surface.

Then, using the above resist film as a mask, polycrystalline Si
RIE is further performed on the film 23 to form a polycrystalline Si film 23.
．． A storage node 27 consisting of 25 is completed.

Thereafter, a dielectric film (
A capacitive element is completed by forming a plate electrode (not shown) on this dielectric film (not shown) and then forming a plate electrode (not shown) on this dielectric film.

At this time, since a cavity 26 is formed between the polycrystalline Si films 23 and 25, a dielectric film is also formed on the inner surface of this cavity 26, and further, in this state, the cavity 26 is filled with a plate electrode.

Therefore, electricity can be stored on the inner surface of the cavity 26, and the surface area of the storage node 27 is large, so that a large cell capacity can be obtained in this embodiment.

Note that in this embodiment, the storage node 27 is constituted by the two-layer polycrystalline Si film 23.25, and the polycrystalline Si film 23.2
Although the cavity 26 is formed only between the polycrystalline Si film 5 and the
Multiple cavities can also be formed between the membranes.

Moreover, no matter how many layers of cavities are formed, the cavities 2
It is only necessary to repeat a process similar to that already described for forming 6.

〔Effect of the invention〕

In the method for manufacturing a semiconductor memory according to the present invention, the cell capacity can be increased simply by repeating similar processes one after another, so it is possible to manufacture a semiconductor memory with a large operating margin while suppressing an increase in the number of processes.

[Brief explanation of the drawing]

FIG. 1 sequentially shows an embodiment of the present invention, and is a side sectional view taken along line II in FIG. 2, and FIG. 2 is a plan view of a memory cell in the middle of the embodiment. In addition, in the symbols used in the drawings, 15. 24--------------5rOz film 2
5-------------Polycrystalline Si film 26
----------- One cavity 27--------------- Storage node.

Claims (1)

[Scope of Claims] A method for manufacturing a semiconductor memory in which a memory cell is constituted by a transistor and a capacitor, comprising: a plurality of conductive films stacked on each other and spanning a step formed by a gate electrode of the transistor; forming a sidewall spacer sandwiched between the plurality of conductive films in the section, processing each layer of the plurality of conductive films into a pattern of a storage node of the capacitor, and forming the sidewall spacer exposed by this processing. A method of manufacturing a semiconductor memory, wherein a dielectric film is formed on the surface of the plurality of processed conductive films by sequentially repeating the steps of removing and removing the plurality of conductive films.