JPH04150485A - Reproducing device - Google Patents

Abstract

PURPOSE:To obtain an electronic still camera with PAL-NTSC mutual conversion of a simple constitution using no frame memory by interpolating scanning lines without frame memory, but by converting a sampling clock. CONSTITUTION:Compressed picture data read out from a memory card 19 are temporarily held in a buffer memory 1 through a card connector 20. The compressed picture data from the memory 1 are entropy-decoded by means of a Huffman decoder 2 and reproduced to picture data (8X8) of blocks through a series of adaptive discrete cosine transformation(ADCT) by means of a quantizing section 3 and reverse DCT 4. Thinning of scanning lines is performed in the stage in which picture data are reproduced in blocks, but the thinning is performed in such a way that the 576-effective scanning lines of a PAL are reduced to the 480-effective scanning lines of an NTSC, namely, 6-scanning lines are thinned to 5-scanning lines.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a playback device used in an electronic still camera or the like.

(Prior Art) Conventionally, there has been a broadcasting system conversion device for professional use that uses a frame memory,
vision system communication) and PAL (Phase Alternation by
There is a system that performs conversion between different broadcasting systems (Line). For example, rNTSC-4PAL new power conversion device.
(Broadcasting Technology, 1986, October issue, 126 pages to 131 pages)
has announced a system that uses frame memory to perform motion compensation and converts the number of scanning lines from 5 to 6 for moving images.

(Problem to be Solved by the Invention) However, the conventional broadcast format conversion device described above uses a frame memory, and because the frame memory is expensive, it has not been widely used in consumer products such as electronic still cameras. there were.

The present invention solves the above-mentioned conventional problems, and aims to provide a playback device that is inexpensive and capable of format conversion, which can be applied to consumer use and uses real-time processing (changes sampling) without using a frame memory. That is.

(Means for Solving the Problems) In order to achieve the above object, the present invention provides a method for converting scanning lines in one screen from m to n in a playback device having an image expansion process. The clock for this process is m/n times the recording clock, and writing from the block to the two 8-line memories for line conversion is done using the same clock as the expansion process m/n times the recording clock. The reading clock is the same as the recording clock, thereby converting the sampling and converting the scanning line.

(Function) Therefore, according to the present invention, since scanning line interpolation is performed by converting the sampling clock without using a frame memory, it is possible to obtain a playback device with a simple format conversion that does not require a frame memory.

(Embodiment) FIG. 1 shows a block diagram of a system conversion/capacity reproduction system according to an embodiment of the present invention. In Figure 1, 1 is a buffer memory to cover the difference in access time between the memory card and the data rate during recording and playback;
2 is a Huffman decoder, 3 is a quantization unit, 4 is an inverse discrete cosine transform (hereinafter referred to as inverse DCT), 5 is a line memory,
6 is a scanning line thinning unit that thins out the number of effective scanning lines from 6 to 5, 7.10 is a switching circuit, and 8 and 9 are line memories (
8H line), 11 is a D/A converter that converts a digital signal into an analog signal, 12 is an adder circuit, 13 is an output terminal, 14 is a synchronization signal generation circuit, 15 is a clock generation circuit (A) from 18.0M, 16 is a 13.5 MHz clock generation circuit (B), and 17 is a control circuit (CPU) that controls the entire playback system of the format conversion device.

Next, the operation shown in FIG. 1 will be explained. memory card 19
The compressed image data read from the card connector 2
0 and is temporarily held in buffer memory l. Compressed image data from buffer memory 1 is sent to Huffman decoder 2
The image data is entropy decoded by the quantizer 3 and restored to image data (8×8) in block units through a demodulation process of a series of adaptive discrete cosine transforms (ADCT) including inverse DCT.

Scanning lines are thinned out at the stage when the image data is restored in blocks, but the effective number of scanning lines for PAL is 576 to N.
The number of effective scanning lines of the TSC is reduced to 480, that is, the number is thinned out from six to five.

FIG. 2 shows this thinning process, in which 20 lines, 6+7+7, are created from a total of 24 lines in three blocks of 1 to m in the vertical direction.

At this time, the calculation formula for scanning line interpolation is (knee 2)
-4)X-+(I-5)X, = I-4'(I-6
)=I-5' (I-7)X-+(I-8)X, = I-6' is used to perform line-to-line interpolation. Therefore, the blocks after the scanning line change have a scanning line configuration of 6 blocks for the ■ block, 7 blocks for the ■ block, and 7 blocks for the ■ block. (2) To create -1', t-S and ll-1 are required, and a line memory 5 is required to store one line in which the eighth line is stored.

FIG. 3 shows the above situation. The first line 1' of the output block (2) from the inverse DTC 4 is first operated on the 8th line (I-8) of the I block in the line memory to create line 1'(II-1') of the block (2). [Below] Repeat the calculation within the block, and at the same time as the 8th line of ■ is calculated, 8 pixels of the line memory are rewritten.■
Waits for the block's calculation.

FIG. 4(a) shows an example of the circuit configuration of the scanning line thinning circuit 6. In FIG. 4, blocks given the same numbers as in FIG. 1 are the same as in FIG. 1, so their description will be omitted. 32 is a timing controller, 33 is a switching circuit, 34.36
is a multiplier, 35 is a delay line (DL) with a one-pixel delay, 37 is an adder, 38 is a coefficient generator, 39 is a switching circuit, 40 is a clock generation circuit (A), and 41 is a clock generation circuit (B)
It is. FIG. 4(b) shows the output of the inverse DCT4.

Next, the operation of the scanning line thinning section 6 will be explained.

The output of the inverse DTC 4 is sequentially output pixel by pixel in the vertical direction as shown in FIG. 4(b).

The pixels on the 8th line are rewritten in the line memory 5. First, the pixels on the 8th line in the vertical direction are switched and outputted by the switching circuit 33, and then the output of the inverse DCT 4 is outputted from the switching circuit 33. In the adder 37, the delay line (DL) 3
The timing controller performs the above operation by adding the result of multiplying the current pixel by the output coefficient of the coefficient generator 38 and each pixel by the multiplier 34 and 36 to convert the scanning line from 6 to 5. 32 controls the rewriting of the line memory 5, the control of the switching circuit 33, and the coefficient generator 38.

The output of adder 37 enters a block-to-line converter. Data is written to and read out from the memory using the switching circuits 7 and 10 and the line memories 8 and 9 on a line-by-line basis. Here, the write and read clocks are a clock generation circuit (A) 40 and a clock generation circuit (B) 4.
1 is used. Clock during compression (recording) is 13.5M
Hz, there are 6 lines in line memory 8 or 9, like 1 block in Figure 2, and a block of 8 lines must be processed while reading 6 lines, so in the case of NTSC, 6 lines are processed. time of 6 x63,
It is necessary to perform line interpolation calculations using the write clock for 8 lines and write them into the line memory 8 or 9 during 555 μ5=381 μs. In other words, the clock generation circuit (A) is 18MHz, and the clock generation circuit (B) is 18MHz.
The conversion can be achieved by adopting 13.5MH2.

In FIG. 1, the clock generation circuit (A) 15 is 18M
Hz, the clock generation circuit (B) 16 generates a 13.5MH2 clock, and the clocks of the quantization unit 3 and inverse DCT 4 operate at 18MH2. This clock generation circuit (A)15. (B) 16 is controlled by the CPU 17, and a synchronization signal is output from the synchronization signal generation circuit 14 according to the timing output from the clock generation circuit (B) 16, and a luminance signal is output from the D/A converter 11. and are added by the adder circuit 12 and output from the output terminal 13.

(Effects of the Invention) As is clear from the above embodiments, the present invention performs scanning line interpolation by converting the sampling clock without using a frame memory, so the present invention is a PAL with a simple configuration that does not use a frame memory. This has the effect that an electronic still camera with NTSC mutual conversion can be achieved in real time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a format conversion device reproduction system in an embodiment of the present invention, FIG. 2 is an explanatory diagram of thinning in an embodiment of the present invention, and FIG. 3 is an illustration of interpolation in an embodiment of the present invention. An explanatory diagram of the situation, FIG. 4 is a circuit configuration diagram of a scanning line thinning section in an embodiment of the present invention. 1... Buffer memory, 2... Huffman decoder, 3... Quantization section, 4... Inverse DCT, 5.8.
9... line memory, 6... scanning line thinning section,
7, 10.33.39...switching circuit, 11...D
/A converter, 12... Addition circuit, 13... Output terminal, 14... Synchronization signal generation circuit, 15, 40.
...Clock generation circuit (A), 16.41...Clock generation circuit (B), 17...CPU, 19...
Memory card, 20...Card connector, 32.
...Timing controller, 34, 36... Multiplier, 35... Delay line, 38... Coefficient generator.

Claims (2)

[Claims] (1) In a playback device that has an image expansion process,
In order to convert the scanning lines in one screen from m to n, the decompression process clock is m/n times the recording clock, and the clock for the conversion from block to line is 2.
m of the clock when recording the 8-line memory write of the book
1. A reproducing device characterized in that the process of expansion by /n times is performed using the same clock, and the reading clock is performed using the same clock as that used during recording, thereby converting sampling and converting scanning lines. (2) In a playback device that has an image expansion process,
A buffer memory that temporarily holds compressed image data, a Huffman decoder, a quantization unit, an inverse DCT, a line memory, a scanning line thinning unit that thins out scanning lines at a ratio of 6 to 5, and blocks. The device is characterized by comprising a converter to a line, a D/A converter, a synchronization signal generation circuit, and an addition circuit that adds a luminance signal output from the D/A converter and an output from the synchronization signal generation circuit. The reproduction device according to claim (1).