JPH04149889A - Dual port memory - Google Patents

Abstract

PURPOSE:To increase a processing speed by outputting N latched distribution bit data in accordance with N status switching states of a selection signal and switching the selection signal within one period of a serial clock. CONSTITUTION:During four periods from the 1st period to the 4th period of a serial clock phi1, odd bit data D1, D3, D5, D7 are read out from the 1st SAM part 26a. Even bit data D2, D4, D6, D8 are read out from the 2nd SMA part 26b. In four periods from the 2nd period to the 5th period, the odd bit data and the even bit data are alternately selected and outputted by a data selector 32. Thereby, eight bit data D1 to D8 can be read out twice the convensional reading speed in twice the frequency of the clock phi1. The selector 32 outputs an image to an external image processing part through a terminal 34.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention is mainly used as a display memory of microcomputers and workstations, and includes a random access memory section (RAM section) consisting of a dynamic RAM and a serial The present invention relates to a dual port memory including an access memory section (SAM section).

<Prior Art> FIG. 5 is a block diagram of a conventional dual port memory.

In the figure, 2 is a RAM section configured with a DRAM (dynamic RAM) having memory cells of 8xk bits (k is an arbitrary integer), 4 is a random port, 6 is a data transfer line for 8 bits, and 8 is an 8-bit data transfer line. 10 is a 1 of 8 selector, 14 is an output terminal, and φ1 is a serial clock applied from the outside. Further, an output cover sofa (not shown) is usually provided between the dual port memory and the subsequent circuit.

Display data is written to the RAM section 2 via the random port 4. All the constituent bits of the specified 8-bit column data among the display data written in the RAM section 2 are transferred to the data transfer line 6 in the transfer cycle.
The data are collectively transferred to the SAM unit 8 via.

As shown in the time chart of FIG. 6, when the serial clock φ1 is externally applied to the 1 of 8 selector 10, the 1 of 8 selector 10
, the address from which the display data should be read from the SAM unit 8 is specified. This address specification is one period T of the serial clock φ.

The processing is performed sequentially in units of a1→a2-...-a8.

The SAM unit 8 starts reading data at the rising edge of the serial clock φ1, and after a predetermined access time elapses! The read data is determined at a and outputted via the output terminal 14 as DI-D2-...-D8.

As is clear from the above description of the operation, the speed at which data is read externally from the dual port memory is the same frequency as the frequency of the serial clock φ1.

<Problems to be Solved by the Invention> Incidentally, in recent image display systems for microcomputers and workstations, remarkable progress has been made in improving the resolution, and displays have also changed from interlaced (interlaced scanning) to non-interlaced (
There is a trend toward a progressive scanning (sequential scanning) method. Along with this, the speed of image display has also been significantly increased. Looking at the horizontal scanning frequency f, the conventional 15.75K
The speed has been increased from Hz to 35KHz and 60KHz.

In order to cope with this increase in image display speed in terms of hardware, it is essential to employ a reasonably high-speed memory as a video memory.

Conventionally, SRA is generally used as such high-speed memory.
M (static RAM) is used.

This is because SRAM has an element structure that is more suitable for high-speed reading than DRAM.

However, since SRAM uses flip-flops as its memory cells, it is considerably more expensive than dual port memories using DRAMs whose memory cells are capacitive elements (capacitors).

The present invention was devised in view of these circumstances, and is based on the premise of using dual port memory, which is widely used as display memory because it is relatively inexpensive and uses RAM. SAM department and SA
The purpose of this invention is to make it possible to output data at high speed even in a dual port memory by devising a circuit configuration around the M section.

<Means for Solving the Problems> In order to achieve the above object, the present invention has the following configuration.

That is, the dual port memory of the present invention includes a random access memory section made of dynamic RAM, N serial access memory sections (N is an integer of 2 or more),
It has a timing control section and a data selector.

The timing control section generates a serial clock that is to be given to each serial access memory section and has a lower frequency than the reference clock based on the reference clock input from the outside, and also generates a serial clock that is to be given to the data selector. The selection signal is configured to generate a selection signal that is switched to N states within one cycle of the serial clock.

Each of the serial access memory units collectively inputs and temporarily stores bit data obtained by sequentially distributing (N-1) bits of all constituent bits of the column data written in the random access memory unit, and The device is configured to sequentially transfer the temporarily stored distributed bit data to the data selector in synchronization with the serial clock every cycle of the serial clock.

Further, the data selector latches the distribution bit data of each cycle transferred from each serial access memory unit for the next one cycle, and also responds to switching of the N states of the selection signal. The latched distributed bit data from each serial access memory section is sequentially switched and output within one cycle of the serial clock.

<Effect> The effects of the above configuration of the present invention are as follows.

To state the conclusion first, in the conventional example, the serial clock
The data output during the period is only one bit, whereas in the case of the present invention, the data is output for N bits, which is the number of serial access memory sections. This will be explained below.

Looking at the period of one cycle of the serial clock,
The data selector latches N distribution bit data transferred from each of the N serial access memory units.

The data selector outputs the latched N distributed bit data in response to N state switching of the selection signal. It is done within.

Therefore, during one cycle of the serial clock, the data selector sequentially switches and outputs N distributed bit data.

That is, compared to the conventional example when the frequency of the serial clock is the same, column data written in the random access memory section can be read out N times faster.

<Example> Hereinafter, an example of the present invention will be described in detail based on the drawings.

FIG. 1 is a block diagram of a dual port memory according to an embodiment of the present invention.

The RAM section 20 has nXk bits (n is any integer)
DRAM (Guynamink RAM) with memory cells of
). Although n has 256 bits for -boat fishing, it is assumed here that n=8 to simplify the explanation.

This RAM section 20 stores the display data written from the random port 22, and also transfers all constituent bits of specified arbitrary 8-bit column data through the 8-bit data transfer line 24 in the transfer cycle. The data is configured to be transferred to the first and second SAM units 26a and 26b at once.

Both the first and second SAM sections 26a and 26b are constructed with 4-bit registers.

The first SAM unit 26a stores bit data DI, D3 . The second SAM section 26b is connected to the RAM section 20 via the data transfer line 24 so as to input the bit data D2 . D4. D6. D8
It is connected to the RAM section 20 via a data transfer line 24 so as to input the data.

The first SAM section 26a stores 4-bit odd bit data DI, D3 . A first l of 4 for sequentially reading D5 and D7 one by one in this order.
A selector 28a is attached.

Similarly, the second SAM section 26b stores the 4-focus even-numbered focus data D2. D4, D6. D
8, one by one in this order.
An of 4 selector 28b is attached.

The first l of 4 selector 28a sets the address from which data is to be read to the first SAM unit 26a for each period in units of one period T of the serial clock φ1. They are given sequentially like a3-a4 (see Figure 2). Similarly, the second 1 of 4 selector 28b also performs the following operations on the second SAM section 26b in each period, one period T1 as a unit.
Read address b 1 - b 2 = b 3 - b 4
It is designed to be given sequentially like this.

The timing control unit 30 receives a reference clock φ input from the outside. is divided by 2 to generate a serial clock φ to be applied to the first and second 1 of 4 selectors 28a and 28b, and a selection signal φ to be applied to the data selector 32.
, is configured to generate .

In the case of this embodiment, since the SAM section is divided into two, the first SAM section 26a and the second SAM section 26b, the selection signal φ2 has the same period as the serial clock φ1. . In addition, the reference clock φ given from the outside. The frequency of is 2 times the frequency of the serial clock φ,
It has doubled.

This reference clock φ given from the outside. corresponds to the serial clock φ given externally in the conventional example, but as mentioned above, the reference clock φ. The reason why is twice the frequency of the serial clock φ1 is because
This is due to the fact that the image display speeds of recent microcomputers and workstations have become faster.

The data selector 32 includes first and second data launch sections (not shown), and includes a first SAM section 26a.
The data input from the first SAM section 26b and the data input from the second SAM section 26b are simultaneously temporarily stored, and the launch data from the first SAM section 26a is output from the output terminal during the period when the selection signal φ is at the 'H'' level. 34, while the selection signal φ2 is at 1L level, the second SAM section 26b
It is configured to output the latch data from the output terminal 34 to the output terminal 34.

Next, the operation of the dual port memory having the above configuration will be explained using the time chart shown in FIG.

The premise is that display data has already been written to the RAM section 20 via the random port 22, and that all constituent bits of the 8-bit column data specified from the RAM section 20 are transferred in the transfer cycle. The first and second SAM sections 26a, 2 are connected via the line 24.
It is assumed that the information is transferred to 6b all at once and stored for - hours.

The data stored in the first SAM section 26a includes odd bit data D1. D3. D5. 4 vias of D7), and the data stored in the second SAM section 26b is the even focus data D2. D4D6. It is a D8 4 focus.

The timing control unit 30 receives an externally applied atsock φ. (Based on FIG. 2(a)), this reference black hole φ. Serial clock φI (Fig. 2(b)) with period T1 (frequency is 1/2) twice that of φ and selection signal φ
2 (Fig. 2 (1)) and generates the serial clock φ
1 to the first and second l of 4 selectors 28a, 2
8b, while the selection signal φ2 is output to the data selector 3.
Output to 2.

First and second l of 4 selectors 28a, 28b
As shown in FIGS. 2(C) and 2(d), in the first period t1 of the serial clock φ, the address al is applied to the first and second SAM sections 26a and 26b, respectively.
, bl, and addresses a2., bl are specified in the second period t2.
b2 is specified, and address a3.b2 is specified in the third period t3. b
3, and the address a4.3 is specified in the fourth period t4. b4
Specify.

At the rising edge of the serial clock φ, data is read from specified addresses al and bl, and after a predetermined access time elapses, the read data D1 and D2 are determined, and the determined odd bit and even bit data Di and D
2 is output to the data selector 32.

In the second period t2 following the first period t1, the data selector 32 outputs the odd bit data D1 from the first SAM section 26a, as shown in FIGS. 2(g) and 2(h).
and even-numbered bit data D2 from the second SAM section 26b are latched into internal first and second data latch sections (not shown), respectively. This data latch starts at the rising timing of the selection signal φ2 (FIG. 2(i)) and is updated at the next rising timing.

Then, as shown in FIG. 2(j), the data selector 32 sends the bordered odd-numbered bit data D1 to the first data launch section during the period when the selection signal φ2 is at the "H" level (second
The even-numbered bit data D2 is outputted to the output terminal 34 during the first half of the period t2 and latched to the second data raft portion during the period when the selection signal φ2 is at "L" level (the first half of the second period t2).
2)).

That is, within a period of one period T1 called the second period t2,
Two bit data, odd bit data D1 and even bit data D2, are output.

Then, in the second period t2, the 10f4 selector 28a
, 28b to the designated addresses a2., 28b to the SAM units 26a, 26b. b2 is given, and in the second half of the second period t2 SA
Odd number bit data D3 and even number bit data D4 are output from the M sections 26a and 26b, and both data D3. D4 is latched,
Odd bit data D3 is output to the output terminal 34 in the first half of the third period t3, and even bit data D4 is output in the second half of the third period t3.

The same operation is repeated thereafter. That is, the third period t
3 specifies address a3. As a result of being given b3, odd bit data D5 is output in the first half of the fourth period t4, even bit data D6 is output in the second half, and finally, as a result of being given designated addresses a4 and b4 in the fourth period t4, the 5
Odd number bit data D7 is output in the first half of the period t5, and even number bit data D8 is output in the second half.

As described above, within the four period period from the first period t1 to the fourth period t4 regarding the serial clock φ,
Odd bit data DI, D are output from the first SAM section 26a.
3. D5. D7 is read out, and even-numbered bit data D2. D4. D6. D8 is read out, and the data selector 32 alternately selects and outputs odd bit data and even bit data within four cycles from the second cycle t2 to the fifth cycle t5, so the serial clock φ, Eight bit data D1 to D8 are processed at a frequency twice that of Dl-D2-...=
It can be read out in the original order like D8. This read speed is twice that of the conventional example, and the reference clock φ is higher.

High-speed reading of data is performed in a state corresponding to . Note that the bit data DI-D8 read from the data selector 32 via the output terminal 14 is output to an external image processing section.

For this high-speed readout, a timing control unit 30 and a data selector 32 are added, but the cost of the memory is sufficiently low compared to SRAM.
Since the AM unit 20) is used, overall high-speed data reading can be achieved at low cost.

In the above embodiment, as the SAM section, the first and second two
Although these SAM sections 26a and 26b are used, the present invention is not limited thereto, and may be configured using N SAM sections (N is any integer greater than or equal to 2). N
FIG. 3 shows the circuit configuration of the embodiment when =4, and FIG. 4 shows its time chart.

In this case, the timing control unit 30 controls the first to fourth SAM units 26a, 26b, 26c, and 26d.
or fourth l of 4 selector 28a, 28b, 2
8c and 28d, the serial clock φ obtained by dividing the reference clock φ0 by 2 is output as in the above embodiment, but the serial clock φ is output to the data selector 32.
, the first selection signal φ! having the same frequency and the same phase as . 1 and
A second selection signal φt1 delayed by 1/4 period
It is configured to output a selection signal φt□.

Moreover, the data selector 32 has φ□=“H”φ,=1L
The bit data D from the first SAM section 26a is
I (D5) and outputs φ2. =″H″, φtz=“
Bit data D2 (D6) from the second SAM section 26b is output during the period of "H", and φ,=1L", φ,-"H"
The bit data D3 from the third SAM section 26C during the period of
(D7) and outputs φ2. -“L”, φ22="L"
The bit data D4 from the fourth SAM section 26d during the period of
(DB).

As a result, eight bit data D1 to D8 are transferred to Dl-D2-... within a period of two cycles of the serial clock φ.
It is possible to read in the order of .=D8, and it is possible to read at a speed four times that of the conventional example.

Note that the first to fourth I of 4 selectors 28a.

Each SAM section 26a includes 28b, 28c, and 28d.

Address designations for 26b, 26c, and 26d are shown together due to space constraints.

<Effect of the invention> According to the present invention, the following effects are achieved.

All constituent bits of the column data in the random access memory section are distributed in skips of (N-1) bits, and the distributed focus data is temporarily stored in N serial access memory sections, and transferred from each serial access memory section. N distributed focus data is sent to 1 of the serial clock.
The launched N distribution bit data is launched into the data selector for a period of the cycle, and in response to the switching of the selection signal which is switched to N states within one cycle of the serial clock. Since the configuration is configured to sequentially switch and output within one period of the serial clock, if the frequency of the serial clock is the same, one
Column data can be read out at a speed N times (N is an integer greater than or equal to 2 and the number of serial access memory sections) compared to the conventional example in which only the data for the focus can be read out.

Therefore, even with dual-port memory using relatively inexpensive dynamic RAM (in other words, without using static RAM, which can operate at high speed but is considerably more expensive), modern microcomputers and workstations can This makes it possible to sufficiently respond to the increased data processing speed required in image display systems.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a dual port memory according to an embodiment of the present invention, and FIG. 2 is a time chart for explaining its operation. FIG. 3 is a block diagram of a dual port memory according to another embodiment of the present invention, and FIG. 4 is a time chart for explaining its operation. FIG. 5 is a block diagram of a conventional dual port memory, and FIG. 6 is a time chart for explaining its operation. 20... Random access memory section (RAM section) consisting of dynamic RAM, 26a, 26b... Serial access memory section (SAM section), 30... Timing control section, 32... Data selector, φ. ...Reference clock, φ, ...Serial clock, φ
2...Selection signal, Dl, D3. D5. D7...odd number focus data (divided focus data), D2. D4゜D6. DB...Even number bit data (distributed bit data)

Claims (1)

[Claims] (1) A random access memory section (20) consisting of a dynamic RAM, N serial access memory sections (26a, 26b) (N is an integer of 2 or more), a timing control section (30), and a data selector (32). ), the timing control unit (30) is a clock to be given to each serial access memory unit (26a, 26b) based on a reference clock (φ_0) input from the outside, and the reference clock (φ_0) A selection signal (φ_2) which is a signal to be given to the data selector (32) and which is switched to N states within one period of the serial clock (φ_1) is generated. ), and each of the serial access memory sections (26a, 26b) sequentially generates (N-1) all constituent bits of the column data written in the random access memory section (20). ) The bit data distributed one by one is input all at once and temporarily stored, and the serial clock (φ_
The data selector (32) is configured to sequentially transfer the temporarily stored distribution bit data to the data selector (32) every cycle of the serial clock (φ_1) in synchronization with the data selector (32). 32) latches the distribution bit data of each cycle transferred from each serial access memory unit (26a, 26b) for the next one cycle, and also latches the N states of the selection signal (φ_2). The distributed bit data from each latched serial access memory unit (26a, 26b) is transferred to the serial clock (φ_1) according to the switching of
) A dual port memory configured to sequentially switch and output data within one period.