JPH0414870A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To reduce the resistance of wirings formed across a step by so forming a lower polycrystalline silicon relatively thick to be etched back as to bury a groove generated between first wirings, flattening the surface, and depositing to cover a metal silicide. CONSTITUTION:A polycrystalline silicon 7 is so deposited sufficiently thicker than the half of the width of a grove 6 to bury the groove 6 by a vapor growing method. Then, the silicon 7 is entirely etched back to be reduced in entire thickness, and the surface is flattened. the etching back is desirably a dry etching method using halogen gas in view point of controllability as compared with a wet etching method. Then, as the metal silicide, WSi 8 is deposited by a sputtering method. Thus, thickly formed polycrystalline silicon is etched back to eliminate a step existing on a base to be flattened. As a result, the WSi can be formed as substantially flat wirings. Accordingly, a wiring length can be shortened by an amount corresponding to the elimination of the step to reduce a wiring resistance.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bit line structure in a memory LSI and a method for manufacturing a memory cell of a dynamic RAM (random access memory).

[Conventional technology]

In recent years, the minimum unit of a dynamic RAM (d-RAM) memory cell is a combination of one capacitor for storing charge as memory information and one switching transistor for storing or extracting charge from the capacitor. The mainstream is structured as . In addition, when integrating multiple memory cells as an LSI, it is necessary to supply charge to the word line, that is, the wiring for turning on and off the switching transistor, and the bit line, that is, the capacitor, necessary to select one cell. Alternatively, the wiring for drawing out is generally arranged such that the bit line is orthogonal to the word line. Furthermore, LSI
As technology becomes more highly integrated, that is, individual elements become smaller, metal silicide, which is a low-resistance material, is increasingly used for bit lines, especially in order to prevent the resistance of bit lines from increasing.

FIG. 2 is a schematic cross-sectional view showing an example of the manufacturing process of a memory cell when metal silicide is used for the bit line. S
After forming a thick 5 inch 212 layer on the i-substrate 11 to serve as an element isolation region, a Si0.13 layer to serve as a gate insulating film of a MOS transistor is formed, and then a gate electrode 14 to serve as a word line is formed. Next, a bit line consisting of a laminated film of polycrystalline 5117 and metal silicide 18 is formed, and the Si
After covering the exposed part of the bit line with 0°19, Si on the Si substrate surface in a predetermined area where a capacitor is to be formed is
02 is removed and the exposed Si substrate surface is removed from the polycrystalline Si.
20 is selectively grown (Figure a).

A Si nitride film 21 and a 5-inch film 222 are stacked (b
figure).

The 5-inch film 222 and the Si nitride film 21 in a predetermined area that will become a capacitor are successively removed using the nosography technique and the anisotropic try-soching technique (FIG. 0).

Polycrystalline 5i24 is formed (Figure d).

For example, an organic substance 25 such as a photoresist is coated on the entire surface by rotation, and the entire surface is etched by dry etching to embed the organic substance only in the concave portions.
(Figure 0).

The polycrystal 5i24 exposed on the surface of the convex portion is selectively removed (FIG. f).

The organic matter filling the recesses is selectively removed to expose the polycrystalline 5i24 that will become the storage electrode of the capacitor (Figure g).

A capacitor insulating film 26 (very thin) and a capacitor plate electrode 27 are formed (FIG. 6).

A memory cell can be constructed through the series of steps described above, and wiring is formed in subsequent steps to form an LSI.

[Problem to be solved by the invention]

The above-mentioned conventional technology uses a laminated structure of polycrystalline Si and metal silicide for the bit line to reduce resistance, but even with this structure, if you try to improve the degree of integration, the bit line will become relatively low. A problem has arisen in which the resistance of the LSI increases and the performance as an LSI deteriorates.

In addition, since metal silicide is used for the bit line, the metal silicide itself contaminates the entire surface of the Si substrate, causing a significant decrease in selectivity during selective growth of Si in a later process, resulting in a reduction in yield. There was a problem with reducing it.

An object of the present invention is to provide a semiconductor device having a wiring structure in which the resistance of wiring formed across steps is reduced.

Another object of the present invention is to avoid the problem of a significant drop in selectivity when Si is selectively grown on a substrate contaminated with metal silicide, and to simplify the manufacturing process of d-RAM.
An object of the present invention is to provide a method for manufacturing a semiconductor device that forms a memory cell.

[Means to solve the problem]

In order to achieve the above object, the second wiring, which is placed across the first wiring, is composed of a laminated film of polycrystalline Si and metal silicide. A relatively thick layer was formed so as to fill the trench where the first wiring was opened, and the surface was planarized. Then, metal silicide was deposited to form a deposited film.

In order to achieve the other objects mentioned above, a pattern of organic material is formed in a predetermined area, and the underlying insulating layer is selectively removed using the organic material as an etching mask to expose the conductor or semiconductor. As mentioned above, polycrystalline Si was formed on the entire surface without removing organic substances.

[Effect]

Flattening by etching back the polycrystalline Si located under the second wiring can fill in the grooves created in the first wiring and flatten its surface, so the metal layer to be laminated as a substantial wiring layer can be flattened by etching back. Silicide can be formed on a flat surface. the result.

When the trench is not filled with polycrystalline Si, the metal silicide extends along the step formed by the first wiring, and the wiring length of the metal silicide itself becomes long, making it impossible to reduce the resistance. Since it can be formed on polycrystalline Si, the actual wiring length can be shortened and wiring resistance can be reduced.

Further, the organic substance used to form a portion of the capacitor can be formed or processed without being affected by contamination of metal silicide present on the substrate surface. Furthermore, in the process, the organic material is silicon dioxide (Si), which has traditionally been used in semiconductor manufacturing processes.
○), Si nitride film (Si3N4), or polycrystalline Si
Etching can be performed with an infinite selection ratio for inorganic materials such as substrates and Si substrates, so even if the inorganic material is present in the underlying layer and the surface of the inorganic material is exposed in a part of the etched area during the etching process, the inorganic material can be etched. It is possible to selectively remove organic matter without etching it at all.It is clear that no plastic deformation will occur in the organic matter itself if it is heated and heated in an atmosphere substantially free of oxygen. Head) Due to the effects of the organic material mentioned above, it is possible to form polycrystalline Si on the entire surface of the organic material at a temperature of about 600° C. in a state where the organic material is subjected to a notch turn process.

In addition, conventionally, organic substances have been patterned using photoresist or potato wire, which is patterned by photolithography.
EB) It is used as a processing mask for the underlying material, as typified by resist, and is removed when the processing of the underlying material is completed. One of the features of the present invention is that it is used as a mask for processing the underlying material, and is used as a supporting base material for forming inorganic materials such as polycrystalline Si while leaving organic materials without removing them.

〔Example〕

Examples of the present invention will be described below.

Embodiment 1 In this embodiment, a wiring forming method, which is one of the gist of the present invention, will be explained with reference to FIGS. 3 and 1.

FIG. 3 shows an example of the conventional method.

5102102 with a thickness of 20 nm is formed on the Si substrate 101 by a thermal oxidation method, and then a polycrystalline layer 5 with a thickness of 350 nm is formed.
i103 was deposited over the entire surface by vapor phase growth. Further, a layer of Sin 104 having a thickness of nm was deposited by vapor phase growth. 5in 2104 and polycrystalline Si by well-known lithography and dry etching techniques
1-03 was processed to form a periodic wiring pattern corresponding to the word line of d-RAM. The width of the wiring is 0.5
μm, and the interval was set to 1 μm.

Next, the exposed sidewalls of the 5-polycrystalline Si 103 were covered with the same <SiO□ 104, and then polycrystalline 5i 105 and metal silicide 106 corresponding to the bit line were formed. First, polycrystalline 5i105 with a thickness of 200 nm was deposited by vapor deposition. Next, metal silicide +06 with a thickness of 150 nm was deposited by sputtering. This state is shown in FIG. 3(a).

In a wiring structure in which metal silicide 106 is deposited on polycrystalline 5i 105, the wiring resistance can be lowered by about one order of magnitude compared to a single wiring made of polycrystalline 5i 105. It is polycrystalline Si
This is because the resistivity of metal silicide is as low as about lX10-'Ω·l, whereas the resistivity of metal silicide is about lX10-'Ω·l.

Therefore, the actual wiring resistance depends on the resistance of the metal silicide layer 106. In this conventional example, 1, for example, d-RA,
M was fully applicable to 4-megabit LSIs, but it has become difficult to apply it to LSIs with a higher degree of integration because the wiring length becomes longer and the wiring resistance increases.

Another problem with this conventional example is that when processing the laminated film to form wiring, as shown in FIG. 3(b), metal silicide
06 tends to remain in the stepped portion, and therefore the polycrystalline 5i 105 below it remains without being etched, which tends to cause short circuits between wirings.

Next, an embodiment, which is one of the gist of the present invention, will be explained with reference to FIG.

Si022 with a thickness of 20 nm is formed on the surface of the Si substrate 1 by thermal oxidation, and a polycrystalline Si3 layer with a thickness of 350 nm is formed on the north side of the Si022 layer with a thickness of 20 nm.
is deposited by vapor phase growth method.

Furthermore, 5i024 with a thickness of 200 nm was deposited by vapor phase epitaxy, processed by lithography and dry etching to form periodic wiring equivalent to the tool L-line, and
OONM 5i025 was deposited by vapor phase growth. Since SiO25 needs to be deposited so as not to form an overhang shape at the stepped portion, SiH, (monosilane) and N,O (- dinitrogen oxide) are deposited in a temperature range of 750°C to 800°C as conditions for vapor phase growth. (all vapor phase growth of SiO2 described below used these conditions)
.

As a result, a groove 6 with vertical side walls is formed (Fig. 8). The process up to this point is the same as the conventional example.

Next, polycrystalline Si 7 was deposited by vapor phase growth to a thickness sufficiently thicker than half the width of the groove 6 so as to fill the groove 6 (Figure b).

Next, the entire surface of the polycrystalline Si7 was etched back to reduce the overall thickness and flatten the surface.

The etch back used here may be a wet etching method, but a dry etching method using halogen gas has better controllability (Figure 0).

Next, tungsten silicide (WSi) 8 with a thickness of 150 nm was deposited as a metal silicide by sputtering (Figure d).

According to this example, by etching back the thickly formed polycrystalline Si, it is possible to eliminate the step existing in the underlying layer and achieve flattening, and as a result, the WSi can be formed as a substantially flat wiring. can. Therefore, compared to the conventional example shown in Fig. 3, in which the wiring is routed faithfully to the underlying level difference, the wiring length can be shortened by the fact that there is no actual level difference, and the wiring resistance can be reduced. There is. Further, since the WSi is formed flat, processing is extremely easy and there is an effect that no etching residue is left.

Furthermore, in an actual LSI pattern, there is always a termination of periodically arranged wiring, resulting in a step 9 shown in figure e6.However, even in this case, if the polycrystalline Si is etched back, the slope of the step can be greatly alleviated. This has the effect of making it possible to process metal silicide without leaving an etch residue.

Furthermore, as shown in figure e, conduction may be established with the impurity diffusion layer 10 formed on the surface of the semiconductor substrate.
Even in this case, since the inside of the trench is completely filled with polycrystalline Si, there is an effect that conduction between the metal silicide and the impurity diffusion layer can be easily ensured. One feature of the present invention is the use of polycrystalline Si, which is formed by introducing impurities during film formation.

Table 1 shows the results of measuring and comparing the wiring resistances of the conventional example and the example of the present invention.

As is clear from the above results in Table 1, even if the wiring is placed across a level difference in the base, according to the present invention, the same resistance as when there is no level difference in the base (sheet resistance in Table 1) can be obtained. effective. Moreover, the above results show that W Si /polycrystalline S
This shows that the resistance value of the laminated wiring made of i is dominated by WSi.

Therefore, in the present invention, WSi is deposited on flattened polycrystalline Si.
Another feature is that the wiring is formed by laminating layers of titanium silicide (which has an even lower resistivity) and tungsten.

Example 2 This example uses the wiring formation method described in Example 1, and further uses an organic material to simplify the manufacturing process.
A method for manufacturing the M memory cell will be explained with reference to FIGS. 4 and 5.

First, FIG. 4 shows an example of a planar layout of a d-RAM memory cell. Words arranged vertically,! 1,2
, 3.4 and the bit lines 1, 2, 3.4 arranged horizontally
are orthogonal. Word line 2 to show the diagram more clearly
The boundaries between the bit lines 3 and 3 are indicated by diagonal lines.

In the figure, attention is paid to word line 2 and bit line 3 in the sense of selecting one memory cell. When the word line 2 is turned on, the charges accumulated in the capacitor formation area are
Contact B, semiconductor substrate directly under the word line.

The signal flows to the bit line 3 via the bit line contact C, and information is transmitted.

An embodiment of the present invention will be described with reference to FIG. 5 using a cross-sectional shape taken along a broken line indicated by AA' in FIG. 4.

On a P-type 10Ω·■ Si single-crystal substrate 201, a 5in22 film with a thickness of 500nm was formed to serve as an element isolation region using a well-known method.
02 was formed. MOS) - 10 nm thick Si○2203, which will be the gate oxide film of the transistor, is formed by thermal oxidation, 350 nm thick polycrystalline Si is deposited by vapor phase epitaxy, and 250 nm thick 5i022O is formed.
5 was deposited by vapor phase epitaxy. Word lines 204 were formed by processing SiO2205 and polycrystalline Si using lithography and dry etching. Next, Word, I! After coating the sidewalls of 205(7) with 5jO2205, 5in2 of the bit line contact 206 area (corresponding to area C in FIG. 4) was removed using lithography and dry etching (Figure a).

Next, bit lines were formed by the method described in Example 1.

First, polycrystalline 5i207 having a thickness of 500 nm was deposited by vapor deposition. Incidentally, when depositing the polycrystalline 5i207, phosphine (PH,) gas was introduced at the same time, and the film was deposited while containing phosphorus. In this embodiment, the spacing force between the word lines 204 is set to 1300 nm, so by setting the film thickness of polycrystalline Si to 500 nm, the grooves formed between the word lines can be completely filled. Example 1
As mentioned above, one of the key points of the present invention is to set the thickness of the polycrystalline Si film so as to fill the recesses existing in the underlying layer (Figure b).

Next, polycrystalline 5i207 was etched back by a dry etching method using halogen gas of sulfur hexafluoride (SF). At this time, control was performed so that about 1100 nm of polycrystalline 5i207 remained on the word line. Even immediately after forming polycrystalline Si, its surface +i.

Although the bit line is almost flat, if the bit line is formed by laminating metal silicide as it is, the processing of the bit line itself and the step caused by the bit line will become high, which will make processing in the later wiring process difficult. Therefore, one of the features of the present invention is to etch back the polycrystalline Si to reduce the substantial film thickness and reduce the step difference in the bit line itself. The range of etchback is
It is desirable to remove 80±10% of the formed film thickness (Figure 0).

Next, using a sputtering method, a WSi2 film with a thickness of 150 nm was
8 was deposited (Fig. d).

Furthermore, SiO2209 with a thickness of 300 nm was deposited by vapor deposition. SiO2209, W S1208, and polycrystalline 5i207 are processed by lithography and dry etching to form bit wiring (Figure e).

A 5 inch 2210 film with a thickness of 1100 nm was formed on the entire surface by vapor phase growth to cover the side walls of the WSi 208 and the polycrystalline 5i 207 (Figure f).

Next, a capacitor was formed. Polyimide resin 211 was formed using a spin coating method so that the thickness at the flat portion was 700 nm. As the polyimide resin, for example, type PiX-LLIO manufactured by Hitachi Chemical Co., Ltd. can be used. After applying the polyimide resin, heat treatment was performed at 600° C. for 20 minutes in an atmosphere of 1 atm or less. Next, Example 3
A hole 212 was formed in the capacitor formation region by the multilayer resist method described in . Polyimide resin, like photoresist, could be processed using only active oxygen (Figure g).

Next, using the polyimide resin 211 as a mask, the Si substrate 2
By selectively removing only SiO□ 210 on 01
The surface of the substrate was exposed and hole contacts 213 were formed. This selective removal of SiO□210 was performed using a dry etching method using a halogen gas (Figure h). In addition, 5
During the dry etching of in2, an extremely thin and degraded layer may be formed on the surface of the polyimide, so in that case it is desirable to lightly (etch) the surface portion using oxygen.

Next, the polyimide resin used as a mask for forming the hole contact 213 was left unremoved, and a polycrystalline 5i 214 with a thickness of 1100 nm was made to become the storage electrode of the capacitor.
was deposited. Impurities may be introduced into the polycrystalline 5i 214 during film formation as in the case of the polycrystalline 5i 207, but may also be introduced by ion implantation after formation.

However, when using the ion implantation method, since the polycrystalline Si stands vertically on the side wall of the polyimide resin, it is necessary to implant the ions so that they are incident obliquely (i
figure).

Next, photoresist is formed on the entire surface by spin coating so that the thickness at the flat part is 1 μm, and it is etched back to leave the photoresist 215 only in the holes, exposing the surface of the polycrystalline 5i 214 on the polyimide resin 211. Let (
Figure 5).

The exposed polycrystal 5i 214 on the polyimide resin 211 was selectively removed by dry etching (Figure k).

Polyimide 4 by oxygen plasma! t m 211 and the photoresist 215 were removed to form a polycrystalline Si screen, which served as the storage electrode 216 of the capacitor (Figure Q).

When this storage electrode 216 is viewed planarly from the front side, it corresponds to the capacitor formation region in FIG. 4.

Next, a capacitor insulating film 217 is formed, and a capacitor plate electrode 218 is further formed to complete the back-passing process of the memory cell (Figure m).

Thereafter, a wiring formation process was carried out to connect peripheral circuits to form an LSI. In this example, we explained the procedure of processing the polyimide resin and then processing the base 5in2 to form hole contacts.However, hole contacts were formed first and polyimide was applied with the Si substrate surface exposed. It is possible to form a polycrystalline Si screen with higher precision by performing the process that includes drilling.

According to this example, the formation of holes is extremely suppressed by using an organic material that has a selectivity close to infinity with respect to inorganic materials such as SiO and Si as the base material for forming the screen of the storage electrode. It has an effect that is easy to perform. therefore,
Unlike the conventional example shown in Fig. 2, it is no longer necessary to raise the exposed Si substrate surface by selective CVD to make contact with the storage electrode, and as a result, when WSi is used for the bit line, WSi S, which should not originally grow during selective CVD of polycrystalline Si due to its own contamination.
It is possible to avoid an interlayer in which Si nuclei grow also on the i02 surface and significantly reduce selectivity, which has the effect of significantly improving manufacturing yield.

Also, formation of polycrystalline Si by selective CVD method.

It has the effect of simplifying processes such as forming the Si nitride film and forming 5in2, and can also be formed using only an extremely simple rotary coater, improving safety and reducing costs. bring about.

Embodiment 3 In this embodiment, an application example of the present invention in combination with lithography technology will be explained with reference to FIG. 6th
The figure is an example of a case where a multilayer resist method is used.

As described in Examples 1 and 2, on the Si substrate 301,
A polycrystalline 51302 wiring corresponding to a d-RAM word line is formed, and a 5in2303 wiring is formed by vapor phase growth method.
The entire surface was covered with the Si substrate, and a simulated step was formed on the Si substrate. The height of the step was set to be approximately 500 nm. Next is a multilayer resist process. First, the thickness at the flat part is 1.
An organic material 304 serving as a 5 μm lower resist layer was formed by a spin coating method. At this time, it is important to select the thickness of the organic material 304 so that the surface of the organic material 304 is flat.

Next, an SOG (spin coating glass) 305 with a thickness of 1100 nm was formed as an intermediate layer, and a photoresist 306 with a thickness of 600 nm was further formed as an upper resist layer by a spin coating method. Next, a photoresist 3 is applied using a well-known photoetching method.
A pattern was formed on 06, and the 5OG305 was tri-etched using the photoresist 306 as a mask to transfer the pattern (FIG. 8).

Next, the organic substance 304 was etched by dry etching using oxygen as a well-known technique, and then pattern transfer was performed. At this time, the upper layer photoresist 306 is etched and disappears at the same time, but since the 5OG 305 remains without being etched by oxygen, the organic substance 304 can be processed with high precision using this as a mask (Figure b).
.

Next, using the organic material 304 as a mask, the 5 inch
Selectively etched 2302.

The surface of the Si substrate was exposed and a contact 307 was formed (
Figure C).

In the conventional method, organic matter 3 used for processing 5in2302
This required a complicated process of once removing 04, forming another inorganic material such as a Si nitride film over the entire surface, and drilling holes in the other inorganic material again using a multilayer resist method.

One feature of the present invention is that the organic material 304 used as a mask for processing 5iO2 302 is not removed, but remains, and polycrystalline 5i 308 is deposited thereon by vapor phase growth.

Hereinafter, according to the method used in Example 2, polycrystalline 5i308
A screen was formed (Figure d).

According to this embodiment, after selectively removing SiO□ using an organic substance as a mask and exposing the surface of the Si substrate.

Since polycrystalline Si is formed using itself as a supporting base material without removing the organic material used as a mask, it ensures continuity between the polycrystalline Si and the Si substrate, and at the same time makes the screen extremely easy and controllable. It has the effect of forming well.

The organic material 304 used in this embodiment may be any organic material other than polyimide resin as long as it can be etched with oxygen.

In addition, in this example, the gist of the present invention was described in combination with a multilayer resist method, but a single layer resist method, that is, a pattern is formed directly on the base material using a photoresist, an EB resist, etc., and then polycrystalline Si is formed. It is also possible to form

Embodiment 4 In this embodiment, an example will be explained with reference to FIG. 7, in which only most of a predetermined region is filled with polycrystalline Si using a method of forming polycrystalline Si on an organic material.

Polycrystalline 5i 402 wiring is formed on the Si substrate 401,
The entire surface was covered with 5 inch 2403 to form a simulated step (
Figure a).

A polyimide resin 404 was formed by a spin coating method, and the polyimide resin in a predetermined region was selectively removed by the multilayer resist method described in Example 3 to form a contact hole 405 (Figure b).

Next, polycrystalline 5i4 is added to fill the contact hole 405.
06 was deposited by vapor phase growth method (Figure 0).

Contact hole 40 by etching back polycrystalline 5i406
Polycrystalline 5i406 remained only inside 5 (Figure d)
.

Next, polyimide resin 404 was removed using oxygen plasma (
Figure e).

According to this embodiment, the selective CVD shown in the conventional example of FIG.
There is an effect that polycrystalline Si can be left and buried only in a predetermined region without using a method.

〔Effect of the invention〕

According to the present invention, the wiring arranged across the base level difference can have a substantially flat structure, which has the effect of lowering the resistance of the wiring itself.

Furthermore, in a memory LSI in which bit lines are arranged across word lines arranged periodically, by making the structure of the bit lines substantially flat, the wiring resistance of the bit lines can be reduced, resulting in faster circuit operation. Look, Memory LS
This has the effect of improving the performance of I. In particular, bit lines are placed directly on word lines with an insulating film interposed therebetween. A remarkable effect can be obtained in a so-called shielded bit line type d-RAM.

In addition, since a part of the capacitor that constitutes the memory cell can be formed using an organic material, the process margin can be improved and the process can be significantly simplified.Furthermore, since there is no need to use selective CVD, the metal silicide itself can be formed. It is possible to avoid the problem of becoming a source of contamination and lowering selectivity and lowering manufacturing yield, which has the effect of significantly improving manufacturing yield.

Further, since the organic material used in the lithography process can be used as is, the process can be simplified and the pattern shape can be formed with high accuracy.

[Brief explanation of drawings]

Fig. 1 is a series of process sectional views showing an example of the present invention, Fig. 2 is a series of process sectional views showing an example of a conventional manufacturing method, and Fig. 3 is a series of process sectional views showing an example of a conventional manufacturing method. 4 is a plan layout diagram of a supplementary memory cell for explaining FIG. 5, and FIGS. 5, 6, and 7 are a series of diagrams showing an embodiment of the present invention. Grandchild 11 Father-in-law?口(child) (Wholesale()L) ■ Figure Figure 4 -Ya Figure Country Z16 Go tr41, Ko'J') I-

Claims (1)

[Claims] 1. Second wirings are periodically and repeatedly arranged on a plurality of first wirings arranged repeatedly on a semiconductor substrate so as to cross the first wirings with an insulating film interposed therebetween. What is claimed is: 1. A semiconductor device having a wiring structure comprising a wiring structure, wherein the surface of the second wiring is substantially flat. 2. The semiconductor device according to claim 1, wherein the second wiring has a structure in which a metal layer or a metal silicide layer is laminated on a Si layer. 3. The semiconductor device according to claim 2, wherein the Si layer is formed inside a groove formed by an adjacent first wiring and has a flat surface. 4. The semiconductor device according to claim 2 or 3, wherein the Si layer is polycrystalline Si into which doping impurities are introduced. 5. A semiconductor device comprising a memory LSI in which the first wiring is a word line and the second wiring is a bit line. 6. In a dynamic memory LSI whose minimum cell unit is a combination of one MOS transistor and one capacitor, the word line serving as the gate electrode wiring of the MOS transistor is used as the first wiring and connected to the source. A dynamic RAM in which a bit line is formed by the second wiring and a storage electrode of a capacitor is connected to the drain. 7. Step of forming the first wiring that will become the gate electrode (word line) of the MOS transistor; Step of covering the exposed part of the first wiring with an insulating film; Step of forming the source and drain regions; Part of the source region a step of exposing the surface of the semiconductor substrate, a step of depositing a first Si film having a film thickness of at least half the distance between adjacent word lines while introducing impurities, and a step of depositing the deposited first Si film. A process of etching back the entire surface to make the surface flat, a process of depositing metal or metal silicide in a laminated manner, the first S
A process of patterning a laminated film of an i film and a metal or metal silicide to form a second wiring that will become a bit line, a process of covering the exposed part of the second wiring with an insulating film, and a process of coating the first organic material on the entire surface. a step of selectively removing a predetermined region of the first organic material to form a hole, a step of exposing a portion of the semiconductor substrate surface within the hole, a step of depositing a second Si film, a step of forming a second organic material on the entire surface; a step of etching back the entire surface of the second organic material to expose the surface of the second Si film formed on the surface of the first organic material; A step of selectively removing the exposed second Si film, selectively removing all the first and second organic substances, and removing the second Si film which will become the storage electrode of the capacitor.
A method for manufacturing a semiconductor device, comprising at least the steps of forming a screen made of a film, forming a capacitor insulating film, and forming the other electrode of the capacitor in the above order. 8. The above organic substances include polyimide resin, photoresist, E
8. The method of manufacturing a semiconductor device according to claim 7, wherein the organic material is an organic material such as a B resist that can be spin-coated onto a substrate. 9. Claim 7, wherein the second Si film is a Si film formed by introducing impurities at the same time as the film is formed.
A method of manufacturing the semiconductor device described above. 10. The second Si film is made of S formed in an amorphous state.
8. The method of manufacturing a semiconductor device according to claim 7, wherein the Si film is a Si film into which impurities are introduced into i by ion implantation. 11. Part of the surface of the semiconductor substrate is exposed before forming the first organic material on the entire surface, and then the first organic material is formed on the entire surface, and the first organic material is formed above the area where the surface of the semiconductor substrate is exposed. 8. The method of manufacturing a semiconductor device according to claim 7, wherein the hole is formed by removing. 12. A method for manufacturing a semiconductor device, comprising forming polycrystalline Si on an organic pattern formed by photolithography. 13. Using the organic material pattern formed by photoetching as a mask, the base insulating film is selectively etched away, and polycrystalline Si is formed with the organic material pattern remaining, and the conductor or semiconductor under the insulating film and polycrystalline silicon are removed. A method for manufacturing a semiconductor device characterized by establishing electrical conduction with crystalline Si.