JPH0414866A - Semiconductor device - Google Patents

Abstract

PURPOSE:To increase the area of a capacitor electrode by forming sidewalls protruding from both sides of a transfer gate and forming a lower electrode, a capacitor insulating film and an upper electrode from a field oxide film of the drain region side of a MOS transistor to the top of the gate through an interlayer insulating film. CONSTITUTION:Sidewalls 6 of asilicon dioxide layer is formed, and ions are implanted to form n<+> type impurity regions 7, 8. Then, a silicon nitride film 5 is removed, formed in a square sidewall 6 protruding upward from the upper surface of a gate electrode 4, a silicon dioxide film 9 is grown as an interlayer insulating film by a CVD method, and a contact hole 10 connecting the region 8. Then, a polysilicon film is grown thereon by a CVD method, and a capacitor lower electrode 11 for a memory cell is formed. Thereafter, a nitride film 12 is formed as a capacitor insulating film on the electrode 11 by a CVD method, and an oxide film is formed on the film 12 by a thermal oxidizing method. Then, a polysilicon film is so grown as to cover the oxide film by a CVD method, and etched to form a capacitor upper electrode 13 for the cell.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a stacked dynamic RAM.

[Conventional technology]

An example of a memory cell structure of a conventional stacked dynamic RAM will be described with reference to FIG.

In FIG. 3, 1 is, for example, a P-type silicon substrate, and a field oxide film 2 is formed on the surface of this substrate 1. An n-type source region 7 and an n-type drain region 8 of a MOS transistor are formed on the surface of the P-type silicon substrate 1 surrounded by this field oxide film 2, and the n-type drain region 8 and the lower surface electrode 11 of a memory cell capacitor are formed. The connection is made through a contact hole formed in the interlayer insulating film 9. A memory cell capacitor upper electrode 13 is formed on the upper surface of the lower electrode 11 with an insulating film 12 interposed therebetween. A transfer gate electrode 4 is formed on the surface of the P-type silicon substrate 1 between the drain region 8 and the source region 7 with a gate insulating film 3 interposed therebetween, and an interlayer insulating film 9 is formed on this.
The source region 7 and the silicide wiring 16 are connected through a contact hole formed in the interlayer insulating film 14.

Such a stacked dynamic RAM is called a one-transistor, one-capacitor type, and its operation is as follows. That is, at the time of writing, an information charge is applied to the n-type source region 7 and the transfer gate electrode 4 is brought into a selected state. Charge is accumulated between the upper surface electrode 13 and the upper surface electrode 13 via the upper surface electrode 13.

By setting the transfer gate 4 to a non-selected state in this state, data is held. At the time of reading, the accumulated charges are transferred to the n-type source region 7 by placing the transfer gate 4 in a selected state.

[Problem to be solved by the invention]

In the conventional stacked dynamic RAM described above, a cell capacitor consisting of a memory cell capacitor bottom electrode 11, an insulating film 12, and a memory cell capacitor top electrode 13 is formed from the middle on the transfer gate to the field oxide film, and the capacitor The shape of the electrode is spread out in a plane. Therefore, such a structure has the problem that it cannot cope with the increase in the capacity of the cell capacitor while the unit cell area has been reduced due to the increase in storage capacity in recent years.

[Means to solve the problem]

In the semiconductor device of the present invention, protruding sidewalls are formed on both sides of the transfer gate, and M
OS) A lower surface electrode, a capacitor insulating film, and an upper surface electrode are formed from the field oxide film on the drain region side of the transistor to the upper part of the transfer gate. With such a structure, the area of the capacitor electrode can be increased without increasing the unit cell area.
Capacity of the capacitor can be increased.

〔Example〕

Next, the present invention will be explained by examples.

FIGS. 1(a) to 1(c) are cross-sectional views for explaining the first embodiment of the present invention in the order of manufacturing steps. In FIG. 1(a), a P-type silicon substrate l is oxidized to 400% by selective oxidation.
A field oxide film 2 of about 0 is formed, on which a silicon dioxide film 3 of about 200 is formed by thermal oxidation, and then a polysilicon film of about 3000 is formed, which becomes a gate electrode, by CVD. 4 and about 3
000 silicon nitride films 5 for exposing the horns are sequentially laminated. Then, using photolithography techniques, silicon dioxide 1lj3. ;t: Etching the three-layer stack of silicon film 4 and silicon nitride film 5 into a desired pattern;
An n'' type impurity region 7'8' is formed by ion implantation.Next, as shown in FIG. 1(b), a silicon dioxide layer 6 of approximately 2000 layers is formed using the CVD method to form a sidewall. , anisotropic dry etching is performed to form a sidewall 6 of silicon dioxide layer.Next, ion implantation is performed again to form the source of the LDD and transistor (
n+ impurity regions 7 and 8 which become drain (or source) regions are formed. Next, Figure 1 (c
), the silicon nitride film 5 is removed and the gate electrode 4 is
A horn-shaped sidewall 6 is formed that protrudes upward from the upper surface. Next, a silicon dioxide film 9 of about 2,000 layers is grown on the entire surface as an interlayer insulating film by the CVD method. A contact hole 10 communicating with drain impurity region 8 is formed in silicon film 9 . Next, approximately 4,000 people grow a polysilicon film on top of it using the CVD method, which will become the bottom electrode of the capacitor.
A desired pattern is etched using photolithography to form the memory cell capacitor lower surface electrode 11. Thereafter, approximately 100 nitride films 12 are grown as a capacitor insulating film on the lower electrode 11 by CVD, and then an oxide film is formed on the surface of the nitride film 12 by thermal oxidation.

Then, a polysilicon film of approximately 1,500 layers, which will become the upper surface electrode of the capacitor, is grown using the CVD method so as to cover the oxide film, and etched using the photolithography technique to form the capacitor upper surface electrode 13 for the memory cell. Next, a silicon dioxide layer 14 is grown as an interlayer insulating film over the entire surface by CVD, a contact hole 15 leading to the source region 7' is formed in the silicon dioxide layer 14 by photolithography, and then, for example, silicide is grown. It is deposited by a sputtering method, and the wiring 16 is formed using a photolithography technique.

Next, a second embodiment of the present invention will be described using FIGS. 2(a) and 2(b). In FIG. 1(c) of the first embodiment,
After growing the silicon dioxide film 9 by CVD method,
When forming a contact hole leading to the drain region 8 in the silicon dioxide film 9 by photolithography, the photoresist 21 is removed from the sidewall 6 to the field oxide film 2, as shown in FIG. 2(a). Thereafter, the silicon dioxide film 9 is etched, and as shown in FIG.
), a self-line contact hole 22 communicating with the drain region 8 is formed. Thereafter, the same process as in the embodiment of FIG. 1 is performed to form the lower surface capacitor electrode 11 and capacitor insulation! In 12 , the upper surface electrode 13 and the like are formed.

〔Effect of the invention〕

As explained above, the present invention makes it possible to increase the area of the capacitor electrode without reducing the degree of integration of the memory cell by forming the sidewall of the MOS transistor of the memory cell of the stacked dynamic RAM into an angular shape. This has the effect of increasing capacity.

[Brief explanation of drawings]

FIGS. 1(a) to 1(c) are cross-sectional views for explaining the first embodiment of the present invention in the order of manufacturing steps, and FIG. 2(a) is a sectional view of the first embodiment of the present invention. (b) is a cross-sectional view for explaining the second embodiment of the present invention in the order of manufacturing steps, and FIG. 3 is a cross-sectional view of a conventional semiconductor device. 1... P-type silicon substrate, 2... Field oxide film, 3... Gate insulating film, 4...
... Gate electrode, 5... Nitride film for protruding horns,
6... Side wall, 7... Source region, 8... Drain region, 9°14...
...Interlayer insulating film, 10.15...Contact hole, 11...Capacitor bottom electrode, 12...
--- Capacitor insulating film, 13 --- Capacitor top electrode, 16 --- Silicide wiring. Agent: Susumu Uchihara, patent attorney Figure 1

Claims (1)

[Claims] A gate electrode formed on a semiconductor substrate of one conductivity type via a gate insulating film, and a source (or drain) of the opposite conductivity type formed on the substrate with the gate electrode sandwiched between the gate electrodes on both sides of the gate electrode. and a drain (or source) region, and a memory cell capacitor formed over the gate electrode and over the drain region and comprising a lower surface electrode and an upper surface electrode with an insulating film in between. Insulating sidewalls protruding from the upper surface of the gate electrode are formed on both sides of the electrode, and the memory cell is connected to the memory cell from the upper surface of the gate electrode to the upper surface of the drain region through an insulating film, including the sidewall on the drain side of the sidewall. A semiconductor device characterized in that a capacitor is formed therein.