JPH0414863A - Forming method for resistance element of semiconductor device - Google Patents

Forming method for resistance element of semiconductor device

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Publication number
JPH0414863A
JPH0414863A JP11792890A JP11792890A JPH0414863A JP H0414863 A JPH0414863 A JP H0414863A JP 11792890 A JP11792890 A JP 11792890A JP 11792890 A JP11792890 A JP 11792890A JP H0414863 A JPH0414863 A JP H0414863A
Authority
JP
Japan
Prior art keywords
region
resistance
conductivity type
resistor
resistance element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11792890A
Other languages
Japanese (ja)
Inventor
Takashi Omori
孝 大森
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
JFE Steel Corp
Original Assignee
Kawasaki Steel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kawasaki Steel Corp filed Critical Kawasaki Steel Corp
Priority to JP11792890A priority Critical patent/JPH0414863A/en
Publication of JPH0414863A publication Critical patent/JPH0414863A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To obtain a resistance element having high resistance without increasing the length of the element by forming a second conductivity type region partly at the element, and reducing the sectional area of the resistance part to be conducted. CONSTITUTION:Part of a high resistor 3A except a region S2 is masked with photoresist, and P-type impurity ions such as second conductivity type boron, etc., are so implanted in polycrystalline silicon 3 of the region S2 in a predetermined depth. Thus, the region S2 becomes a reverse conductivity type region 4 of second conductivity type to form a junction to a region S1 in which an N-type impurities are implanted. Thereafter, with photoresist as a mask an unnecessary part is etched to form a resistance element R of the resistor 3A and the region 4, and a wiring W is formed of a low resistor 3B. Thus, even if a current is fed in an arbitrary direction in the region 4, a current is scarcely fed, and the resistor 3A formed previously is reduced in sectional area in thickness corresponding to the region 4, thereby enhancing its resistance value.

Description

【発明の詳細な説明】 〔産業上の利用分野] この発明は、抵抗素子を有する半導体装置の抵抗素子の
形成方法であって、抵抗素子の一部に逆接合となる領域
を有する抵抗素子を形成する方法に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention is a method for forming a resistor element of a semiconductor device having a resistor element, which includes a resistor element having a region that is a reverse junction in a part of the resistor element. Concerning the method of forming.

〔従来の技術〕[Conventional technology]

従来、不純物イオンを導入して半導体装置に抵抗素子を
形成する方法には、例えば特開昭60−74465号公
報に記載される方法があった。
Conventionally, as a method for forming a resistance element in a semiconductor device by introducing impurity ions, there is a method described in, for example, Japanese Patent Laid-Open No. 60-74465.

すなわち、この方法によっては、まず、上面を絶縁した
基板上に多結晶シリコンを形成し、この多結晶シリコン
に、N型又はP型不純物を導入することにより配線とな
る低抵抗体を形成する。そして、ホトレジストにより所
定の領域をマスクし、この領域以外に、先に多結晶シリ
コンに導入した不純物イオンと反対型の不純物イオンを
重ねて導入し、この領域の低抵抗体を抵抗素子となる高
抵抗体に変化させることにより、半導体装置に抵抗素子
を形成する。
That is, depending on this method, first, polycrystalline silicon is formed on a substrate whose upper surface is insulated, and a low-resistance material serving as a wiring is formed by introducing N-type or P-type impurities into the polycrystalline silicon. Then, a predetermined region is masked with photoresist, and other than this region, impurity ions of the opposite type to the impurity ions introduced into the polycrystalline silicon are superimposed, and the low-resistance element in this region becomes a high-resistance element. A resistive element is formed in a semiconductor device by changing it into a resistor.

かくして、この抵抗素子の形成方法によっては、高抵抗
体と低抵抗体間のイオンの濃度勾配が低くなるために、
多結晶シリコンに不純物イオンを導入する際、この不純
物イオンがマスクした領域以外に拡散することを防止す
る効果が得られる。
Thus, depending on the method of forming this resistance element, the concentration gradient of ions between the high resistance element and the low resistance element becomes low.
When introducing impurity ions into polycrystalline silicon, the effect of preventing the impurity ions from diffusing outside the masked region can be obtained.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかしながら、近年、半導体装置は高集積化が進み、こ
の半導体装置に形成される抵抗素子はそのサイズが幅1
〜2μ、長さ2〜4μにまで小型化されているが、その
一方で抵抗値も10’〜1012Ωの高抵抗ものが要求
されている。
However, in recent years, semiconductor devices have become highly integrated, and the resistance elements formed in these semiconductor devices have a width of 1
Although the size has been reduced to ~2μ and length of 2 to 4μ, high resistance values of 10' to 1012Ω are required.

そして、前記従来の抵抗素子の形成方法によっては、抵
抗素子となる高抵抗体と、その他、配線となる低抵抗体
との厚みが同一となるが、配線の断面積が小さくなると
配線抵抗が上昇するために、抵抗素子の抵抗値を上げる
手段として多結晶シリコンの厚さ自体を薄(することは
できない。従って、抵抗素子の抵抗値を上昇させるため
には抵抗素子を長(しなければならず、上記のような高
抵抗で且つ小型の抵抗素子を形成することは困難であっ
た。
Depending on the method of forming the conventional resistance element, the thickness of the high resistance element that becomes the resistance element and the low resistance element that becomes the wiring becomes the same, but as the cross-sectional area of the wiring becomes smaller, the wiring resistance increases. In order to increase the resistance value of a resistor element, it is not possible to reduce the thickness of the polycrystalline silicon itself.Therefore, in order to increase the resistance value of a resistor element, it is necessary to make the resistor element longer. First, it has been difficult to form a small resistance element with high resistance as described above.

また、前記従来例によって形成された抵抗素子を加工し
、高抵抗体の部分のみをエツチングすることにより抵抗
素子の厚みを薄くすることも考えられるが、抵抗素子の
強度が不足しクランク等が生じやすくなり、耐久性が低
下するために望ましい方法ではなかった。
It is also possible to reduce the thickness of the resistor element by processing the resistor element formed in the conventional example and etching only the high-resistance part, but this may result in insufficient strength of the resistor element and may cause problems such as cranking. This was not a desirable method because it made the process easier and the durability decreased.

一方、多結晶シリコンの成長過程途中において酸素をリ
ークして数人の厚さでシリコン酸化膜を形成し、その上
に多結晶シリコンを成長させる作業を繰り返すことによ
り多結晶シリコンのブレーンサイズを小さくし、もって
、抵抗値を上昇させる方法も提案されているが、同方法
では多結晶シリコンの成長過程が複雑で歩留りが悪くな
り、またエツチング形状も悪化するという問題点があっ
た。
On the other hand, during the growth process of polycrystalline silicon, oxygen is leaked to form a silicon oxide film several times thicker, and polycrystalline silicon is grown on top of it by repeating the process to reduce the brain size of polycrystalline silicon. However, although a method of increasing the resistance value has been proposed, this method has problems in that the growth process of polycrystalline silicon is complicated, resulting in a poor yield, and the etched shape also deteriorates.

そこで、この発明はこのような課題を考慮してなされた
ものであり、本発明の目的は、高抵抗で且つ小型の抵抗
素子を形成する一方で、抵抗素子の強度が低下すること
はなく、もって耐久性に優れ、抵抗素子形成の際の歩留
りに優れた抵抗素子を容易に形成する方法を提案するこ
とにある。
Therefore, the present invention has been made in consideration of such problems, and an object of the present invention is to form a high-resistance and small-sized resistance element, while not reducing the strength of the resistance element. The object of the present invention is to propose a method for easily forming a resistance element that has excellent durability and a high yield when forming the resistance element.

[課題を解決するための手段] この発明は、基板上に第1導電型の不純物イオンを導入
した多結晶シリコンにより、抵抗素子となる抵抗部を形
成する工程と、第2導電型の不純物イオンを、前記抵抗
部の少なくとも一部の表面から所定の深さに導入して第
2導電型領域を形成する工程と、を有してなる半導体装
置の抵抗素子形成方法を提案して、前記の課題を解決し
ている。
[Means for Solving the Problems] The present invention includes a step of forming a resistor portion to become a resistor element using polycrystalline silicon into which impurity ions of a first conductivity type are introduced onto a substrate, and a step of forming a resistor portion to be a resistor element using polycrystalline silicon into which impurity ions of a second conductivity type are introduced. A method for forming a resistor element of a semiconductor device is proposed, comprising the step of: introducing a second conductivity type region from the surface of at least a portion of the resistor portion to a predetermined depth, and Solving problems.

〔作用] 第1導電型としてN型又はP型のいずれか一方の不純物
イオンを導入した多結晶シリコンにより、基板上に抵抗
素子となる抵抗部を形成する。そして、この抵抗部の少
なくとも一部に、先に導入した不純物イオンと反対型の
、第2導電型の不純物イオンを所定の深さで導入するこ
とにより、この部分に第2導電型領域を形成し、同領域
にPN接合を形成する。
[Operation] A resistive portion serving as a resistive element is formed on a substrate using polycrystalline silicon into which impurity ions of either N type or P type are introduced as a first conductivity type. Then, by introducing impurity ions of the second conductivity type, which are of the opposite type to the previously introduced impurity ions, into at least a part of this resistance part to a predetermined depth, a second conductivity type region is formed in this part. Then, a PN junction is formed in the same region.

この状態にあっては、抵抗部に任意の方向に電流を流し
ても、第9導電型領域の一方の接合が電流を通し難いた
めに、その分、通電可能な抵抗部の断面積が減少し、も
って、抵抗素子の抵抗値が上昇する。従って、抵抗素子
の長さを長くすることなく高抵抗の抵抗素子を形成し得
るために、高集積化を達成する。
In this state, even if current is passed through the resistor in any direction, it is difficult to conduct current through one junction of the ninth conductivity type region, so the cross-sectional area of the resistor that can conduct current is reduced accordingly. However, the resistance value of the resistance element increases. Therefore, a high-resistance resistor element can be formed without increasing the length of the resistor element, thereby achieving high integration.

また、抵抗素子自体の厚さは最初に形成された多結晶シ
リコンの厚さのままで薄くなることばないために、強度
が低下することはなく、もって歩留り及び耐久性に優れ
た抵抗素子を形成し得る。
In addition, since the thickness of the resistor element itself remains the same as the thickness of the polycrystalline silicon that was initially formed, there is no decrease in strength, resulting in a resistor element with excellent yield and durability. It is possible.

さらに、逆導電型領域の長さ、深さ及び幅を調整するこ
とにより、抵抗素子の抵抗値を容易に制御し得る。
Furthermore, by adjusting the length, depth, and width of the opposite conductivity type region, the resistance value of the resistance element can be easily controlled.

〔実施例〕〔Example〕

次に、本発明の一実施例について、以下に説明する。第
1図(a)〜(C)は、本発明の一実施例に基づく抵抗
素子の形成工程の説明図である。
Next, one embodiment of the present invention will be described below. FIGS. 1A to 1C are explanatory diagrams of a process for forming a resistance element according to an embodiment of the present invention.

先ず、第1図(a)に示す工程を説明する。半導体の基
板1と後の工程によって形成される配線との電気的な分
離を行うために、この基板1の上面に例えばシリコン酸
化膜等の、絶縁膜2を形成し、その後、さらにこの絶縁
膜2の上面に重ねて、400人〜6000人のノンドー
プの多結晶シリコン3を積層する。
First, the process shown in FIG. 1(a) will be explained. In order to electrically isolate the semiconductor substrate 1 from wiring to be formed in a later process, an insulating film 2 such as a silicon oxide film is formed on the upper surface of the substrate 1, and then this insulating film is further removed. 400 to 6000 layers of non-doped polycrystalline silicon 3 are stacked on top of the layer 2.

そして、この多結晶シリコン3に、lXl0”〜2 X
 10 ”C11−”程度の低ドーズ量で、第1導電型
たるリン等のN型不純物イオンを注入することにより、
この多結晶シリコン3を、抵抗部である高抵抗体3Aと
する。
Then, on this polycrystalline silicon 3, lXl0''~2X
10 By implanting N-type impurity ions such as phosphorus, which is the first conductivity type, at a low dose of about "C11-",
This polycrystalline silicon 3 is used as a high resistance body 3A which is a resistance portion.

次いで、第1図(b)の工程に移り、リソグラフィー技
術により、抵抗素子を形成する領域Slに合わせてパタ
ーニングしたホトレジストを用い(図示せず)、同91
 Jet S + のマスクを行う。そして、開領域S
、以外の領域の多結晶シリコン3に、2x l Q 1
5〜5 X I Q ”am−”  程度の高ドーズ量
で、さらにリン等のN型不純物イオンを注入し、この領
域のシート抵抗を下げ、低抵抗体3Bを形成する。一方
、上記のようにマスクされた領域S、には、不純物イオ
ンが注入されることなく、同領域SIは高抵抗体3Aと
して残存する。
Next, the process moves to the step shown in FIG. 1(b), using a photoresist (not shown) patterned by lithography technology to match the region Sl in which the resistive element is to be formed.
Mask Jet S+. And open area S
, 2x l Q 1 in the polycrystalline silicon 3 in the area other than ,
Further, N-type impurity ions such as phosphorus are implanted at a high dose of about 5 to 5 X I Q "am-" to lower the sheet resistance of this region and form a low-resistance element 3B. On the other hand, impurity ions are not implanted into the region S masked as described above, and the region SI remains as the high resistance element 3A.

さらに、第1図(C)の工程に進み、高抵抗体3Aノ一
部の領域S2以外をホトレジストによりマスクして(図
示せず)、この領域S2の多結晶シリコン3に第2導電
型たる、ボロン等のP型不純物イオンが所定の深さまで
進行するように注入する。
Further, proceeding to the step shown in FIG. 1(C), areas other than a part S2 of the high-resistance element 3A are masked with photoresist (not shown), so that the polycrystalline silicon 3 in this area S2 has a second conductivity type. , P-type impurity ions such as boron are implanted to a predetermined depth.

そして、950〜1000°Cで熱処理を行い、不純物
イオンを活性化させる。
Then, heat treatment is performed at 950 to 1000°C to activate impurity ions.

このP型不純物イオンの注入によって、同領域S2は、
第2導電型領域たる逆導電型領域4となり、N型不純物
イオンが注入されている領域Slに対して接合を形成す
る。そして、この後、さらに多結晶シリコン3にホトレ
ジストをマスクして不要部分をエツチングし、高抵抗体
3Aと通導電体領域4とにより抵抗素子Rを形成し、ま
た、低抵抗体3Bにより配線Wを形成する。なお、配線
パターン等の形成は、第2導電型イオンの注入前に行っ
てもよい。
By implanting this P-type impurity ion, the region S2 becomes
This becomes an opposite conductivity type region 4 which is a second conductivity type region, and forms a junction with the region Sl into which N type impurity ions are implanted. After this, the polycrystalline silicon 3 is further masked with photoresist and unnecessary parts are etched to form a resistance element R by the high resistance element 3A and the conductive area 4, and the wiring W by the low resistance element 3B. form. Note that the formation of the wiring pattern etc. may be performed before the implantation of the second conductivity type ions.

ここで、この逆導電型領域4の厚さは、多結晶シリコン
3の厚さが4000人の場合、1000〜3000人と
するが、この深さは不純物イオンの打ち込み速度や打ち
込み時間を制御することにより調整することができる。
Here, the thickness of the opposite conductivity type region 4 is 1000 to 3000 when the thickness of the polycrystalline silicon 3 is 4000. This depth is determined by controlling the implantation speed and implantation time of impurity ions. It can be adjusted by

また、この逆導電型領域4の長さ及び幅は、ホトレジス
トのサイズを換えることにより容易に調整することがで
きる。
Further, the length and width of this opposite conductivity type region 4 can be easily adjusted by changing the size of the photoresist.

かくして、逆導電型領域4は任意の方向に電流を流して
も電流が流れ難くなり、先に形成された高抵抗体3Aは
、この逆導電型領域4の厚さ分だけ断面積が減少するた
めに、抵抗値をより高くすることかできる一方、抵抗素
子R自体の厚さは、多結晶シリコン3の厚さのままで薄
くなることはないために、強度が低下することはなく、
もって耐久性及び歩留りに優れた半導体装置を生産する
ことができる。
In this way, it becomes difficult for current to flow through the opposite conductivity type region 4 even if the current is passed in any direction, and the cross-sectional area of the previously formed high resistance body 3A is reduced by the thickness of this opposite conductivity type region 4. Therefore, the resistance value can be made higher, while the thickness of the resistance element R itself remains the same as the thickness of the polycrystalline silicon 3 and does not become thinner, so the strength does not decrease.
As a result, semiconductor devices with excellent durability and yield can be produced.

また、抵抗素子の抵抗値は、逆導電型領域4の深さ、長
さ及び幅を変化させることにより容易に制御することが
でき、容易に所望の抵抗値を設定することができる。
Further, the resistance value of the resistance element can be easily controlled by changing the depth, length, and width of the opposite conductivity type region 4, and a desired resistance value can be easily set.

なお、本実施例においては、逆導電型領域4を一箇所に
形成したが、本発明の方法はこれに限られるものではな
く、間隔をおいて複数箇所に形成してもよい。
In this embodiment, the opposite conductivity type region 4 is formed at one location, but the method of the present invention is not limited to this, and may be formed at a plurality of locations at intervals.

また、本実施例においては、先に注入する第1導電型の
不純物イオンをN型とし、後から注入する第2導電型の
不純物イオンをP型としたが、これら不純物イオンの型
を反対にして、先にP型のものを注入し、後にN型のも
のを注入することもできるのは勿論である。
Furthermore, in this example, the first conductivity type impurity ions implanted first were N type, and the second conductivity type impurity ions implanted later were P type, but the types of these impurity ions were reversed. Of course, it is also possible to implant P-type material first and then implant N-type material later.

〔発明の効果] 以上説明したように、本発明の抵抗素子の形成方法によ
っては、抵抗素子の一部に第2導電型領域を形成し通電
する抵抗部の断面積を小さくすることにより、抵抗素子
の長さを長くすることなく高抵抗の抵抗素子を得ること
ができ、高集積化を達成できる。また、抵抗素子自体の
厚さを1くする必要はないために、抵抗素子の強度が低
下することはなく、もって、耐久性に優れた抵抗素子を
形成することができる。
[Effects of the Invention] As explained above, depending on the method for forming a resistor element of the present invention, a second conductivity type region is formed in a part of the resistor element to reduce the cross-sectional area of the resistor part that conducts current. A resistive element with high resistance can be obtained without increasing the length of the element, and high integration can be achieved. Further, since it is not necessary to make the thickness of the resistive element itself equal to 1, the strength of the resistive element does not decrease, thereby making it possible to form a resistive element with excellent durability.

また、本発明によっては、反対型の不純物イオンを導入
するだけで容易に高抵抗の抵抗素子を形成することがで
きるために、抵抗素子の形成工程が単純となり歩留りよ
く抵抗素子を形成することができる。
Further, according to the present invention, a high-resistance resistor element can be easily formed simply by introducing impurity ions of the opposite type, so the process for forming the resistor element is simple, and the resistor element can be formed with high yield. can.

また、第2導電型領域の深さ、長さ及び幅を変化させる
ことにより、抵抗素子の抵抗値を容易に制御するとかで
きる効果も有する。
Furthermore, by changing the depth, length, and width of the second conductivity type region, the resistance value of the resistance element can be easily controlled.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例における抵抗素子の形成工程
の説明図である。 図中、1は基板、2は絶縁膜、3は多結晶シリコン、3
Aは高抵抗体(抵抗部)、3Bは低抵抗体、4は逆導電
型領域(第2導電型領域)である。
FIG. 1 is an explanatory diagram of a process for forming a resistance element in an embodiment of the present invention. In the figure, 1 is a substrate, 2 is an insulating film, 3 is polycrystalline silicon, 3
A is a high resistance element (resistance part), 3B is a low resistance element, and 4 is an opposite conductivity type region (second conductivity type region).

Claims (1)

【特許請求の範囲】[Claims] (1)半導体装置に抵抗素子を形成する方法において、
基板上に第1導電型の不純物イオンを導入した多結晶シ
リコンにより、抵抗素子となる抵抗部を形成する工程と
、第2導電型の不純物イオンを、前記抵抗部の少なくと
も一部の表面から所定の深さに導入して第2導電型領域
を形成する工程と、を有してなることを特徴とする半導
体装置の抵抗素子形成方法。
(1) In a method of forming a resistance element in a semiconductor device,
A step of forming a resistor section to become a resistor element using polycrystalline silicon into which impurity ions of a first conductivity type are introduced on a substrate, and a step of injecting impurity ions of a second conductivity type from at least a part of the surface of the resistor section in a predetermined direction. 1. A method for forming a resistor element in a semiconductor device, comprising the step of: forming a second conductivity type region by introducing the region to a depth of .
JP11792890A 1990-05-08 1990-05-08 Forming method for resistance element of semiconductor device Pending JPH0414863A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11792890A JPH0414863A (en) 1990-05-08 1990-05-08 Forming method for resistance element of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11792890A JPH0414863A (en) 1990-05-08 1990-05-08 Forming method for resistance element of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0414863A true JPH0414863A (en) 1992-01-20

Family

ID=14723674

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11792890A Pending JPH0414863A (en) 1990-05-08 1990-05-08 Forming method for resistance element of semiconductor device

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5389466A (en) * 1992-06-23 1995-02-14 Sumitomo Wiring Systems, Ltd. Battery terminal
WO2004093102A1 (en) * 2003-04-16 2004-10-28 Robert Bosch Gmbh Electric motor
JP2005321070A (en) * 2004-05-11 2005-11-17 Nok Corp Sealing device
US8366324B2 (en) 2006-11-22 2013-02-05 Jtekt Corporation Sealing device and rolling bearing apparatus

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5389466A (en) * 1992-06-23 1995-02-14 Sumitomo Wiring Systems, Ltd. Battery terminal
WO2004093102A1 (en) * 2003-04-16 2004-10-28 Robert Bosch Gmbh Electric motor
US7554249B2 (en) 2003-04-16 2009-06-30 Robert Bosch Gmbh Electric motor
JP2005321070A (en) * 2004-05-11 2005-11-17 Nok Corp Sealing device
US8366324B2 (en) 2006-11-22 2013-02-05 Jtekt Corporation Sealing device and rolling bearing apparatus

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