JPH04148342A - Diagnostic system for data processing equipment - Google Patents

Abstract

PURPOSE:To easily detect the double select state of a module, and the state in which a driver output is equal to '0' by providing a means which issues the first and second test commands for a module diagnosis, and a test selecting means and a test output data preparing means at each module. CONSTITUTION:This system is equipped with a means 80 which issues the first and second test commands, and a test selecting means 54 which outputs the first and second test signals to each module. Also a means 523 which forcedly inhibits data output from its own module when the first test signal indicates a true value, and a test output data preparing means which prepares output data of a prescribed width which has only a specific bit assigned to its own module when the second test signal shows the true value are installed. Then, the diagnosis of the module is operated based on the output data from each module at the time of the execution of the test command. Thus, the double select state of the module and a gate fault at prestate of the driver can be easily detected.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention is suitable for identifying a failure location in a data processing device that includes a plurality of modules that are selected and operated by an address selection circuit. Regarding diagnostic methods.

(Prior Art) Generally, in data processing equipment such as an electronic computer, various modules 1 such as memory and input/output devices are used as shown in FIG.
0-1.10-2.10-3... is the connection means 20-1
．． 20-2, 20-3, . . . are connected to a CPU 40 serving as a control center via a bus 30.

In the computer shown in FIG. 2, when a module, for example module 10-1, operates, this module 10-
1 and the CPU 40 are connected via a bus 30 and a connecting means 20-1. Through this route, various commands and data are exchanged according to the procedures necessary for operation.

Now, in order to operate module 10-1, it is necessary to select module 10-1. Therefore, the module 10-1 includes an address selection circuit (AS) for selecting the module 10-1 according to instructions from CF2O.
) 11 are provided. The CPU 40 sends a command (address selection command) ill for module selection and addresses (address data) 112 to 113 specifying the module 1O-1 to the module 10-1. Address selection circuit 11 decodes addresses 112 to 113 according to command 111, and if it is equal to its own address (address of module 10-1),
A signal 114 indicating the "selected state" is output to the control unit 12 of the module 10-1. The control unit 12 receives the signal 114 and executes a series of operating procedures. Other module 10-
2. Address selection circuit (not shown) also in 10-3...
is provided, and this address selection circuit also has CPU4
Command 111 and addresses 112-113 from 0
is supplied. However, as mentioned above, addresses 112~
113, the address selection circuits in the modules 10-2, 10-3, etc. do not output a signal indicating the "selected state", and the module I0-2. 10-3... does not work.

If module 1O-1 is selected, module 10
-1 to the CPU 40 is normally performed through bus drivers (D) 131-132.

For these drivers 131 to 132, data signals from the final stage gates (G) 121 to 122 of the control unit 2 and a driver enable/disable signal 138 for permitting/prohibiting the output of the drivers 131 to 132 are transmitted. It is connected.

This signal 133 has a true value in the normal operating state, but it becomes a false value when the module to-1 fails (is detected) or when the power is turned on/off, and the bus 3
This is used to prevent a false signal from being output as 0.

(Address selection circuit LL of the above module 10-■)
The bus interface configuration of drivers 131 to 132, etc. is the same for other modules 10-2, 10-3, and so on.

As described above, in the computer shown in FIG. 2, the reason why only one of the many modules responds in accordance with the operation command issued by the CPU is due to the selection operation of the address selection circuit described above. Further, protection for preventing erroneous signals inside the module from being sent to the bus is provided by driver enable/disable signals.

(Problem to be Solved by the Invention) As described above, in data processing equipment such as an electronic computer having multiple modules, in response to an operation request from the CPU, the address selection circuit provided in the module operates. Generally, only the specified module is selected and starts operating. However, if an address selection circuit within a module malfunctions, that module will also be selected and a plurality of modules will start operating at the same time. If a module does not respond to an operation start request from the CPU, it can be easily determined that the module is in an abnormal state. However, when a plurality of modules are selected (double-selected) and operated due to malfunction of the address selection circuit as described above, it is difficult to even determine that double-select has occurred because a complex abnormal state is exhibited. Even if Yoshiba can determine that a double select has occurred, it is extremely difficult for conventional computers to identify which module is in a double select state.

Furthermore, if a failure mode occurs in which the output of the gates in the front stage of the bus driver, such as the gates 121 and 122 shown in FIG.
The driver enable/M stop signal that controls the driver is normally “
1°) is fixed at 0°.In this way, even if the output of other modules changes, the signal line on the bus corresponding to the position of the driver's bit is forced to always be 0°. ”. This is a failure mode that makes the entire system inoperable.Therefore, there is no point in making the modules redundant.Furthermore, since the entire system becomes inoperable, conventional computers cannot detect the location of the failure. The failure was difficult to identify and difficult to handle.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a diagnostic method for data processing equipment that can easily detect the double-select state of a module and a gate failure in the front stage of a driver.

[Configuration of the Invention (Means for Solving the Problem) This invention provides a test that issues a first test command and a second test command for diagnosing a module in a data processing device selected by addressing. A command issuing means is provided in the data processing equipment, and each module in the data processing equipment determines the test command issued from the command issuing means when the module itself is selected, and if it is the first test command, the first test command is determined. a test selection means that outputs a first test signal and outputs a second test signal if it is a second test command; and a test selection means that outputs data from its own module when the first test signal takes a true value. a driver control means for forcibly prohibiting the output of the driver group to be performed, and an output of a predetermined width in which only specific bits assigned to the own module are set to the true value when the second test signal takes a true value. The present invention is characterized in that a test output data generation means for generating data is provided, and the module is diagnosed based on the output data from each module when the above test command is executed.

(Function) In the above configuration, when a module in the data processing equipment is selected and the first test command is issued, the first test signal is output from the test selection means in the module, and this causes the self-module to output the first test signal. The output of the driver group that outputs data is forcibly prohibited by the driver control means.

As a result, the gate in front of the driver in the module being tested by the first test command malfunctions.
If the signal line on the bus corresponding to the output bit position of the driver is always forced to be at "0°", the "0" level signal on the bus will be set to "0" by executing the test using the first test command. Since it disappears, it can be determined that the module to be tested is abnormal (gate abnormality).

Furthermore, when a module in the data processing equipment is selected and a second test command is issued, the second test signal is output from the test selection means in the module, and this causes only the specific bits assigned to the own module to be output. Output data of a predetermined width in which is set to the true value is generated by the test output data generation means and sent to the bus by the driver group. At this time, if it is assumed that another module that is not the test target is also in a double-select state where it has been erroneously selected, the test selection means operates also in this erroneously selected module and the second test signal is output. is output, and output data of a predetermined width in which only specific bits assigned to the module are set to true values is generated and output. Therefore, if the bit position that takes the true value is set in advance to be different for each module, the data output from each module in the double-select state by the test execution using the second test command will be synthesized on the bus. The double select state can be determined from the fact that a plurality of bits take the true value. In addition, a module that has been incorrectly selected can also be identified from the bit position that takes a true value.

(Embodiment) FIG. 1 is a block diagram showing an embodiment of a module configuration inside a computer to which the present invention is applied.

In FIG. 1, 50-1 is a module such as a memory and an input/output device connected to a CPU 80 to be described later by a bus 70, and 51 is an address selection circuit of the module 50-1 (
AS), 511 is an address selection command for module selection from the CPU 80 (actually, a signal line that takes a true value in response to the address selection command), 512 to 5
13 is an address (address data) sent from the CPU 80 for specifying the module to be selected.

Here, 512 is the most significant address bit and 513 is the least significant address bit. 514 is the address “selected!!J” (module 5
This signal notifies the control unit 52 of the selected state (0-1), and is output from the address selection circuit 51.

52 is a control unit that controls the operation procedure of the module 10-1, and 521 and 522 are units from the module 50-1 to the CPU 80.
These gates (G) pass the most significant bit (bit 0) to the least significant bit (bit 31) of, for example, 32 bits of data sent to the gate. 523 is a driver 531 which will be described later.
A driver control circuit (DC) that controls permission/inhibition of the output of ~532, 524 is bit data at a specific bit position previously assigned to module 1O-1 in a specific test mode (here, test 2). In order to set only the true value to the true value and send it to the bus 70, the gates 521 to 522
This is a test output data generation circuit (TG) that gives true values only to corresponding gates.

531 to 532 are connected from the module 10-1 to the bus 70 (C
This bus driver (D) sends bit 0 (most significant bit) to bit 31 (least significant bit) of 32-bit data to the PU 80).

533 is a signal (driver permission/prohibition signal) for permitting/prohibiting the output of the drivers 531 to 532. The driver permission/prohibition signal 533 is output from the driver control circuit 523, and is normally in the true value (permission) state, and of course in the test 2 state (when the test 1 signal 542 is the true value) at the time of module failure or power on/off. ), it becomes a false value (prohibited) state.

54 is a test 1 for detecting an abnormal module due to a failure of a gate in the front stage of the driver when a test command 541 is received from the CPU 80 when the signal 514 indicating the "selected state" from the address selection circuit 51 takes a true value; Alternatively, it is a test selection circuit (TS) that determines which test 2 is specified for detecting a module in a double-select state and outputs the corresponding test signal (test 1 signal 542 or test 2 signal 543). .

541 is a test command specifying test 1 or test 2; 542 is set as a true value by the test selection circuit 54 when the test command 541 specifies test 1;
When the test command 541 specifies test 2, a signal (test 1 signal) 543 that provides a condition for inhibiting the output of 532 is set as a true value by the test selection circuit 54 and sent to the test output data generation circuit 524. This is a signal (test 2 signal) requesting generation and output of a specific bit.

50-2, 50-3, . . . are modules for memories, input/output devices, etc., similar to the module 50-1. Although the modules 50-2, 50-3, etc. do not necessarily have the same configuration as the module 50-1, they include the address selection circuit 51 in the module 50-1 and the gates 521 to 522 in the control section 52 shown in FIG. , the driver control circuit 523, the test output data generation circuit 524, and the drivers 531-
532 and the test selection circuit 54 are included in the same way as the module 50-1. In FIG. 1, these configurations in the modules 50-2, 50-3... are omitted, but from now on, the modules 50-2, 50-3...
... will also be explained as having these configurations.

60-1. Go-2, 60-3... is module 5
0-1.50-2°50-3... and the bus 70 of the CPU 80. Connection means 60
-1.60-2. Go-3... is module 50
-1.50-2.50-3... is a connector when it consists of a single printed circuit board circuit, and is often a signal cable when it is large enough to be an independent device. . 70 is CPUll0 and module 50-
A bus used for input/output between 1.50-2.50-3, etc., 80 is C which forms the control center of the computer in Fig. 1.
It is PU.

Next, the operation of the configuration shown in FIG. 1 will be described using an example in which the CPU 80 executes test 1 and test 2. .

(a) Operation of Test 1 If the CPU 80 predicts that some module (driver of the module) in the computer is always outputting a "0" level signal to the bus 70, each module 50- 1
．． 50-2, 50-3..., for example, test 1 is executed in order from modules 50 to 1.

As an example, it is assumed that the output of the gate 121 (for outputting the most significant bit) of the module 50-1, which is the target of test 1, always takes a true value.

During normal operation, the driver control circuit 523 sets the driver permission/inhibition signal 533 to a true value (permitted state).

Therefore, when the output of the gate 521 is always the true value as in this embodiment, the output of the driver 531 (bit 0 output) is always at the "0" level, and the signal line at the corresponding bit position on the bus 70 is also Always “0”.

When executing test 1 on the module 50-1 in this state, the CPU 80 first sends the address selection command 511 for module selection and the module 50-1.
Addresses 512 to 513 specifying -1 are sent to module 50-1 via bus 70. Module 50-
The address selection circuit 51 in 1 decodes the addresses 512 to 513 in response to the command 511, and if it is equal to its own address (the address of the module 50-1) as in this embodiment, it indicates a "selected state". A signal 514 is output to the control section 52 of the module 50-1. This means that module 50-1 has been selected. This signal 5
14 is also output to the test selection circuit 54.

Next, the CPU 80 sends a test command 541 specifying test 1 to the module 50-1 via the bus 70. The test selection circuit 54 in the module 50-1 receives a signal 51 indicating the “selected state” from the address selection circuit 51.
4 takes a true value, that is, when the own module 50-1 is in the "selected state", when a test command 541 is received from the CPU 80, it is determined whether the test command 541 is a test 1 command or a test 2 command. , in the case of the test 1 command as in this embodiment, the test 1 signal 54
Let 2 be the true value. This test 1 signal 542 is guided to the driver control circuit 523. The driver control circuit 523 is
If the test 1 signal 542 from the test selection circuit 54 is a true value, the enable/prohibit signal 533 is forcibly set to a false value (“0′) in order to prohibit the output of the drivers 531 to 532. As a result, the driver The output of 531-532 is gate 5
It becomes "1" regardless of the state of the outputs 21 to 522, and the O" level signal on the bus 70 disappears. CPUll0
When detecting that the "0" level on the bus 70 is no longer reliable by executing test 1 on the module 50-1, it is confirmed that the module 50-1 is abnormal. , the CPU 80 is connected to the module 50-
Disconnect from the first system and perform alternative processing.

(b) Operation of test 2 The CPU 80 selects each module 50-1.50-2.50-3... if there is a possibility of a double-select state in which multiple modules are operating. Test 2 will be executed in order.

As an example, assume that the first module 50-1 and the third module 50-3 are double-selected. Here, it is assumed that the cause is that the address selection circuit 51 of the module 50-3 is not functioning properly and cannot distinguish between its own address and the address of the module 50-1.

The CPU 80 first performs processing for selecting the module 50-1 to be executed in the test 2, as in the case of executing the test 1 described above. This allows module 50
-1 address selection circuit 5] operates and module 5
0-1 is selected, but at the same time, the test selection circuit (54) in module 50-3 mistakenly performs a selection operation, and module 50-3 is also selected.

The CPU 80 is the module 50 that is the target of test 2.
When -1 is selected, a test command 541 specifying test 2 is sent to module 50-1 via bus 70. If the test command 541 from the CPU l1l[l is the test 2 command as in this embodiment, the test selection circuit 54 in the module 50-1 in the "selected state" sets the test 2 signal 543 to the true value. .

This test 2 signal 543 is the test output data generation circuit 5
Guided by 24. The test output data generation circuit 524 is
When the test 2 signal 543 from the test selection circuit 54 is a true value, among the 32 bits of data, the module 50-I
A signal whose true value is the bit data of a specific bit position previously assigned to is output. In this embodiment, the bit O is set in the modules 50-1, 50-2, 50-3, . . . starting from the module 50-1.

Bit 1. It is assumed that bit 3... has been allocated in advance. Therefore, in module 50-1,
By specifying test 2 from the CPU 80, 32-bit data “1000.
...000' is gates 521-522, driver 531
~532 to the bus 70.

At this time, module 50-3 is also erroneously selected as described above. Therefore, when the test command 541 specifying test 2 is sent from the CPU 80 to the module 50-1, the test selection circuit (54) in the module 50-3 also performs the test selection operation, and the test 2 signal (541) is sent to the module 50-1.
43) is the true value. This test 2 signal (543) is the test output data generation circuit (52) in the module 50-3.
4). When the test 2 signal (543) from the test selection circuit (54) is a true value, the test output data generation circuit (524) in the module 50-3 assigns the 32-bit data to the module 50-3 in advance. A signal having only bit 2 (the third bit from the most significant bit) as the true value is output. As a result, 32-bit data '0010...000' in which only bit 2 is the true value is sent to the bus 70 from the erroneously selected module 50-3.

Now, on the bus 70, the output data "1000...000" from the module 50-1 and the output data "1000...000" from the module 50-1 are transmitted.
As a result of the output data "0010...000" from 3 appearing at the same time, 3 in the form "1010...000"
2-bit data is obtained. CPU80 uses this bus 7
From the bit position that takes the true value in the data pattern above 0,
It can be recognized that the module 50-1 to which bit 0 is assigned and the module 50-3 to which bit 2 is assigned are in a double-select state. Furthermore, the CPU 80 selects and specifies the module 50-1 since the result is the test 2 with the module 50-1 selected and specified.
It can also be recognized that the address selection circuit (51) No. 3 is abnormal.

In this way, it is possible to analyze the abnormal state of the module in the computer shown in FIG.

In the above embodiment, the case where the present invention is applied to the diagnosis of an electronic computer has been described, but the present invention can also be applied to electronic devices in general such as microprocessor application products.

Moreover, the same application is possible even if the connection between the CPU and each module is not a bus type.

[Effects of the Invention] As detailed above, according to the present invention, the data processing device is provided with a test command issuing means for issuing the first and second test commands for module diagnosis, and the Each module includes a test selection means for determining a test command issued by the command issuing means and selecting a test mode when the module itself is selected, and a first test mode specified by the first test command. is selected, a means for forcibly prohibiting the output of the driver group that outputs data from the own module, and a means for forcibly prohibiting the output of the driver group that outputs data from the own module when the second test mode specified by the second test command is selected. A means for generating output data of a predetermined width in which only specific bits assigned to the test command are set to true values is provided, and the module is configured to be diagnosed based on the output data from each module when a test command is executed. Therefore, the "double select" state, which makes failure analysis difficult, and the "driver output - "0" (gate failure in the front stage of the driver)" state are the first state for each module.
．． It can be easily detected by testing using the second test command. Moreover, the failure location can be identified without stopping the system, and the performance of the system in terms of MTBF (mean time between failures) and MTTR (mean time to repair) is improved.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing one embodiment of a module configuration inside a computer to which the present invention is applied, and FIG. 2 is a block diagram showing a conventional example. 50-1.50-2 50-3...Module, 51
. . . address selection circuit (AS), 52 . . . control unit,
54...Test selection circuit (TS) 60-1.
60-2.60-3... Connection means, 70... Bus,
80...CPU (command issuing means), 521-5
22...Gate (G) 523...Driver control circuit (DC) 524...Test output data generation circuit (TG) 531-532...Driver (
D), 541...Test command, 542...Test 1 signal,...Test 2 signal.

Claims (1)

[Scope of Claims] A data processing device equipped with a plurality of modules selected by addressing, comprising test command issuing means for issuing a first test command and a second test command for diagnosing the module; Provided in each of the above modules, when the module itself is selected, determines the test command issued by the above command issuing means, outputs the first test signal if the above first test command is the above, and outputs the first test signal when the above second test command is selected.
test selection means that outputs a second test signal if the test command is, and forcibly inhibits the output of the driver group that outputs data from its own module when the first test signal takes a true value. and test output data generation means for generating output data of a predetermined width in which only specific bits assigned to the module itself are set to true values when the second test signal takes a true value. A diagnostic method for a data processing device, characterized in that the module is diagnosed based on output data from each of the modules when the test command is executed.