JPH04144248A - Testing method of semiconductor integrated circuit - Google Patents
Testing method of semiconductor integrated circuitInfo
- Publication number
- JPH04144248A JPH04144248A JP2268957A JP26895790A JPH04144248A JP H04144248 A JPH04144248 A JP H04144248A JP 2268957 A JP2268957 A JP 2268957A JP 26895790 A JP26895790 A JP 26895790A JP H04144248 A JPH04144248 A JP H04144248A
- Authority
- JP
- Japan
- Prior art keywords
- temperature
- semiconductor integrated
- integrated circuit
- tester
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 24
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 230000005679 Peltier effect Effects 0.000 claims abstract description 4
- 238000010438 heat treatment Methods 0.000 claims description 4
- 238000010998 test method Methods 0.000 claims description 4
- 238000004904 shortening Methods 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 abstract 1
- 239000002184 metal Substances 0.000 description 10
- 238000010586 diagram Methods 0.000 description 7
- 238000001514 detection method Methods 0.000 description 4
- 238000001816 cooling Methods 0.000 description 3
- 230000020169 heat generation Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路の電気的特性の試験方法に関し
、特に高電力である半導体集積回路を冷却する試験方法
に間する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for testing the electrical characteristics of a semiconductor integrated circuit, and particularly to a test method for cooling a high-power semiconductor integrated circuit.
従来、高電力でありT A B (Tape Aut
omatedBonding)状態で出荷をする半導体
集積回路(以下、ICと称す)の自己発熱を、ペルチェ
効果を有する半導体素子(以下、ペルチェ素子と称す)
により吸収して試験を行う場合、ICの自己発熱を外部
の温度センサーにより検出し、この検出地を元にペルチ
ェ素子の温度コントロールを行いICを適切な試験環境
下にて試験を行っていた。Conventionally, high power and T A B (Tape Out
The self-heating of semiconductor integrated circuits (hereinafter referred to as ICs) that are shipped in a bonded state is reduced by a semiconductor element having a Peltier effect (hereinafter referred to as a Peltier element).
When testing the IC by absorbing it, the self-heating of the IC is detected by an external temperature sensor, the temperature of the Peltier element is controlled based on this detection point, and the IC is tested in an appropriate test environment.
第3図に、ペルチェ素子を用いてICを冷却して電気的
特性試験を行う一例の試験装置の概略ブロック図を示す
。FIG. 3 shows a schematic block diagram of an example of a test device that cools an IC using a Peltier element and tests electrical characteristics.
熱伝導の優れた金属ブロック上にペルチェ素子3を接着
し、金属ブロックの下側に被試験IC6内のICチップ
7密着させる。金属ブロック内のICチップにより近い
位置に温度センサー5を埋め込み、試験中のICチップ
7の温度を計測し、その計測値を温度制御部2にて規定
の出力に変換し、ペルチェ素子3の出力をコントロール
し、ICチップ7の温度を一定に保とうとする。The Peltier element 3 is adhered onto a metal block with excellent thermal conductivity, and the IC chip 7 in the IC 6 to be tested is brought into close contact with the lower side of the metal block. A temperature sensor 5 is embedded in the metal block at a position closer to the IC chip, measures the temperature of the IC chip 7 under test, converts the measured value into a specified output in the temperature control section 2, and outputs the Peltier element 3. and tries to keep the temperature of the IC chip 7 constant.
しかしなから、ICチップ7の発熱はICの電源電圧を
印加する事により、急激に上昇するが、ペルチェ素子3
は、ICチップ7の発熱を受けて金属ブロック4の温度
が上昇した段階で始めて金属ブロック4内の温度センサ
5が検出した温度を設定温度に下げるように働く為、こ
こに遅延時間が生じる。However, the heat generation of the IC chip 7 increases rapidly when the IC power supply voltage is applied, but the Peltier element 3
Since the function starts to lower the temperature detected by the temperature sensor 5 in the metal block 4 to the set temperature only when the temperature of the metal block 4 rises due to the heat generated by the IC chip 7, a delay time occurs.
また、ペルチェ素子3が、設定温度に下げるように出力
を開始してからも、ペルチェ素子3とICチップ7間の
金属ブロック4の熱伝達時間が生ずる為、第4図の熱応
答特性に示すように、ICチップが設定温度に達するま
では、ある一定の時間が必要となる。Furthermore, even after the Peltier element 3 starts outputting to lower the temperature to the set temperature, there is a time period for heat transfer in the metal block 4 between the Peltier element 3 and the IC chip 7, as shown in the thermal response characteristics in Figure 4. As such, a certain amount of time is required for the IC chip to reach the set temperature.
従って上述した従来の半導体集積回路の電気的特性試験
方法では、ある一定の温度範囲内で保証された各スペッ
ク〈性能)をテストする為、ICのPOWERON後、
設定温度範囲内に入るまではテストを開始できないとい
う制約があった。Therefore, in the conventional electrical characteristic testing method for semiconductor integrated circuits described above, in order to test each guaranteed specification (performance) within a certain temperature range, after the IC is powered on,
There was a restriction that the test could not be started until the temperature was within the set temperature range.
また、ICの設定温度範囲外にてテストを開始したとし
ても、微視的には設定温度範囲内に入るまでの試験を保
証できないという欠点もあった。Another drawback is that even if the test is started outside the set temperature range of the IC, it cannot be guaranteed that the test will continue until the temperature microscopically falls within the set temperature range.
本発明による半導体集積回路の試験方法は、ICが通電
されて発熱を開始してからそのICの温度変化を温度セ
ンサーが検出するまでの時間と、これを受けてペルチェ
素子が設定温度に下げる為に出力を開始してからICが
設定温度範囲内に冷却されるまでの遅延時間を、ICテ
スタからペルチェ素子の温度を制御する信号を事前に印
加して短縮する手段を有している。The test method for semiconductor integrated circuits according to the present invention is based on the time from when an IC is energized and starts generating heat until a temperature sensor detects a change in temperature of the IC, and the time when a Peltier element lowers the temperature to a set temperature in response to this. The device has means for shortening the delay time from when the IC starts outputting until the IC is cooled to within a set temperature range by applying in advance a signal from the IC tester to control the temperature of the Peltier element.
以下、本発明の実施例について図面を参照して説明する
。Embodiments of the present invention will be described below with reference to the drawings.
第1図に本発明の第1の実施例を説明するための試験装
置の概略ブロック図を示す。FIG. 1 shows a schematic block diagram of a test device for explaining a first embodiment of the present invention.
熱伝導の優れた金属ブロック上にペルチェ素子を接着し
、金属ブロックの下側に被試験IC内のICチップ7を
密着させる。A Peltier element is bonded onto a metal block with excellent thermal conductivity, and the IC chip 7 in the IC to be tested is brought into close contact with the underside of the metal block.
金属ブロック内のICチップ7により近い位置に温度セ
ンサ5を埋め込み、試験中のICチップ7の温度を計測
しその計測値を温度制御部2にて規定の出力に変換し、
ペルチェ素子3の出力をコントロールし、試験中のIC
チップ7の温度を一定に保つ。A temperature sensor 5 is embedded in the metal block at a position closer to the IC chip 7, the temperature of the IC chip 7 under test is measured, and the measured value is converted into a specified output by the temperature control unit 2,
Controls the output of Peltier element 3 and controls the IC under test.
Keep the temperature of chip 7 constant.
テスタ信号線9にて、既知の熱応答特性より求めたデー
タを基にICの電源電圧○N以前にペルチェ素子3をコ
ントロールする為の信号をICテスタ1より温度制御部
2へ印加する。On the tester signal line 9, a signal for controlling the Peltier element 3 is applied from the IC tester 1 to the temperature control section 2 before the power supply voltage ○N of the IC is applied based on data obtained from known thermal response characteristics.
この信号は、ICテスタ1のテスタビンを用いることに
よりテストプログラムにて制御する事が可能であり、各
IC6の出力により自由に制御する事ができる。This signal can be controlled by a test program using the tester bin of the IC tester 1, and can be freely controlled by the output of each IC 6.
テスタ1の出力信号は、IC6のP OWE RON後
、IC6の発熱がある一定のレベルまで達する時間、即
ち、第4図のAの時間にて中断し、その後は従来通り温
度センサ5の検出温度によりペルチェ素子3を制御する
。The output signal of the tester 1 is interrupted at the time when the heat generation of the IC 6 reaches a certain level after the P OWE RON of the IC 6, that is, at the time A in FIG. The Peltier element 3 is controlled by.
第3図は、本発明の第2の実施例を説明するための試験
装置の概略ブロック図である。FIG. 3 is a schematic block diagram of a test device for explaining a second embodiment of the present invention.
第1の実施例では、ICテスタ1からの温度制御用の信
号を、温度センサ5の検出信号に直接印加して、テスト
プログラムにて制御していたのに対し、本実施例ではI
Cテスタ1からの温度制御用の信号と、温度センサ5の
検出信号の接続を入力信号切換スイッチ10にて行い、
この入力信号切換スイッチをタイマ11にて制御する。In the first embodiment, the temperature control signal from the IC tester 1 was directly applied to the detection signal of the temperature sensor 5, and the test program was used for control.
The temperature control signal from the C tester 1 and the detection signal of the temperature sensor 5 are connected by the input signal changeover switch 10.
This input signal changeover switch is controlled by a timer 11.
つまり、テストプラグラムでは温度制御用の信号の入力
タイミングのみを制御し、温度センサ5の検出信号との
切換は、タイマ11にて設定された時間で強制的に実行
される。That is, the test program controls only the input timing of the temperature control signal, and the switching with the detection signal of the temperature sensor 5 is forcibly executed at the time set by the timer 11.
以上説明したように本発明は、高電力である半導体集積
回路の電気的特性試験に於いて試験中に発生する半導体
集積回路の自己発熱をペルチェ効果を有する半導体素子
により吸収して試験を行う時に、半導体集積回路の電源
電圧をONする以前に、予備冷却を施す事により、従来
、ICの温度が設定温度範囲内に下がるまでテストをて
きなかった熱遅延時間を大幅に短縮する事が可能となる
。As explained above, the present invention is capable of absorbing the self-heating of the semiconductor integrated circuit generated during the test by using a semiconductor element having a Peltier effect during the electrical characteristic test of a semiconductor integrated circuit that requires high power. By pre-cooling the semiconductor integrated circuit before turning on the power supply voltage, it is possible to significantly shorten the thermal delay time, which was conventionally not tested until the IC temperature fell within the set temperature range. Become.
第1図は、本発明の第1の実施例を説明するための試験
装置の概略ブロック図、第2図は本発明の第2の実施例
を説明するための試験装置の概略ブロック図、第3図は
従来の半導体集積回路の試験方法の一例を説明するため
の試験装置の概略ブロック図、第4図はペルチェ素子を
用いてICの冷却を行った時の温度センサの検出温度の
熱応答特性図である。
1・・・ICテスタ、2・・・温度制御部、3・・・ペ
ルチェ素子、4・・・金属ブロック、5・・・温度セン
サ、6・・・IC17・・・ICチップ、8・・・接続
器、9・・・テスタ信号線、10・・・入力信号切換ス
イッチ、1]・・・タイマ。FIG. 1 is a schematic block diagram of a test device for explaining a first embodiment of the present invention, and FIG. 2 is a schematic block diagram of a test device for explaining a second embodiment of the present invention. Figure 3 is a schematic block diagram of a test device for explaining an example of a conventional semiconductor integrated circuit testing method, and Figure 4 shows the thermal response of the temperature detected by the temperature sensor when cooling an IC using a Peltier element. It is a characteristic diagram. DESCRIPTION OF SYMBOLS 1... IC tester, 2... Temperature control part, 3... Peltier element, 4... Metal block, 5... Temperature sensor, 6... IC17... IC chip, 8...・Connector, 9...Tester signal line, 10...Input signal selection switch, 1]...Timer.
Claims (1)
ェ効果を有する半導体素子により吸収してICテスタに
より試験を行う半導体集積回路の試験方法において、前
記半導体集積回路が発熱を開始してからその半導体集積
回路の温度変化を温度センサが検出するまでの時間と、
これを受けてペルチェ素子が設定温度に下げる為に出力
を開始してから前記半導体集積回路が設定温度範囲内に
冷却されるまでの遅延時間を、前記ICテスタから前記
ペルチェ素子の温度を制御する信号を事前に印加する事
により短縮する手段を有する半導体集積回路の試験方法
。In a test method for a semiconductor integrated circuit in which self-heating of a semiconductor integrated circuit generated during the test is absorbed by a semiconductor element having a Peltier effect and tested by an IC tester, the semiconductor integrated circuit is tested after the semiconductor integrated circuit starts generating heat. The time it takes for the temperature sensor to detect a temperature change in the circuit,
In response to this, the IC tester controls the temperature of the Peltier element by controlling the delay time from when the Peltier element starts outputting to lower the temperature to the set temperature until the semiconductor integrated circuit is cooled to within the set temperature range. A test method for semiconductor integrated circuits that has a means of shortening the time by applying a signal in advance.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2268957A JPH04144248A (en) | 1990-10-05 | 1990-10-05 | Testing method of semiconductor integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2268957A JPH04144248A (en) | 1990-10-05 | 1990-10-05 | Testing method of semiconductor integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04144248A true JPH04144248A (en) | 1992-05-18 |
Family
ID=17465651
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2268957A Pending JPH04144248A (en) | 1990-10-05 | 1990-10-05 | Testing method of semiconductor integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04144248A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100414301B1 (en) * | 1996-07-10 | 2004-03-30 | 주식회사 하이닉스반도체 | Temperature suction guide of semiconductor device inspection equipment |
JP2020122707A (en) * | 2019-01-30 | 2020-08-13 | 株式会社アドバンテスト | Electronic component handling device and electronic component tester |
JP2020122706A (en) * | 2019-01-30 | 2020-08-13 | 株式会社アドバンテスト | Electronic component handling device and electronic component tester |
CN112824916A (en) * | 2019-11-20 | 2021-05-21 | 圣邦微电子(北京)股份有限公司 | High-temperature testing device and method for integrated chip |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5350982A (en) * | 1976-10-20 | 1978-05-09 | Mitsubishi Electric Corp | Low-high temperature testing station |
JPS5690583A (en) * | 1979-12-21 | 1981-07-22 | Ricoh Co Ltd | Stabilizing device of output for semiconductor laser |
JPS63109174A (en) * | 1986-10-24 | 1988-05-13 | Hitachi Ltd | Sheet-fed cvd device |
JPH01286322A (en) * | 1988-05-12 | 1989-11-17 | Nec Corp | Test method for semiconductor integrated circuit |
-
1990
- 1990-10-05 JP JP2268957A patent/JPH04144248A/en active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5350982A (en) * | 1976-10-20 | 1978-05-09 | Mitsubishi Electric Corp | Low-high temperature testing station |
JPS5690583A (en) * | 1979-12-21 | 1981-07-22 | Ricoh Co Ltd | Stabilizing device of output for semiconductor laser |
JPS63109174A (en) * | 1986-10-24 | 1988-05-13 | Hitachi Ltd | Sheet-fed cvd device |
JPH01286322A (en) * | 1988-05-12 | 1989-11-17 | Nec Corp | Test method for semiconductor integrated circuit |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100414301B1 (en) * | 1996-07-10 | 2004-03-30 | 주식회사 하이닉스반도체 | Temperature suction guide of semiconductor device inspection equipment |
JP2020122707A (en) * | 2019-01-30 | 2020-08-13 | 株式会社アドバンテスト | Electronic component handling device and electronic component tester |
JP2020122706A (en) * | 2019-01-30 | 2020-08-13 | 株式会社アドバンテスト | Electronic component handling device and electronic component tester |
CN112824916A (en) * | 2019-11-20 | 2021-05-21 | 圣邦微电子(北京)股份有限公司 | High-temperature testing device and method for integrated chip |
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