JPH04144139A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form larger particle size, high crystallization polycrystalline silicon with excellent responsibility by forming a polycrystalline semiconductor layer containing silicon as a chief ingredient on an insulating amorphous material and raising the temperature of at least the polycrystalline semiconductor layer to a predetermined temperature higher than the highest temperature in the process. CONSTITUTION:A polycrystalline silicon layer 102 is formed on an insulating amorphous material 101 composed of an insulating amorphous substrate such as glass amorphous material layer such as SiO2. The polycrystalline silicon layer 102 is heat-treated at a predetermined temperature higher than that in the above process. The optimum heat-treatment temperature ranges in a region 700 deg.C-1200 deg.C. Then, after the polycrystalline silicon layer 102 is patterned into a predetermined shape, a gate insulating film 103 is formed. Further, there are formed a gate electrode 105, an interlayer insulating film film 106, a contact hole 107, and a wiring 104.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor element on an insulating amorphous material.

[Prior Art] Attempts have been made to form high-performance semiconductor elements on insulating amorphous substrates such as glass and quartz, and insulating amorphous layers such as 5i02.

In recent years, as the need for large, high-resolution liquid crystal display panels, high-speed, high-resolution contact-type image sensors, and three-dimensional ICs has increased, high-performance semiconductor devices on insulating amorphous materials such as those mentioned above are becoming increasingly popular. The realization of this is eagerly awaited.

Taking the case of forming a thin film transistor (TPT) on an insulating amorphous material as an example, (1) TPT whose element material is amorphous silicon formed by plasma CVD method, etc.
2) TPT whose element material is polycrystalline silicon formed by a CVD method, etc., (3) TPT whose element material is made of single crystal silicon formed by a melt recrystallization method, etc. are being considered.

However, among these TPTs, TPTs made of amorphous silicon or polycrystalline silicon have a significantly higher field effect mobility than those made of single crystal silicon. Quality silicon TFT < 1
cm2/V-sec, polycrystalline silicon TFT
~10cm2/v-5ec), it was difficult to realize a high-performance TPT.

On the other hand, the melting and recrystallization method using laser beams, etc. is still not a fully developed technology, and it also poses technical difficulties when it is necessary to form elements over a large area, such as in liquid crystal display panels. Especially big.

Therefore, as a simple and practical method for forming high-performance semiconductor elements on insulating amorphous materials, a method of solid-phase growth of large-grain polycrystalline silicon at low temperatures has attracted attention, and research is progressing. There is. (ThinSolid Film
s 100 (1983) P, 227, JJAP
Vol, 25N.

, 2 (1986) p. L121) [Problems to be Solved by the Invention] However, in the conventional solid phase growth method, poly-Si with large grain size and high crystallinity can be grown in a low temperature process of about 650°C or less.
It has been difficult to form a high-performance TPT whose field effect mobility exceeds 100 cm 2 /V·S.

Therefore, the present invention uses a simpler and more practical method to form polycrystalline silicon with large grain size and high crystallinity with good reproducibility.
The present invention provides a method for manufacturing high-performance semiconductor devices.

[Means for Solving the Problems] A method for manufacturing a semiconductor device of the present invention includes: (a) forming a polycrystalline semiconductor layer mainly composed of silicon on an insulating amorphous material; (b) step (a) ) is characterized in that it includes at least the step of raising the temperature of at least the polycrystalline semiconductor layer to a predetermined temperature higher than the maximum process temperature of ().

2) The predetermined temperature in step (b) is 700°C to 1200°C.
It is characterized by being ℃.

3) It is characterized in that the heat treatment in step (b) was performed using an excimer laser.

(a) Step of forming a polycrystalline semiconductor layer mainly composed of silicon on an insulating amorphous material; (b) A semiconductor region doped with impurities in or in contact with the polycrystalline semiconductor layer. (c) is characterized by at least the step of heating at least the polycrystalline semiconductor layer and the impurity-doped semiconductor region to a predetermined temperature higher than the maximum process temperature of step (a).

[Example] FIG. 1 is an example of a manufacturing process diagram of a semiconductor device in an example of the present invention. Note that FIG. 1 takes as an example a case where a thin film transistor (TPT) is formed as a semiconductor element.

In FIG. 1, (a) shows a polycrystalline silicon layer 10 on an insulating amorphous material 101 such as an insulating amorphous substrate such as glass or quartz, or an insulating amorphous material layer such as 5i02.
This is the process of forming 2. An example of the conditions for forming the polycrystalline silicon layer is (1) 560°C to 6°C by LPCVD method.
A method of forming a polycrystalline silicon layer (the crystallization rate is not necessarily 100%) with a thickness of about 100 to 2000 at about 30'C. (2) LPCVD method at 500 to 560 C.
After forming a film of amorphous silicon (or microcrystalline silicon in some cases) at a temperature of about 100 to 2,000 degrees,
``A method of heat treatment at about C to 650℃ for about 2 to 20 hours and solid phase growth to polycrystallize, (3) PCVD method to obtain lO
Amorphous silicon (microcrystalline (sometimes made of silicone) for armpit thickness 100 to 2000
After forming a film to a certain degree, it is heated at about 550℃ to 650℃ for 2 to 20 minutes.
There is a method in which the material is heat-treated for about a period of time to cause solid phase growth and become polycrystalline. However, the method for forming polycrystalline silicon is not limited to this.

(b) is a step of heat treating the polycrystalline silicon layer 102 at a predetermined heat treatment temperature higher than that of step (a).

The optimum heat treatment temperature exists between 700"C and 1200C. However, if glass is used as the substrate, it cannot be exposed to the high temperatures mentioned above, so short wavelengths such as excimer lasers etc. It is important to optimize the irradiation intensity and irradiation time so that only the vicinity of the surface layer of the semiconductor is heated to the above temperature by irradiation of light, and the temperature near the interface between the semiconductor layer and the substrate is approximately 600°C or less. - For example, XeC1 excimer laser (wavelength: 308 nm)
) with an irradiation intensity of 0.1 to 1. Conditions such as irradiation of 1 to 10 pulses (1 pulse several ns) at approximately OJ/cm2 satisfy the above-mentioned conditions.

(c) is a step of forming a gate insulating film 103 after patterning the polycrystalline silicon layer 102 into a predetermined shape. The gate insulating film is formed using thermal oxidation method.
A method of forming at a high temperature of about ℃ to 1200℃ (high temperature process), CVD method, plasma CVD method, ECR-CVD
There are methods (low-temperature process) in which the substrate is formed at a low temperature of about 650° C. or lower using a method such as a method, a photo-CVD method, or a sputtering method.Of course, when glass is used as the substrate, a low-temperature process must be adopted.

(d) is a step of forming a semiconductor element, in which 103 is a gate'/IP, an edge film, 104 is a gate insulating film, 105 is a source/drain region, 106 is an interlayer insulating film, and 107 is a contact hole. , 108 indicates wiring, TPT formation - For example, after forming a gate electrode,
The source/drain regions are formed by ion implantation method, thermal diffusion method, plasma doping method, ion shower doping method, etc., and the interlayer insulating film is formed by CVD method, sputtering method, plasma carbon
It is formed by a VD method or the like. Subsequently, in order to reduce the density of defects existing in the grain boundaries, it is exposed to a plasma atmosphere of a gas containing at least hydrogen gas or ammonia gas, etc.
A TPT is formed by making a contact hole in the interlayer insulating film and forming a wiring. When using glass as the substrate, the source/drain regions are formed by implanting impurities such as poron or phosphorus by ion implantation or ion shower doping, and then at a low temperature of about 600°C for several hours to several tens of hours. Methods of activating impurities through heat treatment,
A method of activating impurities using a laser annealing method and a laser doping method that uses a laser to decompose and thermally diffuse doping gas are effective. Also, before performing the heat treatment in step (b), a gate insulating film and a gate electrode are formed, impurities are implanted by ion implantation method, etc., and then step (b) is performed.
High-temperature heat treatment such as laser annealing, lamp annealing, and similar annealing in b) is performed to activate impurities, improve the crystallization rate of polycrystalline silicon, and improve crystallinity such as reducing defects such as twin. There is also a method of performing it in a process, and high performance TPT can be formed with a simpler process.

In the conventional method of forming polycrystalline silicon using only laser annealing, amorphous silicon is irradiated with A, R laser, excimer laser, etc. to melt and recrystallize the amorphous silicon layer. It formed crystalline silicon. Therefore, when the conventional method is used for this process, when the polycrystalline silicon 102 is melted, the source/drain regions 105 are also melted at the same time, so impurities diffuse into the liquid phase and easily reach the channel region. Therefore, it has been difficult to manufacture TPT with normal characteristics with good reproducibility.

On the other hand, in the present invention, high-temperature treatment such as laser annealing
The purpose is not to melt and recrystallize, but to improve crystallinity through high-temperature treatment, so it is not necessarily necessary to melt polycrystalline silicon, and it is also possible to improve crystallinity through solid-phase reaction. can. Therefore, there is no abnormal diffusion of impurities in the liquid phase, which is a problem in conventional methods, and high-performance TPT can be formed with good reproducibility.

FIG. 2 is another example of a manufacturing process diagram of a semiconductor device according to an embodiment of the present invention. In addition, FIG. 2 takes as an example a case where a thin belly transistor (TPT) is formed as a semiconductor element.

In FIG. 2, (a) shows an impurity forming a source/drain region on an insulating amorphous material 201 such as an insulating amorphous substrate such as glass or quartz, or an insulating amorphous material layer such as 5i02. In this step, a polycrystalline silicon layer 202 doped with is formed and patterned into a predetermined shape. An example of the conditions for forming polycrystalline silicon is (1) LPCV
A polycrystalline silicon layer containing impurities such as boron and phosphorus is formed to a thickness of 100A to 250A using the D method at about 560℃ to 630℃.
Method of forming about A degree, (2) LPCVD method at 500℃
Amorphous silicon (sometimes microcrystalline silicon) containing impurities such as boron and phosphorus is deposited at a temperature of ~560°C to a thickness of 10°C.
After 0 to 2,500 people have eaten, the temperature is 550℃ to 650℃.
(3) PCVD method at 100°C to 350°C.
Amorphous silicon containing impurities such as boron and phosphorus at a temperature of about 150°C to 250°C (particularly desirable because the crystal grain size after solid phase growth is large, resulting in low resistivity) (may be microcrystalline silicon) film JI1
After forming a film of about 00A to 2500A, 550℃ to 65℃
There is a method in which heat treatment is performed at about 0° C. for about 2 to 20 hours to cause solid phase growth and polycrystalization. However, the method for forming polycrystalline silicon is not limited to this.

(b) shows a polycrystalline silicon layer 20 forming a channel region.
This is the process of forming 3. An example of the conditions for forming the polycrystalline silicon layer is (1) 560°C to 6°C by LPCVD method.
Polycrystalline silicon layer (crystallinity rate is not necessarily 1) at about 30℃
(2) LPCVD method of 500°C to 560'
After forming amorphous silicon (sometimes microcrystalline silicon) at a thickness of about 100A to 2000A at about C,
100% by PCVD method by heat treatment at ℃ to 650℃ for about 2 to 20 hours and solid phase growth to polycrystallize.
℃ ~ 350 ℃ (particularly, 150 ℃ ~ 250 ℃ is desirable because the crystal grain size after solid phase growth becomes large, resulting in high mobility) and amorphous silicon (microcrystalline silicon) After forming a film with a thickness of about 100 to 200 OA (in some cases), heat treatment is performed at about 550° C. to 650° C. for about 2 to 20 hours to cause solid phase growth and polycrystallization. However, the method for forming polycrystalline silicon is not limited to this. Also, after forming the amorphous silicon in step (a), the silicon layer forming the channel region is formed without solid phase growth. Form a film and grow both in solid phase at the same time.
It can also be polycrystalline.

(c) is a step of heat treating the polycrystalline silicon layer 203 at a predetermined heat treatment temperature higher than that of step (b).

The optimum heat treatment temperature exists between about 700°C and 1200°C. However, if glass is used as the substrate, it cannot be exposed to the high temperatures mentioned above.
By irradiating short wavelength light such as an excimer laser, only the temperature near the surface layer of the semiconductor is raised to the above temperature, and the irradiation intensity and time are optimized so that the temperature near the semiconductor layer and substrate interface is approximately 600 degrees Celsius or less. It is important to - For example, XeC1! Ximer laser (wavelength 308nm)
using an irradiation intensity of 0. 1-1. In the conventional method of forming polycrystalline silicon only by laser annealing, which satisfies the above-mentioned conditions such as irradiation with 1 to 10 pulses (1 pulse number + ns) at about OJ/am2, Ar laser, Polycrystalline silicon was formed by irradiating the amorphous silicon layer with an excimer laser or the like to melt and recrystallize it. Therefore, polycrystalline silicon 20
3, the polycrystalline silicon layer 201 doped with impurities forming the source/drain regions is also melted at the same time, so the impurities diffuse into the liquid phase and easily diffuse into the channel region. TP with normal characteristics
It was difficult to manufacture T with good reproducibility. On the other hand, in the present invention, the purpose of high-temperature treatment such as laser annealing is not to melt and recrystallize, but to improve crystallinity by high-temperature treatment, so it is not necessarily necessary to melt polycrystalline silicon. Instead, it is also possible to improve crystallinity by solid phase reaction. Therefore, there is no abnormal diffusion of impurities in the liquid phase, which is a problem in conventional methods, and high-performance TFTs can be formed with good reproducibility.

(d) is a step of forming a gate insulating film 204.

The method for forming the gate insulating film is thermal oxidation at 900°C.
A method of forming at a high temperature of ~1200℃ (high temperature process), and a method of forming at a low temperature of about 50℃ or less (low temperature process) such as CVD method, plasma CVD method, ECR-CVD method, photo CVD method, Schatta method etc. There is. Naturally, when glass is used as the substrate, a low temperature process must be employed.

(e) is a step of forming a semiconductor element. 202 is a source/drain region, 203 is a polycrystalline silicon layer forming a channel region, 204 is a gate insulating film, 205 is a gate electrode, 206 is an interlayer insulating film, 207 is a contact hole, and 208 is a wiring. TPT formation formation - for example,
After forming a gate electrode using polycrystalline silicon as an element material by LPCVD method, etc., an interlayer insulating film is formed by CVD method, sputtering method, plasma CVD method, etc., and then hydrogenation is performed. A TPT is formed by opening a contact hole and forming wiring.

FIG. 3 is another example of a manufacturing process diagram of a semiconductor device according to an embodiment of the present invention. Incidentally, FIG. 3 shows a simple example of application to a three-dimensional transistor (stacked "CMO3").

In FIG. 3, (a) shows p
- This is a step of forming a well region 302 and forming an element isolation region 303 using the LOCO3 oxidation method.

(b) shows the gate electrode 3 after forming the gate insulating film 304.
After forming 05 using poly-3i etc. as an element material, it is patterned into a predetermined shape to form a source/drain region.
This is a step of forming a diffusion layer 306.

(c) forms an insulating layer 307 forming a gate insulating film,
This is a step of opening a contact hole and forming a polycrystalline silicon layer 308. An example of film forming conditions is (1) L
A polycrystalline silicon layer (crystallinity is not necessarily 100%) is formed to a thickness of 10% using the PCVD method at approximately 560°C to 630°C.
Method of forming about 0A to 200OA, (2) LPCV
Amorphous silicon (sometimes microcrystalline silicon) is coated with a film thickness of 100A to 200OA using the D method at about 500℃ to 560℃.
A method of heat-treating a film that has been formed to a certain extent at about 550°C to 650°C for about 2 to 20 hours to cause solid phase growth and polycrystalline formation, (3
) By PCVD method] About 00℃~350℃ (especially 150℃
℃ ~ 250℃ is desirable because the crystal grain size after solid phase growth is large, resulting in high mobility), and amorphous silicon (in some cases microcrystalline silicon) is grown at 110℃.
After catching about 0A~2000A, 550℃~650℃
There is a method in which heat treatment is performed for about 2 to 20 hours to cause solid phase growth and polycrystalization. However, the method for forming polycrystalline silicon is not limited to this.

(d) is a step in which the polycrystalline silicon layer 308 is heat-treated at a predetermined temperature higher than that in step (c). The optimum heat treatment temperature exists between about 700°C and 1200°C. However, in order to prevent the redistribution of impurities in the semiconductor element in the lower layer, the irradiation should be carried out so that only the vicinity of the surface layer of the semiconductor is heated to the above temperature by irradiation with short wavelength light such as RTA or excimer laser. A method of optimizing intensity and irradiation time is effective. - As an example, use a XeC1 excimer laser (wavelength: 308 nm) with an irradiation intensity of 0.1 to 1.
．． 1 to 10 pulses at about OJ/cm2 (1 pulse number n
s) Conditions such as irradiation satisfy the above conditions.

(e) is a step of forming p' diffusion layers 310 forming source/drain regions in the poly-3i layer.

The p diffusion layer 310 can be formed by implanting impurities by ion implantation or the like and then annealing at about 700°C to 900°C for 30 minutes to several hours.
), impurities are implanted using an ion implantation method, etc., and then high-temperature heat treatment is performed using laser annealing, lamp annealing, furnace annealing, etc. to activate the impurities and improve the crystallization rate of polycrystalline silicon. There is also a method of improving crystallinity, such as reducing defects such as , twin, etc., in the same process, and it is possible to form a high-performance three-dimensional IC with a simpler process. In the conventional method of forming polycrystalline silicon using only laser annealing, polycrystalline silicon is formed by irradiating amorphous silicon with Ar laser, excimer laser, etc., melting the amorphous silicon layer, and recrystallizing it. I formed it again. Therefore, when polycrystalline silicon 308 is melted, the source/drain regions 310 are also melted at the same time, and impurities diffuse into the liquid phase and easily diffuse into the channel region, resulting in normal characteristics. It has been difficult to manufacture TPT with good reproducibility.

- On the other hand, in the present invention, high-temperature treatment such as laser annealing
The purpose is not to melt and recrystallize, but to improve the crystallinity through high-temperature treatment, so it is not necessarily necessary to melt the polycrystalline silicon, but rather to improve the crystallinity through solid phase reaction. You can also do it. Therefore, there is no abnormal diffusion of impurities in the liquid phase, which was a problem with conventional methods, and high-performance TFTs can be achieved.
can be formed with good reproducibility using a simple process. Although this embodiment shows an example of a stacked CMO3 as the simplest example of application to a three-dimensional IC, it goes without saying that the present invention is not limited to this.
The present invention, a part of which is shown in FIG.
It is important that after in-phase growth or film formation is performed at a low temperature of ~650° C. or lower, heat treatment is performed at a higher temperature. The reason for this is explained below.

Polycrystalline silicon and LPCV grown using solid phase growth method
The crystallization rate of as-depo polycrystalline silicon formed by the D method etc. is not necessarily high.
A silicon film (amorphous silicon or microcrystalline silicon in which a minute crystalline region exists in an amorphous phase) formed at a relatively low temperature of about 00°C to 560°C is grown in a solid phase by heat treatment. In this case, the crystallization rate is 50%~
Therefore, it is important to provide a step of crystallizing the uncrystallized region of the polycrystalline silicon layer by performing heat treatment in step (c) at a higher temperature than in step (b). As a result, the crystallization rate can be increased to 99% or more. In particular, when the gate insulating film is formed using the low-temperature process mentioned above, high-temperature heat treatment such as thermal oxidation is not added in the subsequent process, so it is important to increase the crystallization rate by performing the heat treatment based on the present invention. be.

As a heat treatment method, for example, at 850°C, 1 to 2
In addition to heat treatment for about 10 to 20 minutes at 1000℃, lamp annealing using a halogen lamp, arc lamp, infrared lamp, xenon lamp, mercury lamp, etc., excimer laser, Ar laser, He-Ne
There are also methods such as laser annealing using a laser or the like. Among these, laser annealing using an excimer laser can heat only the vicinity of the surface of the semiconductor layer, so it can be used even when an inexpensive glass substrate is used as a substrate, and in 3D ICs, it may adversely affect the underlying elements. The crystallinity of the element in the upper layer can be improved without causing any damage. As a result, the gate insulating film was formed using the aforementioned low-temperature process, and the source/drain regions were also formed using a low-temperature process below about 600°C (for example, after implanting impurities such as B and P using ion implantation,
A high-performance semiconductor element can be formed on a glass substrate by a method such as activating it by subjecting it to a certain amount of heat treatment for several hours to several tens of hours, and the effect is extremely large.
When laser annealing is performed after solid phase growth at about 550°C to 650°C, and when as-depO is grown without solid phase growth.
Compared to the case where the film is laser annealed, the crystal grain size of the solid phase grown film is larger (solid phase growth + laser annealing: 1 μm or more, laser annealing only: <200
(0 people), and the crystallization rate is high (with only laser annealing, the crystallization rate of the semiconductor layer near the substrate is poor, and there are also problems such as impurities (oxygen, etc.) in the lower insulating film being incorporated into the polycrystalline silicon. Particularly in the case of the bottom gate type TFT shown in FIG. 3, this has a significant effect (leading to significant deterioration of characteristics).

Furthermore, it has been found that there is an important correlation between the film formation temperature when the antinode formed by the LP CVD method is grown in a solid phase and the presence or absence of heat treatment in step (c). That is, when comparing a silicon layer formed at a high temperature (for example, about 580°C to 610°C) by the LPCVD method and a silicon layer formed at a low temperature (for example, about 500°C to 550°C), it is found that the heat treatment in step (c) In the absence of such a silicon layer, although the crystal grain size was larger in the silicon layer formed at a lower temperature, the crystallization rate was lower and the field effect mobility of TPT was also lower. However, when the heat treatment in step (c) was performed, on the contrary, the silicon layer formed at a low temperature had a larger crystal grain size, a higher crystallization rate, and a higher field effect mobility of TPT. In addition, this value is 580 by the LPCVD method.
This was a value that could not be obtained with a film formed at a high temperature of about 610°C to 610°C.

This is currently considered to be due to the reasons described below. (1) Films formed at low temperatures are amorphous silicon or microcrystalline silicon in which minute crystal regions exist in an amorphous phase. Therefore, compared to an antinode formed at a high temperature, the rate of polycrystalline nucleation during solid phase growth is lower, and polycrystalline silicon with a large grain size can be formed by solid phase growth. (
2) However, films formed at low temperatures have a high proportion of amorphous phase after solid-phase growth, and require high-temperature heat treatment to increase the crystallization rate. it is conceivable that. Therefore, the present invention is not limited to films formed by the CVD method, but also includes evaporation methods, plasma CVD methods, E
When amorphous silicon or microcrystalline silicon is formed by B evaporation method, MBE method, sputtering method, CVD method, etc., or when microcrystalline silicon or polycrystalline silicon is formed by plasma CVD.
After forming by D method, CVD method, vapor deposition method, EB vapor deposition method, MBE method, sputtering method, etc., Si, Ar, B, P,
He, Ne, Kr.

It is also effective when the microcrystalline silicon or polycrystalline silicon is completely or partially amorphized by ion implantation of an element such as H. Among these, as-depo films have a high ratio of amorphous phase and a low polycrystalline nucleation rate (that is, it is easy to form large-grain polycrystalline silicon by solid phase growth). Inventions have great effects.

The field effect mobility of polycrystalline silicon TPT (N-channel) formed by a low-temperature process using the semiconductor device manufacturing method based on the present invention is 150 to 200 cm2/V-s.
ec, and almost the same characteristics as TFTs formed by the thermal oxidation method were obtained.

Furthermore, as described above, the present invention is most effective when used in low-temperature processes, but is also effective when used in high-temperature processes. That is, when polycrystalline silicon having many uncrystallized regions is thermally oxidized, the uncrystallized regions, which have a higher oxidation rate than crystalline regions, are oxidized first. As a result, an oxide film is formed along grain boundaries, resulting in a phenomenon in which mobility decreases. However, when the annealing method of the present invention is used, the crystallization rate before thermal oxidation can be sufficiently increased and the oxidation along the grain boundaries described above can be suppressed, so the effect is extremely large.

Also, by doping impurities into the channel region, Vt
Means for controlling the h l threshold voltage) are also very effective. In polycrystalline silicon TPT formed by solid phase growth, N
The channel transistor has vth in the depletion direction.
shifts, and the P-channel transistor tends to shift in the enhancement direction. Moreover, when the above-mentioned TPT is hydrogenated, this tendency becomes more pronounced. Therefore, if the channel region is doped with an impurity of about 1015 to 10"/cm', the shift in vth can be suppressed.6 For example, in FIG. 1, before forming the gate electrode, B( 1011 impurities such as boron)
There are methods such as implanting with a dose of about 10"/am2. In particular, if the dose is about the above value, vth is controlled so that the off-state current of both the P-channel transistor and the N-channel transistor is minimized. can do.

Therefore, even when forming a CMO3 type TPT element, the entire surface can be channel-doped in the same process without selectively channel-doping Pch and Nch.

In addition to the TPT shown in the embodiment of FIG. 1, the present invention can be applied to insulated gate type semiconductor devices in general, as well as charging devices such as bipolar transistors, static induction transistors, solar cells, and optical sensors. This is an extremely effective manufacturing method when forming a semiconductor element such as a conversion element using a polycrystalline semiconductor as the element material.

[Effects of the Invention] As described above, according to the present invention, a polycrystalline silicon film with large grain size and high crystallinity can be formed with a simpler manufacturing process. As a result, it has become possible to form high-performance semiconductor elements on insulating amorphous materials, making it easy to manufacture large, high-resolution liquid crystal display panels, high-speed, high-resolution contact image sensors, 3D ICs, etc. can now be formed.

In addition to the TPT shown in the embodiment of FIG. 1, the present invention can also be applied to insulated gate semiconductor devices in general, as well as bipolar transistors, static induction transistors, charging devices such as solar cells and optical sensors. This is an extremely effective manufacturing method when forming a semiconductor element such as a conversion element using a polycrystalline semiconductor as the element material.

[Brief explanation of the drawing]

FIGS. 1(a) to 1(d) are process diagrams for manufacturing a semiconductor device in an embodiment of the present invention. FIGS. 2(a) to 2(e) are process diagrams for manufacturing a semiconductor device in an embodiment of the present invention. FIGS. 3(a) to 3(e) are process diagrams for manufacturing a semiconductor device in an embodiment of the present invention. 101.201 ... Insulating amorphous material 102
．． 203,308 ... 103.204,304.307 104.205,305 ... 105.202 106.206 107.207 108.208 Polycrystalline silicon layer... Gate insulating film Gate electrode source/drain region interlayer Insulating film contact hole wiring silicon substrate element isolation area and above Applicant Seiko Epson Co., Ltd. Attorney Kizobu Tsuchi Suzuki (1 person) Figure 1 (a) Figure 1 (b) Figure 1 (c) Figure 1 (d) Figure 2 (b) Figure 2 (c) Figure 2 (d) Army Figure 2 (8)

Claims (1)

[Claims] 1) (a) Step of forming a polycrystalline semiconductor layer mainly composed of silicon on an insulating amorphous material, (b) Up to a predetermined temperature higher than the maximum process temperature of step (a) A method for manufacturing a semiconductor device, comprising at least a step of increasing the temperature of the polycrystalline semiconductor layer. 2) The predetermined temperature in step (b) is 700°C to 1200°C.
2. The method of manufacturing a semiconductor device according to claim 1, wherein the temperature is .degree. 3) The method of manufacturing a semiconductor device according to claim 1, wherein the heat treatment in step (b) is performed using an excimer laser. 4) (a) Step of forming a polycrystalline semiconductor layer mainly composed of silicon on an insulating amorphous material; (b) Doping an impurity into or in contact with the polycrystalline semiconductor layer. Step (c) of forming a semiconductor region is characterized by having at least the step of raising the temperature of at least the polycrystalline semiconductor layer and the semiconductor region doped with impurities to a predetermined temperature higher than the maximum temperature of 1 degree in the process of step (a). A method for manufacturing a semiconductor device.