JP4377706B2 - Method for manufacturing thin film semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a thin film semiconductor device, and more particularly to a method for manufacturing a thin film semiconductor device characterized by a process for eliminating an injection defect in a channel edge portion associated with a source / drain formation process.

  In recent years, thin film semiconductor devices such as TFTs have been widely used as drive elements for active matrix liquid crystal display devices and the like, but the characteristics of p-channel TFTs are not sufficient compared with those of n-channel TFTs, and CMOS circuits It was a problem when configuring.

The cause is that the resistance value of the source / drain region is high, because the implanted ions are not sufficiently activated.
Therefore, when the activation process is performed at a high temperature in order to increase the activation, the resistance value decreases, but there is a problem that the glass substrate cannot withstand the high temperature.

  Therefore, in order to perform sufficient activation treatment at a relatively low temperature, in the source / drain formation step, Si or Ge is implanted into the source / drain formation region in advance, and then the conductivity type is formed. Improve crystallinity, dopant activation rate, and lower resistance of source / drain regions by utilizing solid layer growth of amorphous layer in the annealing process for activation after ion implantation of deterministic impurities (For example, see Non-Patent Documents 1 and 2).

Here, a manufacturing process of a conventional TFT will be described with reference to FIGS.
See Figure 4
First, an SiO ₂ buffer layer 32 is formed on the glass substrate 31 by a plasma CVD (PCVD) method, and then an α-silicon film 33 is similarly formed on the SiO ₂ buffer layer 32 by a PCVD method.

  Next, laser annealing is performed on the α-silicon film 33 using an excimer laser or the like, so that the α-silicon film 33 is crystallized and converted into a polycrystalline silicon film 34.

  Next, after the polycrystalline silicon film 34 is patterned to form island-shaped silicon regions 35, a gate insulating film 36 is formed so as to cover the island-shaped silicon regions 35.

See Figure 5
Next, after providing a gate electrode 37 on the gate insulating film 36, the peripheral portion of the gate insulating film 36 is removed, and then Si ions or Ge ions 38 are ion-implanted by using the gate electrode 37 as a mask. The formation region is made amorphous to be an amorphous region 39.

Subsequently, the conductivity determining impurity 40 is ion-implanted using the gate electrode 37 as a mask, and annealing is performed at 600 ° C. or lower to activate and recrystallize the implanted ions to form the source / drain regions 41. To do.
At this time, since the ion implantation region is amorphized in advance, the activation efficiency is increased. As the conductivity determining impurity 40, P or As is used when forming an n-type region, and B is used when forming a p-type region.

Next, after depositing an interlayer insulating film 42 on the entire surface, a contact hole for the gate electrode 37 and the source / drain region 41 is provided, and a conductive film such as Al is deposited on the deposition susceptor and patterned to thereby form the source / drain electrode 43 and the gate. By forming an extraction electrode (not shown), the basic structure of the TFT is completed.
Applied Physics Letters, Vol. A44, p. 135, 1987 Mat. Res. Symp. Proc. , Vol. 669, p. 2001

  However, in the amorphization process, Si ions or Ge ions are implanted only in the source / drain formation region, so that the implantation portion is incomplete at the boundary with the channel region. There is a problem that it remains in the channel edge portion at the boundary between the drain region and the channel region, and this injection defect causes an increase in leakage current.

  Therefore, an object of the present invention is to avoid the occurrence of implantation defects at the channel edge portion accompanying ion implantation.

FIG. 1 is a diagram illustrating the basic configuration of the present invention. Means for solving the problems in the present invention will be described with reference to FIG.
Reference numerals 6 and 10 in the figure denote a crystalline group IV semiconductor layer and a gate electrode, respectively.
To solve the above-described problem, the present invention provides a thin film semiconductor device manufacturing method in which at least a source / drain formation region and a channel are formed after a polycrystalline group IV semiconductor layer 2 is deposited on an insulating substrate 1. Either the group IV element or the rare gas element 3 is ion-implanted into the region so that the lower part of the polycrystalline group IV semiconductor layer 2 having a thickness of at least 0.5 nm from the interface with the insulating substrate 1 remains in the polycrystalline state. The step of making the amorphous structure remaining , the step of ion-implanting the conductivity-determining impurity 5 into the source / drain formation region of the amorphized group IV semiconductor layer 4, activating the conductivity-determining impurity 5 and making the amorphous IV And an annealing step of recrystallizing the group semiconductor layer 4 .

In this way, by performing ion implantation for amorphization in at least the source / drain formation region and the channel formation region of the polycrystalline group IV semiconductor layer 2, no implantation defects are generated at the channel edge.
In this case, in the amorphization step, the polycrystalline group IV semiconductor layer 2 having a thickness of 0.5 nm or more, for example, 0.5 nm to 40 nm, more preferably 5 nm to 20 nm, from the interface with the insulating substrate 1. Since the lower portion of the polycrystalline IV semiconductor layer 2 remains as a seed crystal in solid phase growth in recrystallization, good crystallinity is obtained.

  In this case, the group IV semiconductor may be any group IV semiconductor such as silicon, germanium, SiGe, SiC, SiGeC, etc., but silicon is typical, and an element to be implanted for amorphization is used. The element may be any element that does not become a conductivity-type determining impurity for a group IV element such as Si, Ge, or C, or a group IV element such as a rare gas element 3 such as Ar, Xe, or Kr, but either Si or Ge is typical. Is something.

The amorphization step is preferably performed before the step of forming the gate insulating film 9, and the implantation amount is preferably in the range of 1 × 10 ¹⁴ cm ⁻² to 1 × 10 ¹⁶ cm ⁻² .
When the injection amount is less than 1 × 10 ¹⁴ cm ⁻² , which is the critical injection amount, amorphization is not sufficient. On the other hand, when it exceeds 1 × 10 ¹⁶ cm ⁻² , crystallinity is sufficiently recovered in the annealing process. Is not.

  In this case, the annealing temperature is preferably 750 ° C. or lower, which is not distorted by a typical glass substrate typical of the insulating substrate 1, and is 400 ° C. or higher in order to obtain sufficient crystallinity. It is desirable to anneal.

Further, in the ion implantation process to the source / drain formation region, the junction of the source / drain region 7 is deep enough to accommodate the residual defect 8 after annealing, that is, the amorphous group IV semiconductor layer 4 remains. It is desirable to implant ions so that the concentration of the conductivity type determining impurity 5 at the interface with the polycrystalline group IV semiconductor layer 2 is 1 × 10 ¹⁷ cm ⁻³ or more, so that the residual defect 8 is always in a charged state. Therefore, it does not contribute to the leakage current.

  In the present invention, the channel edge portion, which is the boundary between the channel region and the source / drain region, is not damaged by amorphization, so that the leakage current can be reduced.

  Further, in the amorphization step, a polycrystalline group IV semiconductor layer having a thickness of 0.5 nm or more, for example, 0.5 nm to 40 nm, is left from the interface with the insulating substrate 1 to leave the remaining polycrystal. The crystal IV group semiconductor layer acts as a seed crystal for solid layer growth in the recrystallization process by annealing, so that a good crystal is obtained, and the source / drain sheet resistance is reduced to 1/10 and the parasitic resistance value is reduced to 1/3. can do.

  In the present invention, prior ion implantation of an element such as silicon or germanium for enhancing the activation efficiency of conductivity-determining impurity ions implanted in the source / drain regions is performed on the silicon film including the source / drain regions and the channel region. Then, conductivity type determination impurity implantation is performed on the amorphous silicon film, and then annealing is performed to activate the implanted ions, and the amorphized layer is recrystallized to regenerate the source / drain. A region is formed.

  Further, in the amorphization process, a portion having a thickness of 0.5 nm to 40 nm is left in a polycrystalline state from the interface with the glass substrate, so that in the recrystallization process by annealing, almost single crystal Good crystallinity can be obtained.

Here, with reference to FIG.2 and FIG.3, the manufacturing process of TFT of Example 1 of this invention is demonstrated. See Figure 2
First, an SiO ₂ buffer layer 12 having a thickness of, for example, 200 nm is laminated on the transparent glass substrate 11 by, for example, a PCVD method, and then an α-silicon film 13 having a thickness of, for example, 50 nm is sequentially deposited. .

  Next, the α-silicon film 13 is crystallized and converted into a polycrystalline silicon film 14 by performing laser annealing using a XeCl excimer laser.

Next, Ge ions 15 are implanted into the entire surface of the polycrystalline silicon film 14 by 1 × 10 ¹⁴ cm ⁻² to 1 × 10 ¹⁶ cm ⁻² , for example, 1 × 10 ¹⁵ cm ⁻² to make the polycrystalline silicon film 14 amorphous. The silicon film 16 is converted.

At this time, a range of 0.5 nm to 40 nm, for example, 10 nm from the interface of the glass substrate 11 is left as it is as the polycrystalline silicon film 14, and used as a seed crystal in the solid phase growth process in the subsequent annealing process.
Although depending on the implantation conditions, when the Ge ions 15 are less than 1 × 10 ¹⁴ cm ⁻² , the critical dose amount is not reached, so that amorphization is insufficient and exceeds 1 × 10 ¹⁶ cm ⁻² . If the injection amount is too large, the crystallinity may not be recovered.

Next, after the island-like silicon region 17 is formed by patterning the amorphized silicon film 16 / polycrystalline silicon film 14 by performing dry etching, the thickness is again formed on the entire surface by using the PCVD method, for example, A 40 nm SiO ₂ film 18 is deposited.

See Figure 3
Next, after depositing an Al film having a thickness of, for example, 200 nm on the entire surface by sputtering, patterning is performed using a normal photoetching process to form the gate oxide film 19 and the Al gate electrode 20.

Next, ion implantation region 22 is formed by implanting B ions 21 using Al gate electrode 20 as a mask.
In this case, in the annealing process described later, the p ⁺ type source / drain region is amorphized so that the junction of the p ⁺ type source / drain region is deep enough to accommodate the residual defect 25 formed at the amorphized silicon film 16 / polycrystalline silicon film 14 interface. It is necessary to perform ion implantation deeper than the interface of the silicon film 16 / polycrystalline silicon film 14, and specifically, the B concentration at the interface of the amorphized silicon film 16 / polycrystalline silicon film 14 in the implantation profile is 1 × 10 ¹⁷ cm ^−. Ion implantation is performed so that ³ or more.

Next, by performing lamp annealing at 400 ° C. to 750 ° C., for example, 550 ° C. for 4 hours, the implanted P ions are activated to make the ion implantation region 22 into p ⁺ type source / drain regions 23, and amorphous silicon The film 16 is recrystallized to be converted into a crystalline silicon film 24.

  The annealing conditions in this case must be a low temperature of 750 ° C. or lower in order to prevent the glass substrate 11 from being distorted, and the annealing time must be stopped at the time when the solid layer growth is completed.

At this time, Ge ions are also implanted into the channel edge portion to be amorphous, so that no implantation defects remain in the annealing process.
In addition, since the polycrystalline silicon film 14 remains thin on the interface side with the glass substrate 11, the crystallinity of the crystalline silicon film 24 is improved and becomes almost single crystal.

Next, a SiO ₂ film 27 having a thickness of, for example, 30 nm and a Si ₃ N ₄ film 28 having a thickness of, for example, 370 nm are sequentially deposited on the entire surface to form the interlayer insulating film 26.

Next, after forming contact holes for the Al gate electrode 20 and the p ⁺ -type source / drain regions 23 in the interlayer insulating film 26, the entire surface has a thickness of, for example, a 100 nm Ti film, a 200 nm Al film, and a 100 nm Ti film. The basic structure of the TFT is formed by sequentially depositing a film and then patterning to form a source / drain electrode 29 having a Ti / Al / Ti structure and an upper gate extraction electrode / lower gate extraction electrode (both not shown). A configuration is obtained.

  As described above, Ge or the like is ion-implanted at least into the source / drain formation region and the channel formation region before the ion implantation step for forming the source / drain region, so that it is amorphized. An injection defect does not occur in the channel edge portion which is an interface between the source / drain region and the channel region, and a leakage current due to the injection defect can be eliminated.

  Further, in the amorphization process, the polycrystalline silicon film is left on the glass substrate side to form a seed crystal in the annealing process, so that the crystallinity of the crystallized silicon film can be improved.

  Further, since the source / drain regions are formed so as to have a depth that can accommodate the residual defects accompanying the annealing process, the residual defects are always in a charged state, and the leakage current accompanying the residual defects can be reduced.

  By these synergistic effects, in the present invention, the source / drain sheet resistance can be reduced to 1/10 compared to the case where Ge is not implanted, and the TFT parasitic resistance value can be reduced to 1/3. It was.

  Although the embodiments of the present invention have been described above, the present invention is not limited to the conditions and configurations described in the embodiments, and various modifications are possible. For example, the film thickness and the implantation described in the embodiments Numerical values such as quantities are not limited to the numerical values described.

  In the embodiment of the present invention, an excimer laser is used in the first crystallization laser annealing step. However, it is not limited to the excimer laser, and a CW (continuous oscillation) laser such as a YAG laser is used. Is also good.

  In the embodiment of the present invention, lamp annealing is used in the step of activating the implanted ions. However, the present invention is not limited to lamp annealing, and furnace annealing using a heating furnace may be used.

  In the embodiments of the present invention, Al is used as the gate electrode. However, the present invention is not limited to Al, and a refractory metal such as Mo or Ti or a silicide thereof may be used.

  In the embodiments of the present invention, Ge is used as an element to be implanted for amorphization, but is not limited to Ge, Si or C may be used, or Ar, Xe, Kr, etc. The rare gas element may be used.

  In the embodiment of the present invention, Si is used as the element forming semiconductor, but is not limited to Si, and may be other group IV semiconductors such as SiGe mixed crystal, SiC mixed crystal, and SiGeC mixed crystal. In this case as well, an IV group element such as Ge or a rare gas element may be used as an implantation element for amorphization.

  Further, in the embodiments of the present invention, since a thin semiconductor film is premised on forming an element, the source / drain regions are formed so as to have a depth that can accommodate residual defects accompanying the annealing process. When the thickness of the source / drain region is increased, the source / drain region may be formed at a position away from the residual defect caused by the annealing process. In this case as well, the leakage current due to the residual defect can be reduced.

In the embodiment of the present invention, B is used as the conductivity determining impurity for forming the p ⁺ type source / drain regions. However, the present invention is not limited to B. In the case of an n-channel TFT, In order to form the n ⁺ -type source / drain regions, P or As may be ion-implanted.

The detailed features of the present invention will be described again with reference to FIG. 1 again.
1 again (Appendix 1) After depositing the polycrystalline group IV semiconductor layer 2 on the insulating substrate 1, at least one of the group IV element or the noble gas element 3 is added to the source / drain formation region and the channel formation region. A process of ion implantation to amorphize the polycrystalline IV group semiconductor layer 2 having a thickness of at least 0.5 nm from the interface with the insulating substrate 1 while remaining in a polycrystalline state; and an amorphous IV group semiconductor A step of ion-implanting the conductivity type determining impurity 5 in the source / drain formation region of the layer 4; and an annealing step of activating the conductivity type determining impurity 5 and recrystallizing the amorphous group IV semiconductor layer 4 A method for manufacturing a thin film semiconductor device.
(Supplementary Note 2) and the group IV semiconductor is silicon, and method of manufacturing a thin film semiconductor device according to Supplementary Note 1, wherein the group IV element to be injected for the amorphization is either silicon or germanium .
(Additional remark 3) The manufacturing method of the thin film semiconductor device of Additional remark 1 or 2 characterized by the said amorphization process being before the formation process of the gate insulating film 9.
(Appendix 4) Any one of appendices 1 to 3, wherein an amount of an element to be implanted for the amorphization is 1 × 10 ¹⁴ cm ⁻² to 1 × 10 ¹⁶ cm ^−2. Manufacturing method of a thin film semiconductor device.
(Additional remark 5 ) The temperature in the said annealing process is 750 degrees C or less, The manufacturing method of the thin film semiconductor device of any one of Additional remark 1 thru | or 4 characterized by the above-mentioned.
(Supplementary Note 6) Oite the ion implantation process into the source and drain formation regions, said conductivity determining impurity 5 at the interface between the polycrystalline Group IV semiconductor layer 2 described above remains the group IV semiconductor layer 4 mentioned above amorphized 6. The method of manufacturing a thin film semiconductor device according to any one of appendices 1 to 5 , wherein the ion implantation is performed so that the concentration is 1 × 10 ¹⁷ cm ⁻³ or more .

  As a practical example of the present invention, a TFT used in an active matrix liquid crystal display device is typical, but the present invention is not limited to an active matrix liquid crystal display device, and is active for various display devices such as an organic EL. It may be used as a driving element for a matrix substrate or a line light sensor.

It is explanatory drawing of the fundamental structure of this invention. It is explanatory drawing of the manufacturing process to the middle of TFT of Example 1 of this invention. It is explanatory drawing of the manufacturing process after FIG. 2 of TFT of Example 1 of this invention. It is explanatory drawing of the manufacturing process to the middle of the conventional TFT. It is explanatory drawing of the manufacturing process after FIG. 4 of the conventional TFT.

Explanation of symbols

1 Insulating substrate 2 Polycrystalline group IV semiconductor layer 3 Group IV element or rare gas element 4 Amorphized group IV semiconductor layer 5 Conductivity determining impurity 6 Crystalline group IV semiconductor layer 7 Source / drain region 8 Residual defect 9 Gate insulation Film 10 Gate electrode 11 Glass substrate 12 SiO ₂ buffer layer 13 α-silicon film 14 Polycrystalline silicon film 15 Ge ion 16 Amorphized silicon film 17 Island-like silicon region 18 SiO ₂ film 19 Gate oxide film 20 Al gate electrode 21 B ion 22 ion implantation region 23 p ⁺ type source / drain region 24 crystalline silicon film 25 residual defect 26 interlayer insulating film 27 SiO ₂ film 28 Si ₃ N ₄ film 29 source / drain electrode 31 glass substrate 32 SiO ₂ buffer layer 33 α− Silicon film 34 polycrystalline silicon film 35 island-like silicon region 36 gate insulation 37 gate electrode 38 Si ions or Ge ions 39 amorphized regions 40 conductivity determining impurity 41 source and drain regions 42 interlayer insulating film 43 source and drain electrodes

Claims (4)

After depositing the polycrystalline group IV semiconductor layer on the insulating substrate, at least one of the group IV element or the rare gas element is ion-implanted into the source / drain formation region and the channel formation region, from the interface with the insulating substrate. Amorphizing the lower part of the polycrystalline group IV semiconductor layer having a thickness of at least 0.5 nm while leaving the polycrystalline state ;
A step of ion-implanting a conductivity-determining impurity into a source / drain formation region of the amorphous group IV semiconductor layer ;
A method for manufacturing a thin film semiconductor device , comprising: an annealing step for activating the conductivity determining impurity and recrystallizing the amorphous group IV semiconductor layer . 2. The method of manufacturing a thin film semiconductor device according to claim 1, wherein an amount of an element implanted for the amorphization is 1 × 10 ¹⁴ cm ⁻² to 1 × 10 ¹⁶ cm ⁻² . The temperature in the annealing step, the method of manufacturing a thin film semiconductor device according to claim 1 or claim 2, characterized in that at 750 ° C. or less. Oite the ion implantation process into the source and drain formation regions, wherein the amorphized IV semiconductor layer and said remaining polycrystalline concentration of the conductivity determining impurity at the interface between the IV group semiconductor layer is 1 × 10 ¹⁷ cm ^The method for manufacturing a thin film semiconductor device according to claim 1, wherein ions are implanted so as to be ⁻³ or more .

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