JPH02252246A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a polycrystalline silicon film with large grain diameter by a simple process by a method wherein a semiconductor layer whose main body is silicon is formed on insulative amorphous material, and the temperature is raised up to a value for heat treatment by spending a specified time. CONSTITUTION:By LPCVD method, a silicon layer 102 is formed on insulative amorphous material, at a temperature of 500-560 deg.C. The layer 102 is heat-treated in an inert gas atmosphere like nitrogen, at 550-650 deg.C for 2-10 hours, thereby forming a polycrystalline silicon 103. By thermally oxidizing the layer 103 at a gate oxidation temperature of 1000-1200 deg.C, a gate oxide film 104 is formed. In this case, crystal in a region where crystallization is not completed is damaged by rapid temperature rise, so that the crystallizability after gate oxidation becomes high when the temperature rise speed is smaller than 20 deg.C/min. After that, a gate electrode 105, a source-drain region 106, and an interlayer insulating film 107 are arranged, thereby forming a TFT. Hence a semiconductor element of high performance can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor element on an insulating amorphous material.

[Prior Art] Attempts have been made to form a high-performance semiconductor device on an insulating amorphous substrate such as glass or quartz, or an insulating amorphous layer such as 5i02.

In recent years, as the need for large, high-resolution liquid crystal display panels, high-speed, high-resolution contact-type image sensors, Miakimoto ICs, etc. has increased, high-performance semiconductor devices on insulating amorphous materials such as those mentioned above are becoming increasingly popular. The realization of this is eagerly awaited.

Taking the case of forming a thin film transistor (TPT) on an insulating amorphous material as an example, (1) TPT whose element material is amorphous silicon formed by plasma CVD method, etc.;
(2) TPT whose element material is polycrystalline silicon formed by CVD method or the like; (3) TPT whose element material is single crystal silicon formed by melt recrystallization method or the like are being considered.

However, among these TPTs, TPTs made of amorphous silicon or polycrystalline silicon have significantly lower field-effect mobilities than those made of single-crystal silicon (amorphous silicon TFT < 1c
m2/V-sec, polycrystalline silicon TFT
~10 cm2/V-see), it was difficult to realize a high-performance TPT.

On the other hand, the melting and recrystallization method using laser beams, etc. is still not a fully developed technology, and it also poses technical difficulties when it is necessary to form elements over a large area, such as in liquid crystal display panels. Especially big.

[Problem to be solved by the invention] Therefore, a method of solid-phase growth of large-grain polycrystalline silicon has attracted attention as a simple and practical method for forming high-performance semiconductor elements on insulating amorphous materials. and research is underway. (Thin 5 solid films 1
00 (1983) p, 227, JJAP Vo
1, 25 No. 2 (1986) 1), L121) However, in the conventional technology, polycrystalline silicon is formed by a CVD method, and after the polycrystalline silicon is made amorphous by ion implantation of Si'', Heat treatment at about 600° C. was performed for nearly 100 hours.Therefore, in addition to requiring an expensive ion implantation device, the heat treatment time was also extremely long.

Therefore, the present invention provides a manufacturing method for forming polycrystalline silicon with large grain size and high crystallinity using a simpler and more practical method.

[Means for Solving the Problems] The method for manufacturing a semiconductor device of the present invention includes: (a) forming a semiconductor layer mainly composed of silicon on an insulating amorphous material; (b) heating to a predetermined heat treatment temperature. The method is characterized in that it includes at least a step of increasing the temperature over a certain period of time.

Further, the method for manufacturing a semiconductor device of the present invention includes: (a) forming a semiconductor layer mainly composed of silicon on an insulating amorphous material; (b) growing crystals of the semiconductor layer by heat treatment or the like; (c) The method is characterized by comprising at least a step of treating the semiconductor layer at a predetermined heat treatment temperature higher than that of step (b).

[Example] FIG. 1 is an example of a manufacturing process diagram of a semiconductor device in an example of the present invention. Note that FIG. 1 takes as an example a case where a thin film transistor (TPT) is formed as a semiconductor element.

In FIG. 1, (a) shows silicon N102 on an insulating amorphous material 101 such as an insulating amorphous substrate such as glass or quartz, or an insulating amorphous material layer such as Si02.
This is the process of forming. As an example of film forming conditions, Teha, LP
Film thickness of 100~ at about 500℃~560℃ using CVD method
There are methods such as forming a silicon film of about 2,000 layers. However, the film forming method is not limited to this.

(b) is a step of growing crystals of the silicon layer 102 by heat treatment or the like. The heat treatment conditions vary depending on the method of forming the silicon layer in step (a). Polycrystalline silicon QJW 103 is formed by heat treatment at about 550° C. to 650° C. for about 2 to 10 hours in an inert gas atmosphere such as nitrogen or Ar, although the I conditions are different.

(c) is a step of oxidizing the polycrystalline silicon [103] by a thermal oxidation method to form a gate insulating film 104.

The gate oxidation temperature is about 1000°C to 1200°C.

Although the polycrystalline silicon layer 103 is crystal-grown by the in-phase growth method in step (b), its crystallization rate is not necessarily high. In particular, 500°C to 560°C with LPCV and D method.
When a silicon film (amorphous silicon or microcrystalline silicon in which a minute crystalline region exists in an amorphous phase) formed at a relatively low temperature of about °C is grown in solid phase by heat treatment. The crystallization rate is as low as about 50% to 70%. Therefore, when the polycrystalline silicon layer is oxidized by a thermal oxidation method, if the temperature is rapidly raised to a high temperature of about 1000°C to 1200°C, about 50% to 30% of the uncrystallized region remains. Our investigation revealed that the crystallinity of .

Although there is currently no clear cause-and-effect relationship, when the temperature rises rapidly, (1) many crystal layers are generated in the uncrystallized region, and many fine crystal grains grow.

(2) Crystallization of the non-crystalline region that progresses during the temperature rising to thermal oxidation process does not progress very much.

Possible causes include: Therefore, as a means to solve this problem, we have developed polycrystalline silicon by controlling the heating rate and method when heating it to a thermal oxidation temperature of about 1000°C to 1200°C. We have found a way to significantly improve the crystallinity of the layer.

Furthermore, it has been found that there is an important correlation between the film formation temperature of the film formed by the LPCVD method and the temperature raising method during gate oxidation. That is, high temperature (for example, 580 ° C to 6
A silicon layer formed at a temperature of about 10℃) and a silicon layer formed at a low temperature (for example,
When comparing silicon layers formed at a temperature of about 500°C to 550°C, if the temperature rises rapidly to the gate oxidation temperature, the silicon layer formed at a lower temperature has a lower crystallinity, and TPT
The field effect mobility of TPT was also small, but when the temperature raising method of the present invention was adopted, on the contrary, the silicon layer formed at a low temperature had a larger crystal grain size and a higher crystallinity, and the field effect mobility of TPT was lower. It was also big. In addition, this Rano value is LPCVD
This was a value that could not be obtained with a film formed at a high temperature of about 580° C. to 610° C. by the method.

This is currently considered to be due to the reasons described below. (1) Films formed at low temperatures are amorphous silicon or microcrystalline silicon in which minute crystal regions exist in an amorphous phase. Therefore, compared to a film formed at a high temperature, the density of polycrystalline nucleation during solid phase growth is lower, and polycrystalline silicon with large grain size can be formed by solid phase growth. (2)
However, films formed at low temperatures have a high proportion of amorphous phase after solid-phase growth, and the rapid temperature rise during gate oxidation impairs crystallinity for the reasons mentioned above. it is conceivable that. Therefore, the present invention is not limited to films formed by the CVD method, but also includes evaporation methods,
When amorphous silicon or microcrystalline silicon is formed by plasma CVD method, EB evaporation method, MBE method, sputtering method, CVD method, etc., or when microcrystalline silicon or polycrystalline silicon is formed by plasma CVD method, CVD method, vapor deposition method, etc. ~Si, Ar
.

It is also effective when formed by ion implantation of elements such as B, P, He, Ne, Kr, H, etc. to completely or partially amorphize the microcrystalline silicon or polycrystalline silicon, etc. It is. In particular,
As-depo films have a high ratio of amorphous phase and a low polycrystalline nucleation density (that is, it is easy to form large-grain polycrystalline silicon by solid phase growth), and the present invention Great effect.

Next, the heat treatment conditions in the present invention, particularly the method of raising the temperature to a predetermined temperature, will be described. FIG. 2 is an example of a schematic diagram of a temperature raising method in an embodiment of the present invention. In Fig. 2, (a) is silicon which is heated to a predetermined temperature (T1) at a predetermined temperature increase rate and then annealed at a predetermined temperature (T+) in an inert gas atmosphere such as argon or nitrogen. layer 1θ
2 is grown in a solid phase to form a polycrystalline silicon layer 103,
Next, a case will be shown in which gate oxidation is performed by increasing the temperature at a predetermined temperature increase rate to a predetermined gate oxidation temperature (T2). As mentioned above, it is preferable that the temperature increase rate from T1 to T2 is slower than about 20° C./min (preferably 5° C./min) because the crystallization rate after gate oxidation is high. There is also a method in which the atmosphere is switched from an inert gas atmosphere such as argon or nitrogen to an atmosphere containing at least one of oxygen, water vapor, hydrogen chloride, etc. during the temperature increase, and the temperature is increased while oxidation progresses. (This method can also be applied to the heating method described below.) Note that the heating rate does not always need to be constant, and may of course vary within the above-mentioned value range. In addition, after heat treatment at temperature T1, the sample was taken out once again, and the temperature was increased again at the predetermined heating rate to T2.
There is also a way to raise the temperature. (However, continuous heat treatment was more advantageous in terms of time and also had better crystallinity.) Figure 2 (b) shows that the temperature was raised at a predetermined rate to a predetermined temperature (T1). Then, the silicon layer 102 is annealed at a predetermined temperature (T1) to form a polycrystalline silicon layer 103 by solid-phase growth, and then the temperature increase rate is reduced as the temperature increases to a predetermined gate oxidation temperature (T2). In this example, the gate oxidation is performed by increasing the temperature and performing gate oxidation. In particular, the temperature is between 800°C and 1000°C.
In the region where the temperature exceeds about .degree. C., it is preferable to set the temperature increase rate to less than 5.degree. C./min. On the other hand, at temperatures below about 700°C, the temperature increase rate may be set higher than 10°C/min.

In FIG. 2(c), the temperature is raised to a predetermined temperature (T+) at a predetermined temperature increase rate, and then annealed at a predetermined temperature (T+) to grow silicon M102 in solid phase to form a polycrystalline silicon layer 103. Then, the temperature is raised to a predetermined temperature (Ta) at a predetermined temperature increase rate, held for a certain period of time, and then the temperature is raised to a predetermined gate oxidation temperature (T3) at a predetermined temperature increase rate. . By holding the temperature (T2) lower than the gate oxidation temperature (T3) for a predetermined period of time (for example, about 10 minutes to 1 hour), the crystallization rate can be increased without impairing the crystallinity. Therefore, when the temperature is raised to the gate oxidation temperature after being maintained at T2 for a predetermined time, defects are unlikely to occur even if the temperature rise rate is increased. T2 is preferably about 700°C to 900°C. Note that it is not necessary to keep the predetermined temperature (T2) constant. For example, the temperature may be increased slowly at a temperature increase rate slower than 5° C./min. Further, there may be a plurality of temperatures (T2) to be maintained at a predetermined temperature. For example, after being held at about 700°C,
There is also a method of re-holding at about 00°C, which is effective in further reducing defects in the film.

FIG. 2(d) shows the case where gate oxidation is performed by raising the temperature at a predetermined rate to a predetermined gate oxidation temperature (T I), and the stage where in-phase growth is performed while maintaining the predetermined temperature is particularly This is a case in which in-phase growth is allowed to proceed while raising the temperature without providing the same, and the processing time can be shortened. The temperature increase rate to T+ is 5 to 10℃/min (preferably 2
The slower the crystallization rate (°C/min), the higher the crystallization rate, which is desirable. still,
The temperature increase rate does not always need to be constant, and may of course vary within the above-mentioned value range.

FIG. 2(e) shows that up to a predetermined gate oxidation temperature (T+),
A case is shown in which gate oxidation is performed by increasing the temperature at a lower temperature increase rate as the temperature increases. Especially when the temperature is between 700°C and 100°C.
In the region where the temperature exceeds about 0°C, it is preferable to set the temperature increase rate to less than 5°C/min because this improves the crystallinity of polycrystalline silicon. On the other hand, in a region where the temperature is 450° C. or lower, even if the heating rate is increased to more than 40'C/min, the crystallinity of polycrystalline silicon is hardly affected, leading to a reduction in the heating time. In the region of about 500°C to 700°C, in-phase growth progresses, so it is preferable to set the temperature increase rate lower than 5°C/min (preferably 2°C/min).

Note that by using a combination of a plurality of materials shown in FIGS. 2(a) to 2(e), it is possible to further suppress the occurrence of defects and improve crystallinity and crystallization rate. In addition, Fig. 2 (a
) to (e) are examples of the present embodiment, and the present invention is not limited thereto.

FIG. 1(d) shows a step of forming a semiconductor element. Note that FIG. 1(d) takes as an example a case where a TPT is formed as a semiconductor element. In the figure, 104 is a gate insulating film, 105 is a gate electrode, 106 is a source/drain region, 107 is an insulating film between the eyebrows, 108 is a contact hole, 1
09 indicates wiring. As an example of the TPT formation method, after forming the gate electrode, the source/drain regions are formed by ion implantation, thermal diffusion, plasma doping, etc., and the glabella insulating film is formed by CVD, sputtering, plasma CVD, etc. J
f5 is formed. Furthermore, a TPT is formed by making a contact hole in the glabella insulating film and forming wiring.

In this embodiment, gate oxidation is performed as the high-temperature heat treatment, but the present invention is not limited thereto. For example, at a predetermined temperature (e.g. 1000°C to 12°C)
It is also possible to simply perform heat treatment at the predetermined temperature after raising the temperature at a predetermined temperature increase rate to about 00°C. However, when forming an insulated gate type semiconductor element, it is effective to also perform the above-mentioned heat treatment in the gate oxidation step, as this will shorten the process.

The field effect mobility of polycrystalline silicon TPT (N-channel) manufactured by the semiconductor device manufacturing method based on the present invention is 150 to 2000 m2/v-5ec, and high-performance polycrystalline silicon TPT can be formed by a simple process. You can.

Furthermore, when the TPT manufacturing process includes a step of exposing the semiconductor element to a plasma atmosphere of a gas containing at least hydrogen gas or ammonia gas, and the TPT is hydrogenated, the defect density existing in the grain boundaries is reduced, and the electric field Effect mobility is further improved.

Also, by doping impurities into the channel region, Vt
A means for controlling h (L, threshold voltage) is also extremely effective. In a polycrystalline silicon TPT formed by solid phase growth, an N-channel transistor is
th shifts, and the P-channel transistor tends to shift in the enhancement direction. Also, the above TPT
When hydrogenated, this tendency becomes more pronounced. Therefore, if the channel region is doped with an impurity of about 1015 to 10"/am3, the shift in vth can be suppressed. For example, in FIG. 1, before forming the gate N pole, B( There are methods such as implanting impurities such as boron) at a dose of about 1QI to 1QI3/cm2.In particular, if the dose is about the above value, P-channel transistor, N-channel transistor, etc. vth can be controlled so that the transistor off-state current is minimized.Therefore, 0MO
Even when forming an 8-type TPT element, P c h
, N ch without selective channel doping,
The entire surface can also be channel doped in the same process.

In addition to the TPT shown in the embodiment shown in FIG. 1, the present invention can be applied to insulated gate semiconductor devices in general, as well as photovoltaic devices such as bipolar transistors, static induction transistors, solar cells, and optical sensors. This is an extremely effective manufacturing method when forming a semiconductor element such as a conversion element using a polycrystalline semiconductor as the element material.

[Effects of the Invention] As described above, according to the present invention, a polycrystalline silicon film with a large grain size can be formed with a simpler manufacturing process. As a result, it has become possible to form high-performance semiconductor elements on insulating amorphous materials, making it easy to manufacture large, high-resolution liquid crystal display panels, high-speed, high-resolution contact image sensors, 3D ICs, etc. can now be formed.

In addition to the TPT shown in the embodiment of FIG. 1, the present invention can be applied to insulated gate semiconductor devices in general, as well as photovoltaic devices such as bipolar transistors, static induction transistors, solar cells, and optical sensors. This is an extremely effective manufacturing method when forming a semiconductor element such as a conversion element using a polycrystalline semiconductor as the element material.

[Brief explanation of drawings]

FIGS. 1(a) to 1(d) are process diagrams for manufacturing a semiconductor device in an embodiment of the present invention. FIGS. 2(a) to 2(e) are schematic diagrams of a temperature raising method in an example of the present invention. Insulating amorphous material Silicon layer Polycrystalline silicon layer Gate insulating film Gate electrode Source/drain region Interlayer insulating film Contact hole Wiring Applicant Seiko Epson Co., Ltd. Attorney Kizo Suzuki (and one other person) (a) (b) (c) 101 Peeling 1 → Seedling 9 powder 4 ingredients Chart Time Figure 2 (c) Time Figure 2 (d) Time Figure 2 (a) Time Figure 2 (b) Time Figure 2(e)

Claims (1)

[Claims] 1) At least (a) a step of forming a semiconductor layer mainly composed of silicon on an insulating amorphous material, and (b) a step of raising the temperature to a predetermined heat treatment temperature over a certain period of time. A method for manufacturing a semiconductor device, comprising: 2) (a) A step of forming a semiconductor layer mainly composed of silicon on an insulating amorphous material, (b) A step of growing crystals of the semiconductor layer by heat treatment, etc., (c) A higher predetermined amount than step (b). 1. A method of manufacturing a semiconductor device, comprising at least the step of treating the semiconductor layer at a heat treatment temperature of . 3) The method of manufacturing a semiconductor device according to claim 2, wherein step (c) includes at least the step of raising the temperature to a predetermined heat treatment temperature over a certain period of time. 4) Manufacturing the semiconductor device according to claim 1 or claim 3, wherein in the step of raising the temperature to the predetermined heat treatment temperature over a certain period of time, there is a stage where the temperature increase rate is slower than 20° C./min. Method. 5) The method of manufacturing a semiconductor device according to claim 4, wherein the predetermined heat treatment temperature is 700°C to 1200°C. 6) The method of manufacturing a semiconductor device according to claim 5, wherein the step of raising the temperature to the predetermined temperature or the step subsequent thereto is part of a step of forming a gate insulating film.