JPH04143666A - Signal display device - Google Patents

Abstract

PURPOSE:To enable each input signal at different times to be compared easily by shifting a display position in a direction of time base of an input signal waveform of a plurality of channels to be memorized independently and freely for each channel. CONSTITUTION:When an AND gate 24 is forbidden, a trigger signal is fed to a delay counter 25 for setting clock pulses to be counted to a set value and for feeding a delay trigger signal to a control circuit 26, a selection memory circuit 3 becomes a READ mode and a multiplexer 21 selects an ADDER circuit. Then, a clock signal is counted 17, an address signal is fed to a circuit 20, a carrier signal is fed to a multiplexer 19 for enabling bias latch circuits 15 and 16 to be selected alternately for each generation of signal and a 2-channel signal memorized in the circuit 3 to be read out alternately for display. In this case, circuits 15 and 16 read out what is obtained by adding one to a memorized final address when writing is stopped for setting a start address. Therefore, by changing the memorized data, both or one signal waveform can be shifted in horizontal (time base) direction freely for easy comparison.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a signal display device that stores input signals in a storage circuit, reads out the stored input signals, and displays them on a display.

[Prior Art] A signal display device such as a transient digitizer is a device used to digitize an analog signal waveform and process it on a computer, or convert it back to an analog signal and observe it on a display. It is essential for observing and analyzing transient phenomena and mechanical vibrations.

The operation of such a conventional device is performed as follows. In the write mode, input signals are analog-to-digital converted and sequentially stored in a storage circuit (for example, a random access memory RAM), and in the read mode, the digital signals stored in the RAM are sequentially read out. This read signal is converted back into an analog signal and displayed on a display.

This applies even if the input signal is a logic signal.
They are the same except for digital conversion and digital-to-analog conversion.

[Problems to be Solved by the Invention] In a conventional signal display device, when input signals of a plurality of channels are stored and these stored input signals are displayed on a display, the display position of the input signal for each channel is It was possible to control only the amplitude axis direction (Y direction). However, the display position in the time axis direction (X direction) could not be controlled unless all channels were at the same time. Therefore, temporally different input signals of different channels could be controlled. It was inconvenient to compare the parts.

Therefore, an object of the present invention is to provide a signal display device that can independently control the display position of input signals of a plurality of channels in the time axis direction for each channel. A signal display device comprising a memory circuit for storing input signals of channels, a counter for generating an address signal for the memory circuit, and a display for displaying the input signals stored in the memory circuit, the signal display device having multiple channels. a plurality of bias latch circuits provided for each channel, a changing means for changing the memory contents of the bias latch circuits, and an addition means for adding the address signal generated by the counter and the memory contents of the bias latch circuits. It further includes a circuit.

[Operation] The signal display device of the present invention addresses a storage circuit using the output signal of the adder circuit, reads out input signals stored in the storage circuit, and displays these read input signals on the display. Then, the storage contents of the plurality of bias latch circuits are changed by the changing means to control the display position of the input signal displayed on the display in the time axis direction for each channel [Embodiment] FIG. FIG. 2 is a block diagram showing an embodiment of the present invention. FIG. 2 is a block diagram showing a part of FIG. 1 in detail. FIG. 1 shows a case where signal waveforms of two channels are observed, CHI and CH2 are the first channel and the second channel, respectively.
This is the channel input terminal. 1 is an input circuit including a buffer and an attenuator, 2 is an analog/digital (A
/D) Converter, 3 is a selection storage circuit having a selector, RAM, etc., 4 is an output circuit having a digital-to-analog converter, an output amplifier, etc., 5 is an output terminal, and 6 is connected to the output terminal 5 display device (e.g. cathode ray tube), 7
8 is a trigger circuit that generates a trigger signal in response to an input signal;
9 is a central processing unit (hereinafter referred to as "CPU"); 10 is a C
Read-only memory that stores PU9 processing procedures
(ROM), 11 is a RAM of the CPU, 12 is a keyboard (changing means) that issues various commands, and 13 is a clock generator that supplies clock signals to each circuit.

14 is a bus (bus line), and the part without an arrow indicates that it is bidirectional. Through these paths, the CPU 9 controls the clock frequency of the clock generator 13, controls the channel selection of the selector of the selective storage circuit 3, processes (for example, erases) data in the RAM of the selective storage circuit 3, and controls the trigger circuit. Trigger level and slope control for 7 is performed. In addition, 81 is
Read/write control lines 82 indicate addressing lines.

FIG. 2 is a block diagram showing the address control circuit 8 in FIG. 1 in detail. In the figure, bias latch circuits 15 and 16 store the address of the RAM of the selective storage circuit 3 related to when writing is stopped, and 15 is the first
16 is for the second channel. Also,
The memory contents of the bias latch circuits 15 and 16 are as follows:
It can be changed arbitrarily using the keyboard 13. The read counter 17 reads the RAM of the selective storage circuit 3 in the read mode.
The write counter 18 determines the address of the RAM of the selective storage circuit 3 in the write mode. The board 22 is an interface to the CPU 9, and the delay counter 25 is used to delay the trigger for a predetermined period of time as necessary, and is used when it is desired to also store the input signal after the trigger has occurred in the RAM. Multiplexer 19 alternately selects the outputs of bias latch circuits 15 and 16 for each cycle of count of read counter 17. The adder circuit 20 includes a multiplexer 19
The address of the bias latch circuit 15 or 16 selected in is algebraically added to the address from the read counter. The multiplexer 21 selects the output of the write counter 18 or the adder circuit 2o depending on the output of the control circuit 26 which is responsive to the output of the delay counter 25. Control circuit 23
is for triggering and enabling the AND gate 24 in response to a carry signal of the write counter 18, which will be described later, and the output of the boat 22.

Next, the operation of the embodiment shown in FIGS. 1 and 2 will be explained. Assuming that the device is now in the read mode, depending on the operation of the read counter 17, the multiplexer 19
Bias latch circuits 15 and 16 are selected alternately, and multiplexer 21 selects adder circuit 20. According to the output of this multiplexer 21, R of the selection storage circuit 3
An address in AM is selected and data stored in this RAM is read out. The operation in this read mode will be described in detail later. During this time, the control circuit 23 operates the AND gate 2
4 is prohibited.

When the reset/start key on the keyboard 12 is operated, the CPU 9 detects this and controls each circuit as follows according to the processing procedure stored in the ROM 10. First, the CPU 9 instructs the selector of the selection storage circuit 3 to apply a ground potential to the data input terminal of the RAM via the bus 14, and also instructs the control circuit 2 via the bus 14.
6 commands signal line 81 to generate a write mode signal. This write mode signal causes the selective storage circuit 3 to
The RAM changes from the read mode to the write mode, and the multiplexer 21 selects the write counter 18. Further, the CPU 9 supplies a start signal to the write counter 18 via the bus 14 and the boat 22, so that the counter 18 starts counting the clock signal and outputs the output signal as an address signal via the multiplexer 21. It is supplied to RA of the selective storage circuit 3. Therefore, this RAM
writes logic “0” (ground level). Since the maximum count value of the write counter 18 and the storage capacity of the RAM are equal,
When logic "o" is written to all storage elements of the RAM, that is, when erasure of the old signal (first data) stored in the RAM is completed, the write counter 18 generates a first carry signal.

Note that when erasing the RAM of the circuit 3, logic "1" may be written instead of logic "0". Alternatively, the address signal and data may be sent directly from the CPU 9 to the RAM to erase the RAM, and in this case, the write counter 18 is not used.

The first carry signal from the write counter 18 is sent to the CPU 9 via the boat 22 and the bus 14. C
When the PU 9 detects this carry signal, it instructs the selector of the selection storage circuit 3 to supply the output of the analog-to-digital conversion l#2 to the RAM via the bus 14, and also A second start signal, that is, a first control signal, is supplied to the write counter 18. Therefore, the RAM of the circuit 3 writes the digitized input signal, that is, the second data, in accordance with the address signal of the write counter 18 from the multiplexer 21. During this time, similarly to the read mode and the erase mode,
The AND gate 24 is inhibited by the control circuit 23.

When the second data is written to the RAM of the circuit 3 for one cycle, the write counter 18 generates a second carry signal and sends it to the CPU 9 via the boat 22 and the bus 14. The CPU 9 determines that this carry signal is the second time, and sends the carry signal to the control circuit 2 via the bus 14 and the boat 22.
3 to enable the AND gate 24 to trigger. When the AND gate 24 is set to trigger enable, the trigger signal generated by the trigger circuit 7 is always supplied to the delay counter 25. Also, C
In response to the second carry signal, the PU 9 again supplies a start signal to the write counter 18 via the bus 14 and the boat 22, and the RAM of the selective storage circuit 3 is successively rewritten with new second data. This operation is performed by the trigger circuit 7
is repeated until a trigger signal is generated. The above-described # control of the write counter 18 and control circuit 23 may be performed by hard logic instead of being performed by the CPU 9.

Hard logic has the advantage of being able to process faster than a CPU.

When a trigger signal is generated after trigger enable, this trigger signal is provided to delay counter 25 through AND gate 24 . The delay counter 25 is controlled by the CPU 9 and the bus 14 according to the settings on the keyboard 12, and after the output of the AND gate 24 is generated, the delay counter 25 counts the clock pulses up to the set value and outputs the delay signal as the second control signal. Generate a trigger signal. In the pre-trigger mode, in which a signal before the trigger signal is generated, the set value of the delay counter 25 is set to zero, so that the delay counter 25 generates the trigger signal immediately after the trigger circuit 7 generates the trigger signal. In modes other than the flash trigger mode, as described above, the set value of the delay counter 25 is set to a value other than zero, and depending on this set value, the preceding and following trigger signals from the trigger circuit 7 can be arbitrarily stored in the RAM. In any case, it should be noted that in this embodiment, the output signal of the delay counter 25, rather than the trigger signal from the trigger circuit 7, becomes the second control signal.

The delay trigger signal (second control signal) of the delay counter 25 is supplied to the write counter 18 as a stop signal, and causes the write counter 18 to stop counting. bias·
Since the address signal of the write counter 18 and the output of the delay counter 25 are supplied to the latch circuits 15 and 16, the address signal of the write counter 18 when the output of the delay counter 25 is generated, that is, the selection memory circuit 3
The final write address of the RAM is stored. Further, the delay trigger signal of the delay counter 25 is also supplied to the control circuit 26, the signal line 81 changes from the write mode to the read mode, the RAM of the circuit 3 changes to the read mode, and the multiplexer 21 selects the adder circuit 20. . Furthermore, the read counter 17 starts counting the clock signals, supplies the address signal to the adder circuit 20, and supplies the carry signal to the multiplexer 19, so that the bias latch circuits 15 and 16 are alternately connected each time the carry signal occurs. select. This is because two channels of signals are stored in the RAM of circuit 3, but the output circuit 4 has only one digital-to-analog converter, so the first and second channels must be read out alternately. It's for a reason. Therefore, when only the first channel signal is stored, the multiplexer 19 should always select the bias latch circuit 15.

On the other hand, the final address stored in the bias latch circuits 15 and 16 is transferred to the RAM II of the CPU via the bus 14.
1 is algebraically added by the CPU 9 to the bias latch circuit 15 via the bus 14.
and stored in 16. The newly memorized address is
This is the start address for RAM writing. However, if the write counter 18 stops counting at the next clock signal after the stop signal is supplied, and the bias latch circuits 15 and 16 memorize the address at this time, then the CPU
Addition of 1 becomes unnecessary. Since the adder circuit 20 algebraically adds this start address and the address signal of the read counter 17, the output of the adder circuit 20 is added to the address signal of the read counter 17.
When the address signal No. 7 is zero, it becomes the RAM write start address. In this way, the address of the RAM of the circuit 3 is selected according to the output of the adder circuit 20, and the read mode is entered. Note that when the address signal of the read counter 17 is zero, the horizontal display position of the display 6 is at the left end.

In this way, one cycle before the trigger signal is generated (when the delay counter 25 is set to zero) is displayed on the display 6.
The displayed content is always new second data, and is never mixed with old first data, even if a trigger signal is generated within one cycle after trigger enable and writing is stopped.

In some cases, the erase mode in the above operation may be omitted. Note that the CPU 9, the boat 22, the control circuit 23, and the AND gate 24 constitute a prohibition circuit.

The signal waveforms of the two channels displayed on the display 6 are:
For example, as shown in Figure 3A, these two waveforms conventionally can move independently in the vertical direction;
Because a common sweep signal was used for the two channels, they could not move separately in the horizontal (time axis) direction, but only together. Therefore, as shown in FIG. 3A, two large pulse waveforms that are time-shifted cannot be viewed together in time. In the figure, CHI and CH2 are
The first and second channels are shown respectively.

However, in the present invention, as shown in FIG. 3B and C,
The signal waveforms of the two channels can be freely and independently shifted in the horizontal direction, and the entire waveform can always be displayed. In other words, since the start address for reading is set by adding 1 to the address stored in the bias latch circuits 15 and 16 at the time of stop of writing, if the stored contents of the bias latch circuit 16 are changed, the second The starting point when reading the channel changes,
The screen is displayed as shown in FIG. 3B. Bias latch circuit 15
If the stored contents are changed, the starting point when reading the first channel changes, and the display is displayed as shown in FIG. 3C. It is thus possible to freely move both or one of the signal waveforms in their entirety in the horizontal direction. Bias latch circuit 15.
16, the value set by the keyboard 12, which is the changing means, may be sent to the bias latch circuit via the CPU 9 and the bus 14, or the value set by the keyboard 12, which is the changing means, may be sent to the bias latch circuit, or while a specific key on the keyboard 12 is held down. , the CPU 9 may add or subtract one value from the stored contents of the bias latch circuits 15 and 16 one by one.

Furthermore, even if the storage contents of the bias latch circuit 15 or 16 are changed and the display is moved in the horizontal direction, the entire capacity of the RAM of the selection storage circuit 3 is read out, so all the That is, data for one cycle is always displayed. In this case, it must be noted that the time relationships of the displayed waveforms are partially reversed.

Note that the present invention is not limited to the above-described embodiments, and various modifications and changes can be made without departing from the gist of the invention as set forth in the claims. For example, when adding 1 to the memory contents of the bias latch circuit, adding 1 may be omitted in some cases. In this case, the read counter starts counting from 0001. Also,
The present invention can be applied to logic analyzers as well as transient digitizers. Furthermore, the AND gate 24 may be provided after the delay counter 25.

[Effects of the Invention] As explained above, according to the present invention, when displaying input signals of multiple channels stored in a storage circuit on a display, the display position in the time axis direction can be controlled independently for each channel. . Therefore, temporally different portions of each input signal can be easily compared.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the invention, FIG. 2 is a detailed block diagram of a part of the invention, and FIG. 3 is a diagram showing an example of signal display according to the invention. 3: Selection storage circuit 6: Display 12: Keyboard (changing means) 15.16: Bias latch circuit 17: Read counter 20: Addition circuit

Claims (1)

[Scope of Claims] A signal comprising: a memory circuit that stores input signals of a plurality of channels; a counter that generates an address signal for the memory circuit; and a display that displays the input signal stored in the memory circuit. In the display device, a plurality of bias latch circuits are provided for each of the plurality of channels, a changing means for changing the memory contents of the bias latch circuit, and an address signal generated by the counter and the bias latch circuit. further comprising an adder circuit that adds the contents stored in the latch circuit, the output signal of the adder circuit addresses the storage circuit, reads the input signal stored in the storage circuit, and reads the input signal stored in the storage circuit; is displayed on the display, and the changing means changes the memory contents of the plurality of bias latch circuits to control the display position of the input signal displayed on the display in the time axis direction for each channel. A signal display device characterized by: