JPH04143665A - Signal memory method - Google Patents

Abstract

PURPOSE:To prevent an old data and a new data from being memorized together by disabling supply of a trigger signal or nullifying a second control signal until an address control signal specifies all addresses. CONSTITUTION:A CPU 9 outputs a first control signal to an address control circuit 8 and a RAM of selection memory circuit 3 writes a new data. When data is written for one cycle, the CPU 9 instructs the circuit 8 to trigger-enable AND gate for allowing a trigger signal of a trigger circuit 7 to be supplied to a delay counter. However, the RAM rewrites new data continuously and repeats it until the trigger signal is generated. After trigger enable, the delay counter which receives trigger signal counts clock pulses, outputs delay trigger signal which is a second control signal, and then stops writing operation or the AND gate is provided at a later stage of the delay counter, the second control signal is nullified until the circuit 8 specifies all addresses, and writing operation is stopped when the signal is valid.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a signal storage method of a storage device mainly used in a transient digitizer (waveform storage device) or the like.

[Prior Art] A transient digitizer is used to digitize, for example, an analog signal waveform, process it with a computer, etc.
This is a device used to convert the signal back to analog and observe it on a display device.It is used for observing and observing high-speed transient phenomena, mechanical vibrations, etc.
It is essential for analysis.

The operation of such a device is as follows. In write mode, the input signal is converted from analog to digital and stored in a storage circuit (e.g. random access memory RAM).
), and in the read mode, the digital signals stored in this RAM are read out sequentially.However, in any mode, when writing to the entire capacity of the RAM or reading the entire capacity, the writing or Read from the beginning and repeat this from now on. One cycle of this repetition is called one cycle. To stop reading RAM and start writing new data, operate the reset/start switch manually or automatically. to switch the device from read mode to write mode.

In the BRITRIGGER mode, which stores the analog signal waveform before the trigger, writing to RAM is stopped by the trigger signal, and the data previously written to the RAM is read. When a signal is received, the write mode automatically stops. This trigger signal can also be generated manually.

To explain the above-mentioned operation in the pre-trigger mode using a diagram, FIG. 1A shows a case where a trigger is triggered (writing is stopped) after one or more cycles have elapsed after the reset start. Further, FIG. 1B shows a case where the trigger is triggered in the flash trigger mode before one cycle has passed after the reset start. In the figure, R indicates read mode and W indicates write mode. In the case of Fig. 1A, a trigger occurs (write stop) no matter what point the reset or start occurs while reading the old first data from RAM.
Since more than one cycle has passed, the RAM
New second data is written to the entire capacity of . Therefore, after the trigger (after stopping writing), only the second data is read.

[Problem to be solved by the invention] However, in the case of FIG.
There is no time for data to be written, and the first data and second data coexist in the RAM. Therefore, after the trigger in the pre-trigger mode, the portion after the first data and the portion before the second data are read out. In this case, the first and second data are mixed, making it difficult to measure only the second data. Even in cases other than the britrigger mode, this phenomenon occurs in the same way as in the britrigger mode, if the writing operation of new data in the RAM is stopped within one cycle after the start of writing.

Therefore, an object of the present invention is to provide a signal storage method that can prevent old first data and new second data from being stored in a mixed manner in a storage circuit in a signal storage device.

[Means for Solving the Problems] The present invention includes a memory circuit that starts writing an input signal in response to a first control signal, an address control circuit that sequentially specifies addresses of this memory circuit, and a trigger signal that starts writing an input signal in response to an input signal. A trigger circuit generates a clock pulse, and when the trigger signal generated by this trigger circuit is supplied, it starts counting clock pulses, and after counting a set number of clock pulses (including zero), a second control signal is generated. A signal storage method for a signal storage device comprising a delay counter that generates a delay counter. In the first method, after the first control signal is generated, the address control circuit specifies all addresses of the storage circuit.

The trigger signal generated by the trigger circuit is prohibited from being supplied to the delay counter, and when the delay counter generates the second control signal, the write operation of the storage circuit is stopped. In the second method, after the first control signal is generated, the second control signal generated by the delay counter is invalidated until the address control circuit specifies all addresses in the storage circuit, and the second control signal generated by the delay counter is When the control signal is valid, the write operation of the memory circuit is stopped.

[Effect] The present invention will now be described in detail with reference to FIGS. 1C and 1D.

FIG. 1C shows one cycle of leap after the first control signal is generated (in this case, after the reset start) and the memory circuit (RAM).
), the trigger is enabled after writing the digitized input signal, and the second control signal is received within one cycle thereafter (in the britrigger mode, the trigger is triggered). In addition, the first scheme erases the RAM data in one cycle after the reset/start,
After that, during one cycle after receiving the first control signal, the digitized input signal is written to the RAM, and then,
The case where the trigger is enabled and the second control signal is received before one cycle has passed (in the pre-trigger mode, the case is triggered) is shown. Note that in the figure, E indicates the erase mode. In either case, after a reset start, the storage operation is not stopped before new data is written to the RAM for one cycle, i.e., the second control signal is inhibited until all addresses in the RAM are specified; The conventional drawbacks mentioned above can be avoided.

In particular, the first diagram is effective in the slow mode used when the input signal changes very slowly. In the slow mode, since the clock frequency is very low, it is possible to read while writing by time division. However, if the data is not erased after the reset/start, the old 1st data and the new 2nd data will be displayed on the CRT at the same time during the first write cycle, making it hard to see. The data in the RAM is erased during the next one cycle.

[Embodiment] FIG. 2 is a block diagram showing an embodiment of a signal storage device using the present invention, and FIG. 3 is a block diagram showing a part of FIG. 2 in detail. FIG. 2 shows a case where signal waveforms of two channels are observed, CH1 and CH2 are input terminals of the first channel and the second channel, respectively. l
is an input circuit having a buffer, an attenuator, etc.; 2 is an analog-to-digital converter; 3 is a selection storage circuit having a selector, RAM, etc.; 4 is an output circuit having a digital-to-analog converter, an output amplifier, etc. , 5 is an output terminal; 6 is a display device (for example, a cathode ray tube) connected to the output terminal 5; 7 is a trigger circuit that generates a trigger signal in response to an input signal; 8 is a circuit mainly used for writing and reading; An address control circuit 9 designates the address of the RAM of the selective storage circuit 3, and 9 is a central processing unit (hereinafter referred to as rcPUJ).
, IO is a read-only memory (ROM) that stores the processing procedure of the CPU 9, 11 is a RAM of the CPU, 12
13 is a keyboard that issues various commands, and 13 is a clock generator that supplies clock signals to each circuit. 14 is the bus (bus line), but the part without the arrow is
Indicates that it is bidirectional. Through these buses, C
The PU9 controls the clock frequency of the reflock generator 13, controls the channel selection of the selector of the selective storage circuit 3, processes (for example, erases) data in the RAM of the selective storage circuit 3, and controls the trigger level and the trigger level for the trigger circuit 7. Slope control is performed. Note that 81 indicates a read/write control line, and 82 indicates an address designation line.

FIG. 3 is a block diagram showing details of the address control circuit 8 in FIG. 2. In FIG. 0, bias latch circuits 15 and 16 store the address of the RAM of the related selection storage circuit 3 when writing is stopped. 15 is the first
16 is for the second channel. The read counter 17 serves as a reference for the address of the RAM of the selected storage circuit 3 in the read mode, and the write counter 18 determines the address of the RAM of the selected storage circuit 3 in the write mode. The board 22 is an interface to the CPU 9, and the delay counter 25 is used to delay the trigger for a predetermined period of time if necessary, and is used when it is desired to also store the input signal after the trigger has occurred in the RAM. Multiplexer 19 alternately selects the outputs of bias latch circuits 15 and 16 for each cycle of count of read counter 17. The adder circuit 20 includes the bias latch circuit 15 or 16 selected by the multiplexer 19.
algebraically add the address from the read counter. Multiplexer 21 selects the output of write counter 18 or adder circuit 20 depending on the output of control circuit 26 which is responsive to the output of delay counter 25 . The control circuit 23 triggers and enables the AND gate 24 in response to a carry signal of the write counter 18 (described later) and the output of the boat 22.
This is to enable the trigger signal to be received.

Next, the operation of the embodiment shown in FIGS. 2 and 3 will be explained with reference to the first diagram. Assuming that the device is now in the read mode, depending on the operation of the read counter 17, the multiplexer 19 controls the bias latch circuits 15 and 1.
6 is alternately selected, and the multiplexer 21 selects the adder circuit 2
Select 0.

The address of the RAM of the selective storage circuit 3 is selected according to the output of the second multiplexer, and the data stored in this RAM is read out. The operation of this read mode is as follows:
This will be described in detail later. During this time, the control circuit 23 prohibits the AND gate 24.

When the reset/start key on the keyboard 12 is operated, the CPU 9 detects this and controls each circuit as follows according to the processing procedure stored in the ROM IO. First, the CPU 9 instructs the selector of the selection storage circuit 3 to apply a ground potential to the data input terminal of the RAM via the bus 14, and also instructs the control circuit 2 via the bus 14.
6 commands signal line 81 to generate a write mode signal. This write mode signal causes the selective storage circuit 3 to
The RAM changes from the read mode to the write mode, and the multiplexer 21 selects the write counter 18. Further, the CPU 9 supplies a start signal to the write counter 18 via the bus 14 and the boat 22, so that the counter 18 starts counting the clock signal and outputs the output signal as an address signal via the multiplexer 21. It is supplied to RA of the selective storage circuit 3. Therefore, this RAM
writes logic "0" (ground level), since the maximum count value of the write counter 18 and the storage capacity of the RAM are equal,
When logic "0" is written to all storage elements of the RAM, that is, when erasure of the old signal (first data) stored in the RAM is completed, the write counter 18 generates a first carry signal.

Note that when erasing the RAM of the circuit 3, a logic "1" may be written instead of a logic "0". Alternatively, the address signal and data may be sent directly from the CPU 9 to the RAM to erase the RAM, and in this case, the write counter 18 is not used.

The first carry signal from the write counter 18 is sent to the CPU 9 via the boat 22 and the bus 14. C
When the PU 9 detects this carry signal, it instructs the selector of the selective storage circuit 3 to supply the output of the analog-to-digital converter 2 to the RAM via the bus 14, and also writes via the bus 14 and the port 22. counter 1
8 is supplied with a second start signal, that is, the first control signal. Therefore, the RAM of circuit 3 is
During this period, the AND gate 24 is disabled by the control circuit 23, as in the read mode and the erase mode. It is in.

When the second data is written to the RAM of the circuit 3 for one cycle, the write counter 18 generates a second carry signal and sends it to the CPU 9 via the boat 22 and the bus 14. The CPU 9 determines that this carry signal is the second time, and sends the carry signal to the control circuit 2 via the bus 14 and the boat 22.
3 to enable the AND gate 24 to trigger. When the AND gate 24 is set to trigger enable, the trigger signal generated by the trigger circuit 7 is always supplied to the delay counter 25. Also, C
In response to the second carry signal, the PU 9 again supplies a start signal to the write counter 18 via the bus 14 and the boat 22, and the RAM of the selective storage circuit 3 is successively rewritten with new second data. This operation is performed by the trigger circuit 7
is repeated until a trigger signal is generated. The above-mentioned write counter 18 and control circuit 23 may be controlled by hard logic instead of by C and PU 9.

Hard logic has the advantage of being able to process faster than a CPU.

When a trigger signal is generated after trigger enable, this trigger signal is provided to delay counter 25 through AND gate 24 . The delay counter 25 is controlled by the CPU 9 and the bus 14 according to the settings on the keyboard 12, and after the output of the AND gate 24 is generated, the delay counter 25 counts the clock pulses up to the set value and outputs the delay signal as the second control signal. Generate a trigger signal. In the above-described pre-trigger mode in which a signal before the trigger signal is generated, the set value of the delay counter 25 is set to zero so that the delay counter 25 generates the trigger signal immediately after the trigger circuit 7 generates the trigger signal. In modes other than the flash trigger mode, as described above, the set value of the delay counter 25 is set to a value other than zero, and depending on this set value, the preceding and following trigger signals from the trigger circuit 7 can be arbitrarily stored in the RAM. In any case, it should be noted that in this embodiment, the output signal of the delay counter 25, rather than the trigger signal from the trigger circuit 7, becomes the second control signal.

The delay trigger signal (second control signal) of the delay counter 25 is supplied to the write counter 18 as a stop signal, and causes the write counter 18 to stop counting. bias·
Since the address signal of the write counter 18 and the output of the delay counter 25 are supplied to the latch circuits 15 and 16, the address signal of the write counter 18 when the output of the delay counter 25 is generated, that is, the selection memory circuit 3
The final write address of the RAM is stored. Further, the delay trigger signal of the delay counter 25 is also supplied to the control circuit 26, the signal line 81 changes from the write mode to the read mode, the RAM of the circuit 3 changes to the read mode, and the multiplexer 21 selects the adder circuit 20. . Furthermore, the read counter 17 starts counting the clock signals, supplies the address signal to the adder circuit 20, and supplies the carry signal to the multiplexer 19, so that the bias latch circuits 15 and 16 are alternately connected each time the carry signal occurs. select. This is because two channels of signals are stored in the RAM of circuit 3, but the output circuit 4 has only one digital-to-analog converter, so the first and second channels must be read out alternately. It's for a reason. Therefore, when only the first channel signal is stored, the multiplexer 19 should always select the bias latch circuit 15.

On the other hand, the final address stored in the bias latch circuits 15 and 16 is transferred to the RAM II of the CPU via the bus 14.
1 is algebraically added by the CPU 9 to the bias latch circuit 15 via the bus 14.
and stored in 16. The newly memorized address is
This is the start address for RAM writing. However, if the write counter 18 stops counting at the next clock signal to which the stop signal is supplied, and the bias latch circuits 15 and 16 memorize the address at this time, then the CPU
Addition of 1 becomes unnecessary. Since the adder circuit 20 algebraically adds this start address and the address signal of the read counter 17, the output of the adder circuit 20 is added to the address signal of the read counter 17.
When the address signal No. 7 is zero, it becomes the RAM write start address. In this way, the address of the RAM of the circuit 3 is selected according to the output of the adder circuit 20, and the read mode is entered. Note that when the address signal of the read counter 17 is zero, the horizontal display position of the display device 6 is at the left end.

In this way, in the flash trigger mode where the delay counter 25 is set to zero, one cycle before the trigger signal is generated is displayed on the display device 6, but the displayed content is the same as the one after the trigger is enabled as shown in the first figure. Even if a trigger signal is generated within one cycle and writing is stopped, a new second
data, and will not be mixed with old first data.

In some cases, the erase mode in the above operation may be omitted. Note that the CPU 9, the board 22, the control circuit 23, and the AND gate 24 constitute a prohibition circuit.

Note that the present invention is not limited to the above-described embodiments, and various modifications and changes can be made without departing from the gist of the invention as set forth in the claims. For example, when adding 1 to the stored contents of the bias latch circuit, adding 1 may be omitted in some cases; in this case, the read counter starts counting from 0001. Also,
The present invention can be applied to logic analyzers as well as transient digitizers.

Furthermore, the AND gate 24 may be provided after the delay counter 25. In this case, after the first control signal is generated, until the address control circuit 8 specifies all addresses of the storage circuit,
invalidating the second control signal generated by the delay counter 25;
When the second control signal generated by the delay counter 25 is valid, the write operation of the memory circuit is stopped.

[Effects of the Invention] As explained above, according to the present invention, when an input signal is stored, the old signal and new signal do not coexist in the storage circuit after the writing operation of the new signal in the storage circuit is stopped.
Therefore, even if the contents stored in this memory circuit are displayed, old signals and new signals will not be displayed together.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of the operation of the conventional signal storage method and the present invention. FIG. 2 is a block diagram showing a signal storage device using the present invention. FIG. 3 is a detailed block diagram showing the address control circuit used in FIG. 2. It is a diagram. 3: Selection memory memory circuit 7: Trigger circuit 8 Near address control circuit 25; Delay counter

Claims (1)

[Scope of Claims] A memory circuit that starts writing an input signal in response to a first control signal, an address control circuit that sequentially specifies addresses of the memory circuit, and a trigger circuit that generates a trigger signal in response to the input signal. When the trigger signal generated by the trigger circuit is supplied, it starts counting clock pulses, and after counting a set number (including zero) of the clock pulses,
and a delay counter that generates a second control signal, wherein after the first control signal is generated, the trigger circuit continues to operate until the address control circuit specifies all addresses of the storage circuit. Prohibiting the generated trigger signal from being supplied to the delay counter, and stopping the write operation of the storage circuit when the delay counter generates a second control signal; or, after generation of the first control signal, Until the address control circuit specifies all addresses of the storage circuit, the second control signal generated by the delay counter is invalidated, and when the second control signal generated by the delay counter is valid, the second control signal generated by the delay counter is valid. A signal storage method characterized by stopping a write operation of a circuit.