JPH04142834A - Clock signal changeover device - Google Patents

Abstract

PURPOSE:To select one clock signal among input clock signals at a proper time as required by generating clock interrupt information simulatingly in a similar form as a clock interruption detection circuit so as to generate a control signal to select an optional clock signal. CONSTITUTION:A clock interruption detection circuit 2 detects whether or not inputted clock signals CK1-CK4 are interrupted and sends sets of detection information 1A-4A to an A/M(auto/manual) selector control circuit 3 and an M selector circuit 4 generates sets of information 1B-4B to interrupt a signal other than a designated clock signal according to the designation of a selected clock signal. Then the A/M selector control circuit 3 selects any of the sets of clock interrupt information 1A-4A, 1B-4B according to the command to generate a selection control signal SC and a selector circuit 1 receives it to select a reference clock signal among the inputted clock signals CK1-CK4. Thus, as required, one clock signal is selected among the inputted clock signals CK1-CK4 at a proper time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Purpose of the Invention (Industrial Application Field) The present invention relates to a tarock signal switching device used, for example, in a synchronous terminal station of a so-called 5ONET (synchronous optical communication network) system.

(Prior art) In a synchronous optical communication network system, each synchronous terminal station receives network synchronization clock signals of the N (Norma I: Normal) system and the E (Emergency) system, or a network synchronization clock signal prepared as a backup. Select a reference clock signal from among other clock signals (often a built-in clock signal using a temperature-compensated crystal oscillator or a clock signal provided by the device's loop) and synchronize to that clock signal. We plan to generate and use clock signals of various frequencies. FIG. 3 shows the configuration of a conventional clock signal switching device that selects such a reference clock signal.

That is, this device is composed of a selector circuit 1 and a clock interruption detection circuit 2. The prepared N-system, E-system, built-in clock, and other signals are input to both the selector circuit 1 and the clock disconnection detection circuit 2.

The clock disconnection detection circuit 2 detects the disconnection state of the input clock signal and sends the information to the selector circuit 1. The selector circuit 1 selects a reference clock signal from among the input clock signals based on the clock interruption information sent from the clock interruption detection circuit 2.

By the way, when inspecting a synchronous terminal station, it is necessary to select one clock signal from among the above-mentioned various input clock signals and check the operation of the terminal station.

Additionally, information about which clock signal is currently selected as a reference is normally sent to the alarm system, but even when checking the operation of this alarm system, it is necessary to select one clock signal from among the input clock signals at the appropriate time. Is required.

However, in the circuit configuration of the conventional clock signal switching device as shown in FIG. When inspecting a terminal station, it is not possible to manually switch the clock signal in a timely manner. Therefore, a problem arises in that it is not possible to select a clock signal and check the operation of the terminal station.

(Problems to be Solved by the Invention) As described above, in the conventional clock signal switching device,
When inspecting a synchronous terminal station, it is not possible to switch the necessary input clock signals in a timely manner, and it is not possible to select an arbitrary clock signal to check the operation of the terminal station.

The present invention has been made to solve the above-mentioned problems, and therefore, the clock 21. It is an object of the present invention to provide a lock signal switching device that allows a signal to be selected.

[4F4 components of the invention (Means for solving the problem)] In order to achieve the above [1], the clock signal switching device according to the present invention detects whether each of a plurality of taro clock signals is in an off state or not. a clock disconnection detection circuit that generates clock disconnection information; a pseudo clock disconnection generation means that generates pseudo clock disconnection information that disconnects other than a desired clock signal among the plurality of clock signals; and the clock disconnection detection circuit and the pseudo clock. Information selection means for selecting one of the outputs of the cutoff generation means in response to an external command, and clock signals to be selected in accordance with a predetermined priority based on the tally cutoff information selected by this means. , comprising a selector control means for generating a corresponding selection control signal, and a selector circuit inputting the plurality of clock signals and selectively outputting a clock signal according to the selection control signal output from the selector control means. configured.

(Function) In the clock signal switching device having the above configuration, when selecting the normal usage state, the information selection means selects the output of the clock disconnection detection circuit, and the selector control means selects the output of the clock disconnection detection circuit.
Identifying a clock signal to be selected according to a predetermined priority based on the selected clock disconnection information, generating a corresponding selection control signal, sending this to a selector control means, and specifying it with the selection control signal. The clock signal is selectively output. Further, when it is desired to selectively output an arbitrary clock signal, the information selection means selects the output of the pseudo clock disconnection generation means, and the selector control means selects the clock signal to be selected based on the selected pseudo clock disconnection information. Identifying the signal and generating the corresponding selection control signal;1. This is sent to the selector control means to selectively output a desired clock signal designated by the selection control signal.

(Embodiment) An embodiment of the present invention will now be described with reference to FIGS. 1 and 2. However, in FIG. 1, the same parts as those in FIG. 3 are designated by the same number 71 and will be explained.

Figure 1 shows its basic structure (,11).To keep the explanation simple here, the N system clock signal CK
1. It is assumed that an E system lock signal CK 2, a loop system clock signal CK 3, and a built-in clock signal CK 4 are prepared. These human input/tsuku signals CKI~
CK 4 is selector circuit 1 and clock disconnection detection circuit 2
is input to both. The clock disconnection detection circuit 2 detects whether or not each of the four inputted clock signals is disconnected, and sends the detection information IA to 4A to the A/M (auto/manual) selector control circuit 3.

7J, this A/lvl selector control circuit 3i:
Information from the M (manual) selector control circuit 4 is also sent. This M selector circuit 4 generates the to/M mode switching control signal CO according to the A/M mode designation instructed by manual operation, and also generates the to/M mode switching control signal CO in accordance with the designation of the clock signal to be selected. It creates information (pseudo clock disconnection information) 1B to 4B that disconnects signals other than the specified clock signal in the format, and these A
The /M/M mode IJ switching sub-control signal Co and clock interruption information 1B to 4B are sent to the A/M selector control circuit 3.

The A/M selector control circuit 3 transmits the clock interruption information I from the clock interruption detection circuit 2 and the M selector control circuit 4 to 4A, IB in response to the A/M mode switching control signal C.
-4B. Then, a selection control signal SC is generated according to this information and a predetermined priority order, and sent to the selector circuit 1. The selector circuit 1 receives the selection control signal SC and outputs four input clock signals CK.
Select a reference clock signal from CK1 to CK4.

FIG. 2 shows a specific configuration of the clock signal switching device having the above configuration. However, in FIG. 2, the same parts as in FIG. 1 are designated by the same reference numerals, and their explanations will be omitted.

That is, the selector circuit 1 of this device is composed of a 4ch (channel) multiplexer, which manually inputs 2-bit address information AO and AI as the selection control signal SC, and selects the addressed one of the four input clock signals CK1 to CK4. It is designed to selectively output the clock signal of the channel.

Further, the A/M selector control circuit 3 includes a 2ch multiplexer 3] and an encoder 32.

In response to the switching control signal CO, the 2ch multiplexer 31 sends the clock disconnection information on the A channel side (the clock disconnection detection circuit 2 side) to 4A and the clock disconnection information 1B to 4B on the B channel side (the M selector control circuit 4 side). This is for selecting one of the clock interruption information IY selected here.
~4Y is sent to the encoder 32. This encoder 32 specifies the clock signal to be selected according to the priority order from the input clock disconnection information IY to 4Y, and creates corresponding address information AO, AI. As above 4ch
The signal is sent to a selector circuit 1, which is a multiplexer.

According to the above configuration, the apparatus shown in FIG. 1 can be easily realized using several or one existing IC.

In the above configuration, the control means will be explained.

First, if it is desired to operate normally in the auto mode, the M selector control circuit 4 is instructed to operate in the auto mode. At this time, from the M selector control circuit 4 to the A/M selector control circuit 3
Then, a switching control signal CO is sent to the information I from the clock interruption detection circuit 2 so as to select four people. The A/M selector control circuit 3 includes, in the 2ch multiplexer 31,
Disturbed by the switching control signal CO, the clock interruption information 18 to 4A from the clock interruption detection circuit 2 is selected, and the selected clock interruption information IY to 4Y is sent to the encoder 32. and,
In this encoder 32, the address information AO, Al, which becomes the selection control signal SC, according to a predetermined priority order.
is generated and sent to the selector circuit 1. As a result, the selector circuit 1 selects and outputs a reference clock signal from the four clock signals CK1 to CK4.

Next, when selecting a desired clock signal in manual mode, specify manual mode to the M selector control circuit 4 and specify the desired clock signal.

At this time, a switching control signal CO is sent from the M selector control circuit 4 to the A/M selector control circuit 3 so as to select information from the M selector control circuit 4, and a clock interruption signal that cuts off signals other than the desired clock signal is sent. Information IB-4B is sent. The A/M selector control circuit 3 selects the clock disconnection information 1B to 4B from the M selector control circuit 4 in the 2Ch multiplexer 31 based on the switching control signal CO, and sends the selected clock signal MiY to 4Y to the encoder 32. send. This encoder 32 outputs address information A, which is a selection control signal SC, so as to select a clock signal that is not disconnected.
O and AI are generated and sent to the selector circuit 1.

As a result, the selector circuit] receives four clock signals CK
A desired clock signal is selectively output from I to CK4.

Therefore, in the clock signal switching device having the above configuration, the M selector control circuit 4 creates pseudo clock loss information in the same format as the clock loss detection circuit 2, and the information is sent to the A
Since the control signal is sent to the /M selector control circuit 3 to select an arbitrary clock signal, it can be sent to the existing selector circuit 1 and the clock break detection circuit 2.
A/M selector control circuit 3 and M selector control circuit 4
By simply adding , any clock signal can be easily selected and output, thereby eliminating the need for complicated clock signal selection operations when checking the operation of the terminal station.

Although the number of input clocks is four in the above embodiment, the present invention is not limited to this, and can accommodate an even larger number of input clock signals. Alternatively, the direct mode switching signal co may be generated and input to the A/M selector control circuit 3.

Furthermore, although the specific configuration is shown in FIG. 2, it goes without saying that the present invention is not limited to this and can be realized with other logic circuit configurations.

[Effects of the Invention] As described above, the present invention provides a lock signal switching device that can select one clock signal from among manually operated clock signals when necessary based on the information of clock disconnection. I can do it.

[Brief explanation of the drawing]

FIG. 1 is a basic configuration diagram showing an embodiment of a clock signal switching device according to the present invention, FIG. 2 is a block circuit diagram showing a specific configuration of the same embodiment, and FIG. 3 is a conventional clock signal switching device. FIG. 2 is a block circuit diagram showing the configuration of FIG. Selector circuit, 2/Clock disconnection detection circuit, 3 A
/M selector control circuit, 31...2ch multiplexer, 32...encoder, 4...M selector control circuit, CK 1/N system clock signal, CK 29. . E system clock signal, CR2...Loop system lock signal) CK4...Built-in clock signal, Co...switching control signal, C...selection control signal.

Claims (2)

[Claims] (1) A clock disconnection detection circuit that detects whether or not each of a plurality of clock signals is disconnected and generates clock disconnection information, and a pseudo clock disconnection circuit that disconnects other than a desired clock signal among the plurality of clock signals. pseudo clock interruption generation means for generating information; information selection means for selecting the output of either the clock interruption detection circuit or the pseudo clock interruption generation means in accordance with an external command; and clock interruption information selected by this means. a selector control means for specifying a clock signal to be selected according to a predetermined priority based on the above and generating a corresponding selection control signal; A clock signal switching device comprising a selector circuit that selectively outputs a clock signal according to a control signal. (2) The information selection means is constituted by a two-channel multiplexer that uses the outputs of the clock interruption detection circuit and the pseudo clock interruption generation means as channel outputs, and selects one of the outputs in accordance with an external command. The selector control means includes an encoder that addresses a clock signal to be selected from the output of the two-channel multiplexer, and the selector circuit inputs the plurality of clock signals into channels and addresses the clock signals to be selected by the selector control means. 2. The clock signal switching device according to claim 1, further comprising a multiplexer that selectively outputs the clock signal of the selected channel.