JPH0414230A - Semiconductor element - Google Patents
Semiconductor elementInfo
- Publication number
- JPH0414230A JPH0414230A JP2117187A JP11718790A JPH0414230A JP H0414230 A JPH0414230 A JP H0414230A JP 2117187 A JP2117187 A JP 2117187A JP 11718790 A JP11718790 A JP 11718790A JP H0414230 A JPH0414230 A JP H0414230A
- Authority
- JP
- Japan
- Prior art keywords
- head
- solder
- electrode
- chip
- diameter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 239000004020 conductor Substances 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000005219 brazing Methods 0.000 abstract description 20
- 229910000679 solder Inorganic materials 0.000 abstract description 14
- 239000002184 metal Substances 0.000 abstract description 8
- 229910052751 metal Inorganic materials 0.000 abstract description 8
- 239000011347 resin Substances 0.000 abstract description 3
- 229920005989 resin Polymers 0.000 abstract description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 2
- 238000000034 method Methods 0.000 abstract description 2
- 244000287353 Crassocephalum crepidioides Species 0.000 abstract 1
- 206010016322 Feeling abnormal Diseases 0.000 abstract 1
- 239000000463 material Substances 0.000 description 9
- 239000000945 filler Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3205—Shape
- H01L2224/32057—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体基板の表面上の電極に他端が端子とな
るような接続導体の頭部がろう付けされる半導体素子に
関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor element in which the head of a connecting conductor whose other end serves as a terminal is brazed to an electrode on the surface of a semiconductor substrate.
半導体素子の半導体基板上に設けられる電極にはリード
、配線等の導体が接続される。一方、半導体素子の外部
回路との接続のためには端子が必要である。最も簡単な
構造としては、電極に接続される導体の他端を端子とし
て使用することである。接続導体がリードのようなｉ線
であるときには、その一端を電極の面積に対応した面積
をもつ頭部に成形し、その頭部と電極をろう付けするの
が広く行われる。第２図はそのようなピンヘッド型の半
導体素子を示し、第３図はその半導体チップを示す、半
導体子ノブ１の表面には電極２が形成され、周縁部は表
面に露出した接合保護のための酸化膜３が覆っている。Conductors such as leads and wiring are connected to electrodes provided on the semiconductor substrate of the semiconductor element. On the other hand, terminals are required to connect the semiconductor element to an external circuit. The simplest structure is to use the other end of the conductor connected to the electrode as a terminal. When the connecting conductor is an i-line such as a lead, one end of the connecting conductor is generally formed into a head having an area corresponding to the area of the electrode, and the head and the electrode are brazed together. FIG. 2 shows such a pinhead type semiconductor element, and FIG. 3 shows the semiconductor chip. An electrode 2 is formed on the surface of the semiconductor knob 1, and the peripheral part is exposed on the surface to protect the junction. is covered with an oxide film 3.
このような半導体チップ１の両面の電極とリード４の頭
部５とをはんだ６でろう付けする。そして、多くの場合
チップ１の露出面を接合被覆樹脂（ＪＣＲ）で覆ったの
ち、点線で示したように樹脂あるいはガラスのような絶
縁材料７により封止する。リード４の先端の頭部５は、
半導体チップ１の電極とのろう付面積を大きくして接続
強度を確保するためのもので、ヘッダ加工などにより成
形される。The electrodes on both sides of the semiconductor chip 1 and the heads 5 of the leads 4 are brazed with solder 6. In many cases, the exposed surface of the chip 1 is covered with a bonding coating resin (JCR) and then sealed with an insulating material 7 such as resin or glass as shown by the dotted line. The head 5 at the tip of the lead 4 is
This is to increase the brazing area with the electrodes of the semiconductor chip 1 to ensure connection strength, and is formed by header processing or the like.
上記のような半導体素子のり一ド４の頭部５を半導体チ
ップ１の電極とろう付けするとき、はんだなどのろう材
６の量が多すぎると、例えば第３図の電極２の上からは
み出し、酸化膜３の上に到達し、素子特性への影響を及
ぼすおそれがある。When brazing the head 5 of the semiconductor element glue 4 with the electrode of the semiconductor chip 1 as described above, if the amount of brazing material 6 such as solder is too large, it may protrude from above the electrode 2 in FIG. 3, for example. , may reach the top of the oxide film 3 and affect the device characteristics.
あるいは、チップ１に低電位の金属部分が存在するとき
に、ろう材がその上に到達すると、電気的な短絡を起こ
すという問題がある。また、ろう材６の量が適正でろう
付は時には電極２の面からはみ出していなくても、素子
に過電流が流れたときの発熱により、はんだのような低
融点のろう材が溶け、例えば半導体チップとＪＣＲとの
間に流れ込んで特性を低下させたり、短絡を起こしたり
することがある。Alternatively, if there is a low-potential metal part on the chip 1 and the brazing material reaches thereon, there is a problem that an electrical short circuit will occur. In addition, even if the amount of brazing filler metal 6 is appropriate and the brazing does not protrude from the surface of the electrode 2, the heat generated when an overcurrent flows through the element may melt the low-melting-point brazing filler metal such as solder, e.g. It may flow between the semiconductor chip and the JCR, degrading the characteristics or causing a short circuit.
本発明の目的は、上記の問題を解決し、ろう材が電極面
上より外へ流出することがない、半導体素子を提供する
ことにある。SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide a semiconductor device in which the brazing material does not flow out from above the electrode surface.
上記の目的を達成するために、本発明は、半導体基板の
表面上の電極に接続導体の頭部の端面がろう付けされる
半導体素子において、頭部の端面中央部にくぼみを有す
るものとする。In order to achieve the above object, the present invention provides a semiconductor element in which the end face of the head of a connecting conductor is brazed to an electrode on the surface of a semiconductor substrate, which has a recess in the center of the end face of the head. .
半導体基板の電極と接続するときにろう材が過剰であっ
ても、過剰のろう材がくぼみ内に蓄積され、電極面外に
流出することはない、また、ろう材の量が適正な場合は
、くぼみ内に空洞が生し、ろう材の凝固、収縮によりこ
の空洞が低真空状態となる。そして、素子に過電流が流
れてろう材が再溶融したときには、溶けたろう材はこの
空洞に吸い込まれ、電極面外に流出することはない。Even if there is an excess of brazing material when connecting to the electrode of a semiconductor substrate, the excess brazing material will accumulate in the recess and will not flow out of the electrode surface, and if the amount of brazing material is appropriate. , a cavity is formed within the recess, and this cavity becomes a low vacuum state due to solidification and contraction of the brazing filler metal. When an overcurrent flows through the element and the brazing filler metal remelts, the melted brazing filler metal is sucked into this cavity and does not flow out of the electrode surface.
第１図は本発明の一実施例のビンヘッド型半導体素子を
示し、第２図と共通の部分には同一の符号が付されてい
る。リード４は直径１ｎの銅線でヘッダ加工により形成
された直径２．５ｍ、厚さ０．５〜１ｎの頭部５を有す
る。頭部５の中央には深さ約０．５ｍ、直径約０．７ｆ
ｉの凹部８が形成されている。このようなり−ド４の頭
部５と半導体チップ１の電極とをはんだ６でろう付けす
ると、過剰のはんだは凹部８の中に入る。そして凹部に
空洞９が残る。従って、はんだ６の量が過剰でも電極面
から外へ流出することはない。また、この素子の使用中
に過を流が流れてはんだ６が再熔融しても、そのはんだ
は低真空状態の空洞９へ流れ込み、チップ１およびリー
ド頭部５の側面に塗られたＪＣＲＩＯとチップ１との間
に流出することはない。FIG. 1 shows a bottle head type semiconductor device according to an embodiment of the present invention, and parts common to those in FIG. 2 are given the same reference numerals. The lead 4 has a head 5 with a diameter of 2.5 m and a thickness of 0.5 to 1 n, which is formed by header processing from a copper wire with a diameter of 1 n. The center of the head 5 has a depth of about 0.5m and a diameter of about 0.7f.
A recess 8 of i is formed. When the head 5 of the wire 4 and the electrode of the semiconductor chip 1 are brazed together with the solder 6, excess solder enters the recess 8. Then, a cavity 9 remains in the recess. Therefore, even if the amount of solder 6 is excessive, it will not flow out from the electrode surface. Furthermore, even if the solder 6 is remelted due to a flow of current during use of this element, the solder will flow into the cavity 9 in a low vacuum state and join the JCRIO coated on the sides of the chip 1 and the lead head 5. There is no leakage between chip 1 and chip 1.
第４図は本発明の別の実施例のフラットベース型半導体
素子を示し、この場合は半導体チップ１は第５図に示す
ように円形であり、円形の底板１１の上にろう材６によ
り固着され、上面の電極２はリード４の円形の頭部５と
ろう材６によりろう付けされている０頭部５には凹部８
が形成されていて第１図の実施例と同様の効果を生ずる
。FIG. 4 shows a flat base type semiconductor device according to another embodiment of the present invention, in which the semiconductor chip 1 is circular as shown in FIG. The electrode 2 on the top surface is brazed to the circular head 5 of the lead 4 with a brazing material 6. The head 5 has a recess 8.
is formed, producing the same effect as the embodiment shown in FIG.
本発明によれば、半導体基板の電極にろう付けされる接
続導体の中央部にろう材のためのくぼみを設けるだけで
、電極面から外部へのろう付は時あるいは使用中の異常
温度上昇の際の溶融ろう材の流出が防止できる。くぼみ
形成による接続導体と電極との固着強度の低下はほとん
どない、これにより、特に接合が電極の周辺に近接して
表面に露出しているプレーナ型半導体素子の接合上への
ろう材の流出が防止できるため、その効果は特に大きい
。また、半導体素子の過電流耐量の向上に対する効果も
大きい。According to the present invention, by simply providing a recess for the brazing material in the center of the connecting conductor to be brazed to the electrode of the semiconductor substrate, brazing from the electrode surface to the outside can be carried out over time or during abnormal temperature rise during use. It is possible to prevent the molten brazing filler metal from flowing out during the process. There is almost no decrease in the adhesion strength between the connecting conductor and the electrode due to the formation of the depression, and this prevents the leakage of the brazing material onto the bond, especially in planar semiconductor devices where the bond is close to the periphery of the electrode and exposed on the surface. The effect is especially great because it can be prevented. Moreover, the effect on improving the overcurrent withstand capacity of the semiconductor element is also large.
第１図は本発明の一実施例のビンヘッド型半導体素子の
断面図、第２図は従来のビンヘッド型半導体素子の断面
図、第３図はその半導体チップの平面図、第４図は本発
明の別の実施例のフラットベース型半導体素子の断面図
、第５図はその半導体チップの平面図である。FIG. 1 is a sectional view of a bottle head type semiconductor device according to an embodiment of the present invention, FIG. 2 is a sectional view of a conventional bottle head type semiconductor device, FIG. 3 is a plan view of the semiconductor chip, and FIG. FIG. 5 is a cross-sectional view of a flat base type semiconductor device of another embodiment, and FIG. 5 is a plan view of the semiconductor chip.
Claims (1)
がろう付けされるものにおいて、頭部の端面の中央部に
くぼみを有することを特徴とする半導体素子。1) A semiconductor element in which the end face of the head of a connecting conductor is brazed to an electrode on the surface of a semiconductor substrate, characterized in that the end face of the head has a recess in the center.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2117187A JPH0414230A (en) | 1990-05-07 | 1990-05-07 | Semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2117187A JPH0414230A (en) | 1990-05-07 | 1990-05-07 | Semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0414230A true JPH0414230A (en) | 1992-01-20 |
Family
ID=14705561
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2117187A Pending JPH0414230A (en) | 1990-05-07 | 1990-05-07 | Semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0414230A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006218122A (en) * | 2005-02-10 | 2006-08-24 | New Industry Research Organization | System for diagnosing leg condition and method for diagnosing using it |
-
1990
- 1990-05-07 JP JP2117187A patent/JPH0414230A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006218122A (en) * | 2005-02-10 | 2006-08-24 | New Industry Research Organization | System for diagnosing leg condition and method for diagnosing using it |
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