JPH04137912A - Output circuit - Google Patents

Abstract

PURPOSE:To increase/decrease an output current as required by changing the drive capability of an output buffer driving an external load of a semiconductor integrated circuit through the detection of an output voltage. CONSTITUTION:With an L level provided to an input terminal 1, a P-channel MOS transistor(TR) (Pch TR) 3 is turned on and is going to output an output H, and suppose that the drive capability of the Pch TR 3 is unable to supply the output to an H level. In such a case, an input of an inverter 13 is at an L and an H output is supplied to a NAND 16. An H level is provided to other terminal of the NAND 16 from an inverter 14 and the NAND 16 provides an L level to the data input of a set flip-flop (SDF) 9. After the data input of the SDF 9 is decided, a clock is supplied and an L level is outputted via an OR 7 to the Pch TR 4, which is turned on.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an output circuit, and in particular to an output circuit that can automatically change the driving capacity depending on the size of the load when driving an external load of a semiconductor integrated circuit. Regarding circuits.

Conventional technology The output circuit of a conventional 1 (OS LSI) is shown in FIG.

In this example, the output buffer is a P-type MOS transistor 22 and an N-type MOS transistor 22. The drive capacity of this output buffer is determined by the size of the P-type and N-type MOS transistors.

Further, the size of this transistor is designed according to the size of the external load to be used.

Therefore, when varying the external load, it is designed assuming that the external load is the largest.

Problems to be Solved by the Invention In the conventional output circuit described above, since the transistor of the output buffer is fixed, the driving ability, that is, the output current value is constant. When changing the load, it is necessary to provide the necessary driving capacity when the load is the largest, and the same output current will flow even when the number of negative bacteria is reduced, and in this case, more power than necessary is required. There was a problem with consuming too much.

The present invention has been made in view of the above-mentioned conventional situation,
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a novel output circuit which solves the above-mentioned problems inherent in the prior art and allows the output to be adjusted as necessary.

Means for Solving the Problems In order to achieve the above object, the output circuit according to the present invention includes a complementary MOS output buffer that is always used, a spare complementary MOS output buffer, and a complementary MOS output buffer that responds to changes in input signals. a flip-flop circuit that generates an output signal and controls the opening/closing of the spare output buffer; The first logic circuit that gates the output compares the logic of the input and output, and when the logic of the output does not match the expected value, the spare output buffer
a second logic circuit that applies a signal to the data input of the flip-flop so as to turn it on; and a delay circuit that delays a change in the clock input of the flip-flop from a change in the signal of the second logic circuit. Prepared and configured.

Embodiments Next, preferred embodiments of the present invention will be specifically explained with reference to the drawings.

FIG. 1 is a circuit block diagram showing a first embodiment of the present invention.

Referring to FIG. 1, normally, the signal input from input terminal 1 is transmitted through a P-type)40S) transistor (hereinafter referred to as Pch Tr).
) 3 and N-type MOS transistor (hereinafter referred to as Nch
(referred to as Tr) 5 and is inverted by an output buffer and outputted from an output terminal 2. However, Pc
If an external load exceeding the driving capacity of the output buffer composed of hTr3 and Nch Tr5 is applied, the output cannot reach the expected output value of "H" or vice versa. It is expected that a phenomenon will occur in which the output cannot reach "L" with respect to the expected output value "S". However, the present invention can prevent such a phenomenon.

First, consider the case where the input is "H→L" and the expected output value is "Ho". When “L” is applied to input terminal 1, Pch
Tr3 turns on and tries to output an output of “H”, but at this time, the driving ability of PchTr3 alone cannot output “H”.
”. In this case, inverter 1
3 input is “L”, “H” output t, NAND
Give to 16. “H” is applied to one terminal of the NAND 16 from the inverter 14, and the NAND 16
gives “L” to the data input of the set flip-flop (hereinafter referred to as SDF) 9.

After the data input of SDF 9 is determined, a clock is given to it, and it outputs "L". This signal is given to Pch Tr4 via OR7, and Pch Tr4 is also turned on. In this way, Pch By turning on the two transistors Tr3 and Tr4, the drive capacity increases (if the size ratio of the two transistors is 1, the drive capacity is twice the normal drive capacity).Pch Tr4 remains “on” until the next input logic inverts.

Similarly, when the input is "L→H" and the expected output value is "L", if the drive capacity is insufficient, Nch jR6 turns on and the drive capacity increases.
It then remains “on” until the input logic is reversed.

At the beginning of circuit operation, spare buffers (Pch Tr4, Nc
hTr6) is turned off by connecting the SDF 9, the SN input of the reset flip-flop (RDF) 10, and the R
Each N input has a power-on clear (P
, 0, C) signal is applied to set or reset.

FIG. 2 is a circuit block configuration diagram showing a second embodiment according to the present invention.

Referring to FIG. 2, by replacing the inverter 13 in FIG. 1 with a comparator 19, the switching judgment of the output buffer driving ability, which was previously based on the logic threshold of the inverter 13, can be changed to the resistance R, (20). , and resistor R2 (21), it is possible to set an arbitrary voltage level.

As described in detail, the output circuit of the present invention has the function of changing the driving ability of the output buffer that drives the external load of the semiconductor integrated circuit by detecting the output voltage. As a result, it is possible to suppress the output current and the through-current of the output buffer during normal times, and increase the output current when necessary.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram showing a first embodiment according to the present invention, FIG. 2 is a circuit block diagram showing a second embodiment according to the present invention, and FIG. 3 is a circuit diagram of a conventional output circuit. be. 1...Input terminal, 2...Output terminal, 3...P type M
O5+- runcisister (PchTr always used), l-
P-type MOS transistor (PchTr, spare) -5・=
N-type MOS transistor (NchTr always used),
6.-N type MOS transistor <NchTr, spare)
, 7-OR gate, 8...AND gate, 9...set 1 inch flip-flop (5DF), 10...flip-flop with reset (RDF) 11-15...inverter, 16-NAND gate, 17- NOR gate, 1
8...Delay element, 19...Comparator 520
... Resistor R,, 21... Resistor R2, 22... P-type MOS) transistor, 23... N-type MOS transistor Patent applicant: NEC Co., Ltd. representative / attorney Yutabe Kumagai, patent attorney

Claims (1)

[Claims] A complementary MOS output buffer that is always used, a complementary MOS output buffer that is a backup, a flip-flop circuit that generates an output signal in response to a change in an input signal and controls opening and closing of the backup output buffer, and a flip-flop circuit that controls opening and closing of the backup output buffer. A first logic circuit gates the output of the flip-flop circuit so that the output buffer does not output a logic opposite to the logic of the always-used output buffer, and the input/output logic is compared to determine the output logic. A spare output buffer is used when the expected value is not met.
a second logic circuit for applying a signal to the data input of the flip-flop so as to turn it on; and a delay circuit for delaying a change in the clock input of the flip-flop relative to a change in the signal of the second logic circuit. An output circuit comprising: