JPH04137500U - Step motor drive circuit - Google Patents

Abstract

(57) [Summary] [Purpose] To stabilize the pulse width of a motor drive pulse signal and normalize the drive function for a step motor. [Structure] A frequency divider circuit 1 that frequency divides an oscillation signal 101, a binary flip-flop circuit 2 driven by an output signal 103 of the frequency divider circuit 1, and data flip-flop circuits 3-1 and 3-2. and is driven by another divided signal 102 of the frequency divider circuit 1 and an output signal 104 of the binary flip-flop circuit 2 to output a pair of signals 105, 108 and 106, 107, respectively. Circuit 3 and NOR circuits 4-1 and 4-
2, and a pulse generation circuit 4 which receives the output signal of the pulse width adjustment circuit 3 and outputs a pair of motor drive pulse signals 109 and 110.

Description

[Detailed explanation of the idea]

0001

[Industrial application field]

The present invention relates to step motor drive circuits, and is particularly applicable to step motor drive circuits. This invention relates to a step motor drive circuit.

0002

[Conventional technology]

A conventional step motor drive circuit of this type has a predetermined speed, as shown in FIG. A frequency dividing circuit 5 that divides the frequency of the oscillation signal 111 and an output signal 112 of this frequency dividing circuit 5 binary flip-flop circuit 6 and NOR circuits 7-1 and 7-2 driven by and delay elements 7-3 and 7-4, and the output of the binary flip-flop circuit 6. Driven by force signals 113 and 114, a pair of motor drive pulse signals 11 The pulse width adjustment circuit 7 outputs signals 7 and 118.

0003 In FIG. 3, the oscillation signal 111 is divided by n (n is a positive integer) in the frequency dividing circuit 5. The output signal 112 is the clock terminal of the binary flip-flop circuit 6. input to the child. Output signals 113 and 1 of binary flop-flip circuit 6 14 are a NOR circuit 7-1 and a delay element included in the pulse width adjustment circuit 7, respectively. 7-4, a NOR circuit 7-2, and a delay element 7-3.

0004 4(a), (b), (c), (d), and (e) correspond to the operation of the conventional example. The timing chart of each signal is shown, but the output signal 11 of the frequency divider circuit 5 2, the output signal 113 of the binary flip-flop circuit 6 is N It is input to one input terminal of the OR circuit 7-1 (see FIG. 4(b)). Also, at the same time Then, the output signal 114 of the binary flip-flop circuit 6 is sent to the delay element 7-3. It is output as a signal 115 with a delay of a certain time (τ), and is also output as a signal 115 through the NOR circuit 7-. 1 (see FIG. 4(c)). Therefore, NOR circuit 7- 1 outputs a motor drive pulse signal 117 shown in FIG. 4(d).

[0005] Similarly, in response to the input of the output signal 112 of the frequency divider circuit 5, the binary flip The output signal 114 of the flop circuit 6 is input to one input terminal of the NOR circuit 7-2. At the same time, the output signal 113 of the binary flip-flop circuit 6 is 7-4, it is output as a signal 116 with a certain time delay (τ), and the NO It is input to the other input terminal of the R circuit 7-2. Therefore, from the NOR circuit 7-2, , a motor drive pulse signal 118 shown in FIG. 4(e) is output.

[0006] That is, the output signals 113 and 114 of the binary flip-flop circuit 6 are Since the motor drive pulse signals 117 and 118 are output inverted from each other, are output with a phase difference of 180 degrees from each other, and the pulse width is adjusted by adjusting the pulse width. It is set by the delay time of the delay element included in the circuit 7.

[0007]

[Problem that the idea aims to solve]

In the conventional step motor drive circuit described above, the pulse width adjustment circuit The pulse width of the motor drive pulse signal may vary due to variations in the delay time of the delay elements. If the pulse width is not constant and the pulse width becomes narrow, try driving the step motor. The disadvantage is that it is impossible.

[0008]

[Means to solve the problem]

The step motor drive circuit of the present invention includes a frequency dividing circuit that divides the frequency of a predetermined oscillation signal; A binary flip driven by the first frequency divided signal output from the frequency dividing circuit. a second frequency-divided signal output from the frequency divider circuit, and a second frequency-divided signal output from the frequency divider circuit; Pulse width adjustment driven by the signal output from the flip-flop circuit circuit, and receives a plurality of signals output from the pulse width adjustment circuit, and outputs the oscillation signal. A pair of motor drive pulses with different phases and a time width equivalent to an integral multiple of the period of the signal. and a pulse generation circuit that generates a signal.

[0009]

【Example】

Next, the present invention will be explained with reference to the drawings.

0010 FIG. 1 is a block diagram showing one embodiment of the present invention. As shown in Figure 1, the book The embodiment includes a frequency dividing circuit 1 that frequency divides a predetermined oscillation signal 101, and an output of this frequency dividing circuit 1. A binary flip-flop circuit 2 driven by a power signal 103 and a data Another frequency divider of frequency divider circuit 1, including flip-flop circuits 3-1 and 3-2. Driven by signal 102 and output signal 104 of binary flip-flop circuit 2 and output a pair of signals 105, 108 and 106, 107, respectively. The pulse width adjustment circuit includes a pulse width adjustment circuit 3 and NOR circuits 4-1 and 4-2. 3, outputs a pair of motor drive pulse signals 109 and 110. The pulse generation circuit 4 is configured to include a pulse generation circuit 4.

[0011] In FIG. 1, an oscillation signal 101 is divided by m (m is a positive integer) in a frequency dividing circuit 1. and its output signal 102 is sent to data flip-flop circuits 3-1 and 3- It is input to the clock terminal of No.2. In addition, the output signal frequency-divided by n in the frequency divider circuit 1 is No. 103 is input to the clock terminal of the binary flip-flop circuit 2. The output signal 104 of this binary flip-flop circuit 2 is the data flip-flop circuit 2. It is input to the data terminal of the flop circuit 3-1, and the data flip-flop circuit 3 -1, receives the input signals 102 and 104 and outputs a pair of signals 105 and 1. 06 is output. The signal 105 is the data input signal of the data flip-flop circuit 3-2. The signal 106 is input to the input terminal of the NOR circuit 4-1 and the input terminal of the NOR circuit 4-1. It is input to one input terminal of the NOR circuit 4-2. data flip-flop times In the path 3-2, receiving the input signals 102 and 105, a pair of signals 10 7 and 108 are output from the other NOR circuits 4-2 and 4-1, respectively. input to the other input terminal.

0012 Figures 2 (a), (b), (c), (d), (e), (f) and (g) show the book A timing chart of each signal corresponding to the operation of the example is shown, but the frequency division The output signal 103 of circuit 1 is divided by two in binary flip-flop circuit 2. The data is output as a signal 104 to the data flip-flop circuit 3-1. input to the terminal. In the data flip-flop circuit 3-1, the clock A signal 105 having the same frequency as the signal 104 is synchronized with the signal 102 input to the terminal. Then, this inverted signal 106 is output. And data flip-flop circuit In 3-2, the signal 105 input to the data terminal and the signal 105 input to the clock terminal are The signal 102 is synchronized with the signal 102 and the signal 1 is synchronized with the signal 105. A signal 107 delayed by one period of the period of 02 and this inverted signal 108 are output. Ru. These signals 105, 108 and signals 106, 107 are as described above. These are input to NOR circuits 4-1 and 4-2, respectively, but these NOR circuits 4- 1 and 4-2, as seen in FIGS. 2(f) and (g), the frequency divider circuit 1 synchronized with the m-frequency-divided signal 102 output from the Motor drive pulse signals 109 and 110 having a pulse width corresponding to the period are output. Powered. And the phase relationship of these motor drive pulse signals 109 and 110 As is clear from Figures 2(f) and (g), the relationship is In the period of the signal 104 output from the loop circuit 2, a phase difference of 180 degrees is alternately applied. It is output based on the relationship that it has.

[0013] That is, the pulse width of the motor driving pulse signals 109 and 110 is determined by the frequency dividing circuit 1. It is uniquely determined by the frequency of the oscillation signal 101 input to the pulse generator. The width of the path is kept stable at all times.

[0014]

[Effect of the idea]

As explained above, the present invention uses digital processing for oscillation signals to The pulse width of the pulse signal for driving the motor is set. The effect is that it is held stably and the step motor can be driven stably at all times. There is.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a diagram showing a timing chart of each signal corresponding to the operation of this embodiment.

FIG. 3 is a block diagram showing a conventional example.

FIG. 4 is a diagram showing a timing chart of each signal corresponding to the operation of the conventional example.

[Explanation of symbols]

1, 5 frequency divider circuit 2, 6 Binary flip-flop circuit 3, 7 Pulse width adjustment circuit 3-1, 3-2 Data flip-flop circuit 4 Pulse generation circuit 4-1, 4-2, 7-1, 7-2 NOR circuit 7-3, 7-4 Delay element

Claims (1)

[Scope of utility model registration request] [Claim 1] A frequency dividing circuit that divides a predetermined oscillation signal;
A binary flip-flop circuit driven by a first frequency-divided signal output from the frequency divider circuit, a second frequency-divided signal output from the frequency divider circuit, and a binary flip-flop circuit driven by the first frequency divided signal output from the frequency divider circuit. a pulse width adjustment circuit driven by a signal, and a pair of motors having different phases, each having a time width corresponding to an integral multiple of the period of the oscillation signal, in response to the plurality of signals output from the pulse width adjustment circuit. A step motor drive circuit comprising: a pulse generation circuit that generates a drive pulse signal.