JPH04110029U - Phase synchronized oscillation circuit - Google Patents

Abstract

(57) [Summary] [Purpose] To provide a phase synchronized oscillator circuit that generates less phase noise in the voltage controlled oscillator 13 and that obtains an output signal with reduced phase noise even when the reference signal contains jitter. [Configuration] First oscillation circuit 1 having a voltage-controlled crystal oscillator 9 that forms a phase-locked loop and oscillates with respect to a reference signal.
6 and a second oscillation circuit 17 having a voltage-controlled oscillator 13 that forms a phase-locked loop with respect to the output signal of the first oscillation circuit 16 and oscillates, forming a phase-locked oscillation circuit.

Description

[Detailed explanation of the idea]

0001

[Industrial application field]

This invention relates to phase-locked oscillator circuits, and in particular, it uses a fixed frequency reference signal. This invention relates to a phase synchronized oscillator circuit with reduced phase noise that is frequency multiplied.

0002

[Conventional technology]

An example of a conventional phase-locked oscillator circuit is shown in FIG. In the figure, 1 is an input terminal. The frequency of the reference signal input to input terminal 1 is divided by 1/x by frequency divider 2, It is input to one input terminal of the phase comparator 3. 5 is a voltage controlled oscillator, which controls It oscillates at a voltage-controlled frequency. The signal oscillated by the voltage controlled oscillator 5 The signal is output from the output terminal 8 and is also sent to the prescaler 6 and module controller. The frequency is divided into 1/y by the frequency divider 8 with a loop, and the other input terminal of the phase comparator 3 input to the child. Prescaler 6 is a high frequency divider, and the division ratio is only 1. Either of the frequency division ratios will be used to control the frequency divider 7 with module control. is selected to divide the input signal. Frequency divider 7 with module control The division ratio of rescaler 6 is selected by time division, and prescaler 6 and module controller are selected. The prescaler 6 sets the overall frequency division ratio of the frequency divider 7 with the troll to exactly y. control. The phase comparator 3 corresponds to the frequency and phase difference of the above two input signals. The loop filter 4 removes high frequency components of the output voltage and controls the voltage. This is the control voltage of the control oscillator 5. As mentioned above, the phase comparator 3, the loop filter 4 , voltage controlled oscillator 5, prescaler 6 and frequency divider with module control Synchronized to the reference signal input to input terminal 1 by the phase-locked loop consisting of 7. The resulting output signal is output from the output terminal 8.

In the above circuit, if the frequency of the reference signal is F _r and the frequency of the output signal is F _v , then F _v = (y/x) F _r and the comparison frequency F _c in the phase comparator 3 is F _c = F _r /x=F _v /y.

0004

[Problem that the invention attempts to solve]

In the conventional system described above, when the phase noise of the reference signal is small, Also, the influence of the phase noise generated in the voltage controlled oscillator 5 itself is large, and as a result, the output There was a problem that the phase noise of the signal became large.

[0005] In addition, if the reference signal contains jitter, its effect will appear on the output signal. There was a drawback that

[0006] This idea was made in view of the above points, and its purpose is is less affected by the phase noise generated by the voltage controlled oscillator itself, and also has less influence on the reference signal. You can obtain an output signal with reduced phase noise even if it contains jitter. The object of the present invention is to provide a possible phase-locked oscillation circuit.

[0007]

[Means to solve the problem]

The phase-locked oscillator circuit of this invention forms a phase-locked loop with respect to the reference signal. a first oscillation circuit having an oscillating voltage-controlled crystal oscillator; and an output of the first oscillation circuit a second voltage-controlled oscillator that forms a phase-locked loop with respect to the signal and oscillates; It consists of an oscillation circuit.

[0008]

[Effect]

According to this invention, the phase-locked oscillation circuit consists of a first oscillation circuit and a second oscillation circuit. Since it is formed by cascade connection, it is the product of the frequency multiplication ratio of each phase-locked loop of both oscillator circuits. The overall frequency multiplication ratio can be increased, and the input frequency and output frequency can be increased. Input signal of the phase comparator of the phase-locked loop of the first oscillation circuit for setting the ratio to a predetermined value frequency can be lowered. Therefore, by dividing the reference signal with a large division ratio, It can be input to the phase comparator of the phase-locked loop of the first oscillator circuit, and the frequency is divided. This reduces jitter with a short fluctuation cycle of the reference signal. Furthermore, the first oscillation Since the circuit is oscillated by a voltage controlled crystal oscillator, phase noise is low.

[0009] Also, the comparison frequency in the phase comparator of the phase-locked loop of the second oscillation circuit is increased. This reduces the phase noise of the voltage controlled oscillator in the second oscillation circuit. , it becomes possible to oscillate a frequency with less phase noise as a whole.

0010

【Example】

A phase-locked oscillation circuit which is an embodiment of this invention will be explained based on FIG.

[0011] In the figure, 1 is an input terminal. The reference signal input to input terminal 1 is applied to frequency divider 2. The frequency is divided by 1/X and input to one input terminal of the phase comparator 3. . 9 is a voltage controlled crystal oscillator, which oscillates at a frequency controlled by the control voltage. do. The signal oscillated by the voltage controlled crystal oscillator 9 is input to one input terminal of the phase comparator 11. At the same time, the frequency is divided into 1/Y by the frequency divider 10, and the phase is compared. The signal is input to the other input terminal of the device 3. The phase comparator 3 detects the frequency of the above two input signals. The loop filter 4 outputs a voltage according to the number and phase difference, and the loop filter 4 outputs a voltage corresponding to the high frequency of the output voltage. The wave component is removed and a control voltage is supplied to the voltage controlled crystal oscillator 9. As above, the position It consists of a phase comparator 3, a loop filter 4, a voltage controlled crystal oscillator 9, and a frequency divider 10. The output is synchronized with the reference signal input to input terminal 1 by the phase-locked loop created. A power signal is output from the voltage controlled crystal oscillator 9. The above circuit is the first oscillation circuit 16 It consists of

Similarly, the second oscillation circuit 17 includes a phase comparator 11 , a loop filter 12 , a voltage controlled oscillator 13 and a prescaler 14 . Note that the prescaler 14 is a frequency divider in which a high frequency division ratio of the input signal frequency is fixed. A signal output from the first oscillation circuit is input to one input terminal of the phase comparator 11. The voltage controlled oscillator 13 oscillates at a frequency controlled by a control voltage. The signal oscillated by the voltage controlled oscillator 13 is output from the output terminal 15, has its frequency divided by 1/Z by the prescaler 14, and is input to the other input terminal of the phase comparator 11. The phase comparator 11 outputs a voltage according to the frequency and phase difference of the two input signals, and the loop filter 12 removes high frequency components of the output voltage and supplies a control voltage to the voltage controlled oscillator 13. As described above, the second oscillation circuit 17 is constituted by a phase locked loop composed of the phase comparator 11, the loop filter 12, the voltage controlled oscillator 13, and the prescaler 14. The second oscillation circuit 17 outputs from the output terminal 15 an output signal synchronized with the signal output from the first oscillation circuit. In order to set the frequency of the reference signal input to the circuit of the above embodiment to be the same F _r as in the case of the circuit of FIG. 2, and to set the frequency of the signal output from the output terminal 15 to be the same F _v as in the case of the circuit of FIG. For example, X=x×Z, Y=y. In that case, the output frequency of the first oscillation circuit is (Y/X)F _r =(y/xZ)F _r , and the output frequency F _v of the second oscillation circuit is F _v = (y/xZ) F _r ×Z=(y/x) _Fr , which is the same as in the case of the circuit in FIG. The comparison frequency of the phase comparator 11 of the second oscillation circuit can be increased by setting Z<y, and the phase noise generated in the second oscillation circuit is reduced. In the embodiment, the frequency division ratios X, Y, and Z are set to 8192, 6473, and 128, respectively, and a reference signal with a frequency of 16 MHz is input. An output signal with an extremely stable frequency of 25 MHz could be obtained.

[0013]

[Effect of the idea]

According to this invention, the phase of the first oscillation circuit is determined by dividing the reference signal with a large frequency division ratio. It can be input to the phase comparator of the synchronous loop, and by dividing the frequency, the reference signal Jitter with a short fluctuation period is reduced. Furthermore, the first oscillation circuit is a voltage controlled crystal oscillator. Since it is oscillated by an oscillator, there is little phase noise.

[0014] In addition, the comparison frequency of the phase-locked loop of the second oscillation circuit can be increased. Therefore, the phase noise generated in the phase-locked loop itself can be reduced, and the influence of mechanical vibration can be reduced. It is possible to obtain the effect that the noise is also reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a phase-locked oscillation circuit as an embodiment of the invention.

FIG. 2 is a block diagram showing an example of a conventional phase-locked oscillation circuit.

[Explanation of symbols]

1 Input terminal 2 Frequency divider 3 Phase comparator 4 Loop filter 5 Voltage controlled oscillator 6 Prescaler 7 Frequency divider with module control 8 Output terminal 9 Voltage controlled crystal oscillator 10 Frequency divider 11 Phase comparator 12 Loop filter 13 Voltage controlled oscillator 14 Prescaler 15 Output terminal 16 First oscillation circuit 17 Second oscillation circuit

Claims (1)

[Scope of utility model registration request] 1. A first oscillation circuit including a voltage-controlled crystal oscillator that oscillates by forming a phase-locked loop with respect to a reference signal, and a phase-locked loop forming with respect to an output signal of the first oscillation circuit. A phase synchronized oscillation circuit configured with a second oscillation circuit having an oscillating voltage controlled oscillator.