JPH04136984A - Driver circuit for display device - Google Patents

Abstract

PURPOSE:To reduce the number of external voltages required for a tone expression by applying the voltage of one level out of the external voltages to a picture element for the first half of one output period of a signal voltage and controlling so as not to send a voltage for the prescribed time of the latter half, when the signal voltages of different levels are applied to the picture element based on digital picture signal data and the tone expression is carried out. CONSTITUTION:A voltage selecting means SEL sends the voltage of the level corresponding to picture signal data D0 - D2 for the first period of the beginning of one output period, and does not send the voltage for the second period of the reset. Since the picture element connected with a signal electrode, the voltage applied on the picture element is only gradually approximated to a sent voltage according to a prescribed voltage, even if the voltage of a constant value is sent to the signal electrode. Therefore, the voltages V1 - V4 applied from a voltage supplying means are properly used according to the picture signal data: they are sent to the signal electrode as they are, by controlling time like the above-mentioned. Thus, the voltages of the number of external voltage levels or more can be applied on the picture element. This properly using can be carried out by a time control circuit TC.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a drive circuit for a display device, and more particularly to a drive circuit for a display device that can perform gradation display using an amplitude modulation drive method. Although the following explanation will be given by taking a matrix type liquid crystal display device as an example, the present invention is also applicable to drive circuits for other types of display devices, such as EL (electroluminescence) display devices and plasma displays.

(Prior art) When driving a liquid crystal display device, the response speed of the liquid crystal is faster than that of a CRT.
(Cathode Ray Tube) Because it is very low compared to the fluorescent materials used in displays, special display drive circuits are used. In other words, the liquid crystal display drive circuit does not directly apply the image signals that are sent to each pixel as they are, but rather
Image signals sampled corresponding to each picture element within one horizontal period are held during that horizontal period, and are output all at once at the beginning of the next horizontal period or at an appropriate time in the middle thereof. After the output of the image signal voltage to each picture element is started, the signal voltage is held for a time that sufficiently exceeds the response speed of the liquid crystal.

In order to maintain this signal voltage, conventional drive circuits use capacitors. Figure 1O shows a signal voltage output circuit (source driver) that supplies drive voltages to a large number (120 picture elements in this case) on one scanning line selected by a scanning signal. The source driver for the picture element is an analog switch SW as shown in FIG.
1. It is composed of a sampling capacitor C3fflP, an analog switch SW2, a hold capacitor CH%, and an output cover sofa amplifier A. The operation of conventional signal voltage output will be explained with reference to these circuit diagrams and the signal timing diagram of FIG. The analog image signal V5 input to the analog switch SW is the horizontal synchronization signal H9.
,. The sampling signal Tsr+ρ1 corresponding to each of the 120 picture elements on one scanning line selected for each
˜T 5l Sequentially sampled by IPI 211. Through this sampling, instantaneous voltages VSrlPI to VSnPI2i1 of the image signal vs at each time point are applied to each sampling capacitor csnp. The n-th sampling capacitor C511ρ is charged with the image signal voltage value srlρ corresponding to the n-th picture element and holds that value. The signal voltage VSIIPI thus sequentially sampled and held during one horizontal period
~VSMρ122 is moved from each sampling capacitor C3lip to a hold capacitor CH for holding the output by an output pulse OE given to all analog switches SW2 at once, and is connected to each picture element via a buffer amplifier A. It is output to source lines 01 to 01211.

(Problem to be Solved by the Invention) The drive circuit described above is for the case where the image signal is given in analog form, or when the image signal is given in the form of digital data, the drive circuit as shown in FIG. is used. Here, for the sake of simplicity, it is assumed that the image signal data is composed of 2 pits (D9% DI). That is, the image signal data has four values from 0 to 3, and the signal voltage given to each picture element is V e -
It will be one of the 4 levels of V3. FIG. 14 shows a signal voltage output circuit (
This circuit shows the first stage D flip-flop (sampling memory) M provided for each bit (DeSD 1) of the image signal data.
S+1ρ, second stage flip-flop (hold memory) MH1, 11 decoders DEC1, and analog switches A S W9- A S each provided between 4-level external voltage source ■8 to V3 and source line On.
It is composed of W3. This circuit operates as follows. The image signal data DI+, DI are taken from the sampling memory MSMP to the hold memory MH at the rising edge of the sampling pulse TshPn corresponding to the n-th picture element, and are held there. At the end of sampling for one horizontal period, the output pulse OE is applied to the hold memory MH, and the image signal data DQ and DI held in the hold memory MH are output to the decoder DEC.

The decoder DEC receives this 2-bit image signal data D8,
D, and depending on the value (0 to 3), one of the analog switches ASWs to ASW3 is made conductive, and one of the four levels of external voltages ■8 to ■3 is turned on to the source line. Output to.

In the example of FIG. 14, the image signal data is 2 bits, so the external voltage output to the source line O1 is 4 (
-22) level (V[l~V3) was required. When the image signal data is given in 3 bits, the signal voltage output circuit becomes as shown in Fig. 15, and the external voltage is 23-bit.
Eight levels (V[l to Vv) are required. That is, in a digital image signal drive circuit configured in this manner, if the digital image signal data is n bits, external voltages of 2n levels must be prepared. As the types of voltages that need to be applied externally increase in this way,
The following problems arise.

(1) As the number of types of voltages to be supplied increases, the voltage supply circuit becomes larger and the cost also increases.

(2) Since the number of input terminals of the LSI constituting the drive circuit including the signal voltage output circuit described above increases, it becomes difficult to implement the LSI.

The present invention was made in view of the current situation, and
It is an object of the present invention to provide a drive circuit for digital image signals in which the number of external voltages does not increase rapidly even if the number of bits of image signal data increases.

(Means for Solving the Problems) A drive circuit for a display device according to the present invention is a drive circuit for a display device provided with a plurality of parallel signal electrodes each connected to a picture element having an electric capacity. voltage supply means for outputting voltages of mutually different levels; time control means for generating a pulse signal that divides one output period into a first period and a second period according to a portion of input digital image data;
and according to the pulse signal from the time control means, no voltage is sent to the signal electrode during the first period, and during the second period, the input digital signal among the plurality of voltages output from the voltage supply means is The image forming apparatus is provided with voltage selection means for sending a voltage of one level corresponding to the remaining part of the image data to the signal electrode, thereby achieving the above object.

=7 (Function) The voltage selection means does not send a voltage to the signal electrode during the first period at the beginning of one output period, and sends a voltage at a level corresponding to the image signal data during the remaining second period. do. The picture element connected to the signal electrode has an electric capacity, so even if a constant voltage is sent to the signal electrode, the voltage applied to the picture element will gradually approach the sending voltage according to a predetermined curve. Only. Therefore, by appropriately determining the value of the voltage sent to the signal electrode and the length of the second period during which the voltage is sent, the output period begins when the value of the signal voltage applied to the picture element reaches the desired value. It is possible to cause the voltage to be delivered to the signal electrode to end when the voltage is completed. Therefore, depending on the image signal data, the voltage supplied from the voltage supply means can be sent to the signal electrode as it is, or it can be sent while controlling the time in this way. A voltage of , can be applied to the picture element. The time control circuit separates these cases.

=8- (Example) The invention will now be described with reference to examples.

FIG. 1 shows a signal voltage output circuit (source driver) corresponding to the nth signal line (source line) oo of a drive circuit for a liquid crystal display device when digital image signal data is composed of 3 bits. .

This circuit consists of a sampling memory MSMP, an output holding memory (hold memory) MH, a time control circuit TC1 selection circuit SEL, and four analog switches ASW+ to A.
Equipped with SW a.

The sampling memory MS+1ρ is composed of three D flip-flops corresponding to each bit De, DI, and D2 of the digital image signal data, and the image signal data is latched into the sampling memory MSMP at the rising edge of the sampling pulse TSMPn, and is stored in the hold memory. M
Output to H. The data input to this hold memory M)I is latched by the rising edge of the output pulse OE, and is output to the time control circuit TC and the selection circuit SEL. Here, among the outputs of the hold memory MH, the least significant bit D[+ of the digital image signal data is the time control circuit T
The other bits (in this embodiment, the upper two bits D1 and D2) are input to the selection circuit SEL.
It becomes B.

In addition to the 1-bit data (the least significant bit Dl of the image signal data) from the hold memory M)l, a pulse signal (time control pulse signal) TM is input to the time control circuit TC from the outside. The output CTM is the upper bits of the image signal data (in the case of this embodiment, 2 bits D1,
Together with D2), it becomes an input to the selection circuit SEL. Based on these inputs, the selection circuit SEL sets one of the four inputs S, to S4 to a high level (1) using logic described later.

As a result, the corresponding analog switches sw1 to SW4
One of the external voltages 1 to V4 (where V 1 < V 2 < V 3 < Va) becomes conductive and the source line ○ becomes conductive. is output to.

The relationship between the input A (DI+) of the time control circuit TC and the output CTM is shown in the logic table of FIG. When the value of manually input data is 0 (that is, Ds=O), the input pulse signal TM
becomes the output as it is, and Dl! When = 1, output CTM
is always 1.

The relationship between the inputs B, C, CTM and the output of the arrester circuit SEL is shown in the logic table of FIG. When CTM is 0, other input B,
Regardless of the value of C (that is, the upper bits of the image signal data), all outputs S, ~SJ are always 0. When CTM is 1, the value (
In this example, two digits, C as the upper digit and B as the lower digit, are used.
Only the output 5X (X = Y + 1) according to Y (base value) is 1
becomes.

When the time control circuit TC and the selection circuit SEL output according to such logic, the source driver shown in FIG. 1 operates as follows.

When the least significant bit D6 of the image signal data is 1, the output CTM of the time control circuit TC is always 1, and the selection circuit SEL selects the upper 2 bits (Dl, D2) of the image signal data.
A decoder (decoder DE in Figs. 13 to 15) whose input is
The operation is similar to C).

Of course, depending on the value of the upper two bits of the image signal data, one of the outputs of 81 to S4 is set to 1, and the corresponding analog switch ASW is made conductive, and four levels of external voltages ■1 to ■4 are applied. Either one is output to the source line On.

When D9 (lowest via of image signal data) is 0, the same operation as above occurs when the time control pulse signal TM is at a high level (1), but when the pulse signal TM is at a low level (
0), the outputs S1 to S4 of the selection circuit SEL are all O regardless of the value of the upper two bits of the image signal data, and the source line 0° is in a high impedance state. That is, when the least significant bit of the image signal data is O, the output time of the external voltage to the source line O1 can be controlled by the pulse signal TM.

FIG. 4 shows an equinodal circuit for the load on the source line On. R
5 is the resistance of the source line, and CS is the capacitance of the liquid crystal picture element connected to the source line On. Further, v con is a common voltage applied to the counter electrode of the liquid crystal. Assuming that the time point at which the time control pulse signal TM changes from low level to high level is 1=0, the voltage v(t) output from the source driver in FIG. 1 to the source line O1 is as follows: V(t)=O( t<0) v(t)=V+ (0≦t).

In response to this change in output voltage, the voltage v ((1) applied across the capacitor C8 of the picture element, which is the load of the source line ON, is
It can be obtained by solving the simultaneous equations (% formula %). Here 1 (1)
is the current flowing to the source line ON. Solving this simultaneous equation gives VC(t)-Vcon+V+・(1-ex p(t/(Cs-Rs)) 1...(
1), and vc(t) approaches ■1 as shown in Figure 5. Therefore, before vc(t) approaches ■1 sufficiently,
By lowering the time control pulse signal TM to a low level and stopping output to the source line On when the desired value is reached, the voltage applied to the picture element can be set to an arbitrary value. In Figure 6, source line ○. When the voltage vi outputted to is Vl, v2, v3, v4, the voltage vc(t) applied to the picture element (v:
The changes in (t) and (t) are shown below. In FIG. 6, it is assumed that the intervals between the external voltage levels V1, 2, 3, and 4 are constant. Each voltage V+ (t)
From the above formula, v+ (t)=Vcon+V+°(1-exp (-
t/ (CssRs))IV2 (t) =Vcoh
+V2・(1-e x p (-t/ (Cs-Rs
) ) 1v3(t)=VcorI+■3・(l e X p(-t/ (Cs-Rs) ) ) Va (
t)=Vcon+Va・(1 e x p (-t/'(Cs-Rs)) 1
It is expressed as As can be seen in FIG. 6, V4(t) becomes equal to the voltage v3 at a certain time t3, and v3(t) becomes equal to the voltage ■2 at a certain time t2. These times t2
, t3 are obtained by solving the following equations.

V2”VCO gate ten v3・(1 eXp (t2/ (Cs-Rs))IV3-VC
ON+ V4・(1 eX p (t3/ (Cs-Rs))) Here, V
4-V3=V3-V2=V2 V+-Δ■, then v2=v, +ΔV V3=V, +2ΔV V4=V++3 Δ■ Therefore, the above equation becomes ■1+ΔV=Vcon+ (Vt+2ΔV) (1e
Xp(t2/ (Cs-Rs))1 ■1+2ΔV=Vcon+(Vt+2ΔV)(1exp
It is rewritten as (-t3/ (Cs-Rs)) 1. By solving these equations, t2 and t3 are calculated as t2=C8-Rs-I n ((Vt+2ΔV)/(Vt+2ΔV)1t
3=Cs-Rs-I n ((V++ 3ΔV) / (Vcorl + ΔV)1.The time difference t3-t2 is t
3-t2=C5-Rs・I n ((Vt+3ΔV)/(Vt+2ΔV)1
... (2) However, since Vt+3ΔV>Vt+2ΔV, t3-t2>o, that is, t3>t2 is always satisfied.

Similarly, t2-tI=Cs-R5・In [(V, +2ΔV)/(Vt+ΔV)1...
(3) and t 2 > t, so in the end, t 3 > t
The relationship 2>tl holds true. Therefore, the times t at which V3<V4(t)<V4 V2<V3 (t)<V3 Vl<v2 (t)<V2 Vl-ΔV<v2(t)<Vl -16~ are t3<t t2< t 1 , <1 0<1 . That is, the voltage applied to the picture element is ■1,
There is a unique point in time when the voltage is any value between (2), (3), and (4).

In the above equations (2) and (3), if ■1>>Δ■, then ta#t2#t+. Also, at this time, v4(1
), va(t), V2(t), and v+(t) are at exactly intermediate levels of external voltages ■1, ■2, ■3, and V4, respectively (V
J+V3)/2, (Vs+V2)/2, (V2+v
1) / 2 and vl - ΔV/2 all have approximately the same value.

Since the value of vl can be arbitrarily determined,
If we define ■1 so that the above relationship ■1〉〉Δ■ is satisfied, then
The exact middle value of each level (V4+V3)/2, <V3
+V2)/2, (V2+Vl)/2, V1ΔV/2
- is uniquely determined as the time during which is applied to the picture element. Therefore, by setting the width of the time control pulse signal TM shown in FIG. 6 to - for this time, it is possible to apply a voltage exactly between these values to the picture element with only a small number of external voltages. Note that normally, as the number of gradations to be displayed increases, ΔV becomes smaller, so the above-mentioned condition V]>>ΔV can be easily satisfied as the number of gradations increases.

FIG. 7 shows an example in which the time control circuit TC and selection circuit SEL shown in FIG. 1 are specifically constituted by a logic circuit including an AND element and an OR element. The time control circuit TC is simply an OR element 1
The selection circuit SEL can be constructed from four AND elements. FIG. 8 shows the timing relationship between the output pulse OE and the time control pulse signal TM input to the time control circuit TC. At the same time as the output pulse OE rises, the time control pulse TM becomes a zero level and starts outputting the external voltage ■1 to the source line 0°, and after 2 hours when the voltage of the picture element reaches an intermediate value, it is turned off. Go down to the level. At this point, the next output pulse OE rises, and the next voltage starts to be output from the source driver to the source line. The picture element becomes separated from the source driver,
This picture element will maintain a charged state of (V + 10V +++) / 2.

Digital image signal data Dils DI, D2 (7) in the source driver of this embodiment that operates in this way
To summarize the relationship between the value and the voltage applied to the liquid crystal C8,
The results are as shown in the table in Figure 9. By replacing the voltages at each level realized by this example as follows,
It is understood that the source driver of this embodiment has the same function as the circuit shown in FIG. 15 which requires eight levels of external voltage.

V+ AV/2 -” VII ■1 → ■1 (V ++ V2) / 2 → ■2■2
→ V3 (V 2 + V 3) / 2 → ■4■3
→ ■5(V3+V4)/2
→ ■6 v, -Vv In the above embodiments, the digital image signal data is made up of 3 bits, but even if the image signal data is made up of 4 bits in order to further increase the gradation to 16 levels, for example. In the signal voltage supply circuit according to the present invention, it is only necessary to prepare a 23-8 level external voltage and one time control pulse signal TM.

(Effects of the Invention) According to the present invention, when expressing gradation by applying signal voltages of different levels to picture elements based on digital image signal data, no voltage is sent out during the first half of one output period of the signal voltage. , one level of the external voltage is supplied to the picture elements only during the second half of the predetermined time period.

By calculating this time in advance based on the capacitance value of the picture element, etc., it is possible to reach the desired voltage at the end of one output period.

Therefore, it is also possible to apply a voltage exactly in the middle of a plurality of external voltages to the picture element.

In this manner, the drive circuit of the present invention does not require a predetermined number of external voltages to express a predetermined number of gradations, but a smaller number of external voltages can be used. As a result, the external voltage supply circuit can be made smaller, and the number of terminals in the drive circuit of the display circuit can also be reduced. Furthermore, since it is possible to apply a voltage with a finer step difference to the pixel than the step difference between levels of an external voltage source, even in cases where it is difficult to generate a voltage with a fine difference with an external voltage generation circuit, it is possible to apply a voltage with a finer step difference to the picture element. Tonal expression becomes possible.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a portion corresponding to one source line of a driving circuit of a liquid crystal display device using an embodiment of the present invention;
The figure shows a logic table of the relationship between the input and output of the time control circuit of the embodiment, FIG. 3 shows the logic table of the relationship between the input and output of the selection circuit of the embodiment, and FIG. is an equivalent circuit diagram of the load on one source line, Figure 5 is a graph showing the relationship between changes in the voltage level output to the source line and the voltage applied to the picture element, and Figure 6 is a graph showing the relationship between the voltage applied to the picture element and the voltage applied to the source line. A graph showing changes in the voltage of picture elements when output to the line, Figure 7 is a circuit diagram of the signal voltage output circuit showing the inside of the time control circuit and selection circuit in more detail, Figure 8 is the output pulse FIG. 9 is a timing diagram showing the relationship between the input image signal data and the output voltage of the drive circuit of the embodiment, and FIG. 10 is a timing diagram showing the relationship between the time control pulse signal input to the time control circuit. Circuit diagram of the drive circuit for image signals, 1st
Figure 1 is a circuit diagram of only one source line extracted from the circuit, Figure 12 is a timing diagram showing the operation of the drive circuit, and Figure 13 is a method in which a digital sampling circuit is provided for each source line. Figure 14 is a circuit diagram of only one source line extracted from the drive circuit, and Figure 15 is a circuit diagram of a conventional digital drive circuit when the image signal data is 3 bits. be. Dθ, I) I, D2... Image signal data, MSIIP
...Sampling memory, M14...Hold memory, TC...Time control circuit, SEL...Selection circuit,
A, SW, ~ASW4...Analog switch, On/
...Source line, TsNPn...Sampling pulse, OE...Output pulse, ■1 to ■4...External voltage, TM...Time control pulse signal or more

Claims (1)

[Claims] 1. A drive circuit for a display device provided with a plurality of parallel signal electrodes to which picture elements each having an electric capacity are connected, the voltage supply outputting a plurality of voltages at different levels. means, time control means for generating a pulse signal that divides one output period into a first period and a second period according to a portion of the input digital image data; During one period, no voltage is sent to the signal electrode, and during the second period, one level of voltage corresponding to the remainder of the input digital image data among the plurality of voltages output from the voltage supply means is applied to the signal. A drive circuit for a display device comprising means for selecting a voltage to be sent to an electrode.