JPH04134785A - First-in first-out memory device - Google Patents

Abstract

PURPOSE:To cope with a high speed response by making a gate to be enable when a data does not exist in a front state register, and executing a control to shut off a signal which express the presence of the data to be transmitted to the front stage. CONSTITUTION:When no data exists in the front stage register, the corresponding gate is made enable, and the control is executed to shut off the signal which expresses the presence of the data to be transmitted to the front stage. That is, the AND gate 21C shuts off a data status signal which expresses the presence of the data to be transmitted to the front stage when the gate signal become enable. Also, an OR gate 21b produces an output ready signal which expresses the presence of the data in its own register part or the presence of the data in the register with a later stage than itself. Then, the data to be outputted can be taken out passing the gate and the data line and bypassing, without waiting for it to arrive at the final stage of the register. Thus, the high speed response can be coped with.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention provides a synchronous first-in, first-out memory device with a shift register configuration, that is, a F I F O (First In First Out) memory device.
The present invention relates to a first out (first in, first out) memory device, and more particularly to an improvement in a FIFO memory device that reduces data retrieval time.

<Prior art> FIFO memory devices are used for the purpose of improving data transfer performance when data is transferred using DMA (direct memory access) between circuits with two different data transfer speeds. , which are often used, include synchronous and asynchronous methods.

FIG. 4 is a block diagram showing an example of a synchronous FIFO memory device. This memory device is a FIFO using dual port 1, and is basically one RA.
The configuration is such that the M45 is accessed alternately from the two ports 4]42 (person) j port and the output port. In this case, the selector 44 selects the hash connected to the port with higher priority by the arbitration circuit, and the RAM 4
It is connected to the lotus on the 5 side and is configured to access the RAM.

FIG. 5 is a configuration block diagram showing an example of an asynchronous FIFO memory device. This memory device is constructed by connecting in series five circuits 52, 53, . Each circuit is activated by the clock from the previous stage, but a delay circuit is installed inside.
Therefore, the clock is delayed and output to the next stage. As a result, the entire device functions like a shift register, and data flows through the flip-flops. In this case, input and output are completely asynchronous.

<Problems to be Solved by the Invention> When a conventional FIFO memory device having such a configuration is used for data transfer between the circuits described above, there are the following problems.

In other words, synchronous FIFO memory is basically RAP
Is there an advantage in increasing the capacity because vl is used? Access to RAM is controlled by an arbitration circuit, so only one of the human input and output ports can be used.
Cannot handle high-speed response.

On the other hand, asynchronous FIFO memory does not allow high-speed access, but it is difficult to increase the memory capacity due to the introduction of flip-flops, and it is prone to glitches (because it uses internal delays). However, there were problems such as the occurrence of hairs (whiskers) and difficulty in conducting simulations for circuit verification.

The present invention has been made in view of these points, and provides a FIFO mesori device that can perform stable data transfer between circuits with different data transfer speeds, shorten data retrieval time, and support high-speed response. The purpose is to provide

Means for Solving the Problems> FIG. 1 is a basic block diagram of the FIFO memory device of the present invention. In the figure, 11. ．． 1.213...
Reference numeral 4 indicates a plurality of data register groups, and 4 indicates a data line having a bus configuration for outputting data to the outside, and is arranged in parallel with the plurality of data register groups.

31, 32, 33... are each data register 1], 12.
A plurality of gates output shift data from 13, . . . to data line 4.

21, 22, 23... sends out the synchronized clock INCLK for shifting data to each data register, and the gate signal GATE that controls each gate.
This is a register control circuit group that outputs .

Function> Multiple data register groups are connected in series to each other and FIF
It constitutes O.

The register control circuit group controls the transmission of the synchronous clock INCLK to be applied to the registers depending on whether data can be taken in or whether the register at the previous stage can receive data. At the same time, the presence or absence of data in the register is notified to the previous stage.

Furthermore, when outputting data to the outside, if there is data in its own register and no data exists in the previous register, the corresponding gate is enabled, and when the gate is enabled, the data to be sent to the previous stage is Control is performed to block the signal indicating the presence/absence.

This makes it possible for the data to be output to bypass the gate and be taken out at high speed without waiting for the data shift to reach the final stage register.

<Example> Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a configuration diagram showing an embodiment of the present invention. Since the configuration of each stage is the same, only the configuration of two stages is representatively shown in the figure, and the same parts as those in FIG. 1 are given the same reference numerals.

register], 1. , 12, for example, a D-type flip-flop is used as shown in the figure, and the input data led to the D input terminal is taken in at the rising edge of the clock NCLK given from the register control circuits 21 and 22. .

Although the figure only shows a 1-bit register,
In reality, as many flip-flops as the number of bits of input data are arranged in parallel, and each stage of flip-flops has a
The same clock INCLK is applied in parallel so that a plurality of bits are shifted in parallel.

Register control circuits 21 and 22 have the same configuration.

Flip-flop 21A receives an input status signal (INPUTSTATUS) led to the D input terminal.
AND gate 21F (input ready signal (IN
PUUTREAIJY) is another key component). This input status signal is a signal indicating whether or not there is data to be taken into the register section, and is given from the outside (for example, a processor).

Pretending to capture the input status signal.

The Q output of the flop 21A is passed through the gate 2IC,
It is applied to the D input terminal of the flip-flop 22A in the preceding stage. This Q output is the data status signal (D
ATASTATUS), which is a status signal indicating whether or not there is data in its own register section (presence or absence of data).

OR gate 2] G is the inverted output Q of the flip-flop 21A and the output of the previous stage OR gate 22G (LOAD signal, a signal indicating that the previous stage is ready to take in data. On the output side of the FIFO, it is a strobe signal to take out data. ). This final stage OR signal is an input ready signal (INPUUTR).
EADY) to an external processor.

ANDGATE 21. D is the load signal (LOAD) that is input manually when extracting data from the FIFO, the data status signal (DATASTATUS) output from Q that indicates that there is data in its own register, and the data that is not present in the previous stage register. And gate 2 that shows that
It inputs the signal from 2E and outputs a gate signal (GATE) that controls the gate 31.

The AND gate 21C is provided to cut off a data status signal indicating the presence or absence of data to be sent to the previous stage when the gate signal (GATE) is enabled. Output ready signal (OUTPUTREAD
Y).

The operation of the device configured as described above will be explained as follows.

FIG. 3 is a time chart showing the operation.

When inputting data to FIFO, clock (CLK)
Data (DATA IN) and input status signal (INPUTSTATUS) are input in synchronization with the .

At this time, in the n-th stage, the register control circuit outputs a clock (INCLK) for taking in data based on this input status signal. Further, the input status signal (INPUTSTATUS) itself is output as a data status signal (INSTSn) at the nth stage at the rising edge of the clock (a).

When the first data is imported, as shown in (b),
Output ready signal (OUTPUT
READY) is output. The output section J receives this output ready signal and outputs the load signal LOAD (C
) and extract the data. In this case, the first data in the FIFO is output to the output section, but the data status signal (INS) for the first data is
TS) is cut off by the gate 21D by the load signal, and at the rising edge of the clock (CLK), there is no data as shown in (d).

When the load signal is not input manually, if data exists in the FIFO, it is shifted as is by the clock (INCLK).

<Effects of the Invention> As explained in detail above, the present invention allows data to be output to be bypassed through gates and data lines and retrieved without waiting for the data shift to reach the final stage register. It is configured so that it can be done. Therefore, until now, the waiting time from when data is written to the FIFO to when it is taken out depends on the frequency of the clock CLK and F
Although the data was proportional to the number of IFO stages, once data is written, it can be retrieved immediately regardless of the number of FIFO stages, and it is possible to provide a FIFO mesori device that can handle high-speed response.

[Brief explanation of drawings]

Fig. 1 is a basic block diagram of the FIFO memory device of the present invention, Fig. 2 is a configuration block diagram showing an embodiment of the invention, Fig. 3 is a time chart showing its operation, and Fig. 4 is a synchronous type. FIG. 5 is a block diagram showing an example of an asynchronous FIFO memory device. 11.12.13...Data register group 21.22.
23...Register control circuit group 31.32.33...
Gate 4...Data lines 21A, 22A...Flip-flops 21B, 22B
...Or gate 2IC, 22C...And gate 21D, 22D...And gate 21E, 22E...And gate

Claims (1)

[Claims] A data register group in which a plurality of registers are connected in series, a data line having a bus configuration that outputs data to the outside, and a plurality of gates that output shift data from each register to the data line; A register control circuit group that sends out a synchronized clock for shifting data to each of the registers and outputs a gate signal that controls each of the gates, and the register control circuit group determines whether data can be taken in or not. Alternatively, it controls the sending of a synchronous clock to a register depending on whether the register in the previous stage can receive data, and at the same time notifies the previous stage of the presence or absence of data in the register, and when outputting data to the outside, it controls the sending of a synchronous clock to the register. The control is characterized in that when there is data and there is no data in the register at the previous stage, the corresponding gate is enabled, and when the gate is enabled, a signal indicating the presence or absence of data to be sent to the previous stage is cut off. A first-in, first-out memory device.