JPH04134602A - Data storage device - Google Patents

Abstract

PURPOSE:To improve the peak shift or the amplitude fluctuation of a data part caused by the resolution of a read signal by switching two transversal filters when reading out a gap part and when reading out data information. CONSTITUTION:A cosine equalization circuit changeover signal 106 is switched at the same time when a read starting signal 107 becomes active or before that, or before data starting information, and from the same time when the read starting signal 107 becomes active or before that through before the data starting information, a second cosine equalization circuit 40 is selected, and other than that, a first cosine equalization circuit 11 is selected. The first cosine equalization circuit 11 has a gain transmitting characteristic in which a high frequency area is raised in order to improve the peak shift or the amplitude fluctuation caused by the resolution of the read signal. On the other hand, the characteristic of the second cosine equalization circuit 40 reduces the raise of the high frequency area and the fall of the signal of the gap part, and improves the ratio of the signal to the noise of the gap part.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data storage device, and more particularly to a data storage device having a signal processing circuit for phase-synchronized data.

[Conventional technology]

Among conventional data storage devices, a data storage device having a signal processing circuit for phase-locked data in particular converts a reproduced signal read from a data storage section into a data pulse. A phase synchronization circuit that inputs this data pulse and generates a read clock for data demodulation performs a pull-in operation using a gap section provided at the beginning of the stored data and consisting of data of the same cycle.

The readout signal processing circuit for this purpose is provided with a transversal filter in order to improve fluctuations in peak shift amplitude caused by the resolution of the readout signal.

[Problem to be solved by the invention]

The transversal filter of the read signal processing circuit of the conventional data storage device as described above has a gain transfer characteristic with an increased high frequency region in order to improve the peak shift and amplitude fluctuation of the read signal. For this reason, the signal-to-noise ratio of a read signal with many low frequency components deteriorates, and the temporal fluctuation of the peak pulse increases. On the other hand, since the data in the gap portion of the stored data has a pattern with the same period, there is almost no peak shift or amplitude fluctuation caused by the resolution. Therefore, only the temporal fluctuation of the peak pulse due to the transversal filter increases, and the quality of data in the gap portion deteriorates.

The data in the gap is used for the pull-in operation of the phase synchronization circuit that generates the read clock for data demodulation, so if there is a large amount of temporal fluctuation in the data pulse, the pull-in operation will be adversely affected and it will take longer to complete the pull-in operation. Therefore, there is a drawback that erroneous detection of stored data occurs.

[Means to solve the problem]

The data storage device of the present invention is a data storage device that reads out stored data having a gap portion consisting of data of a constant period at the beginning and performs a pull-in operation of a phase synchronization circuit to reproduce data information. Two different transversal filters are provided, and the two transversal filters are switched and used when reading out the gap portion and when reading out the data information.

That is, the data storage device of the present invention includes an amplifier circuit that inputs a reproduction signal that is an output signal of a magnetic head, a filter that inputs an output signal of the amplifier circuit amplified by the amplifier circuit, and a filter that removes high-frequency components in the filter. a first cosine equalization circuit and a second cosine equalization circuit to which the filter output signal is input; a reproduction control circuit to which the reproduction control signal is input and output a cosine equalization circuit switching signal and a read start signal; A first cosine equalization circuit output signal whose peak shift has been improved in the first cosine equalization circuit is inputted to a first input terminal, and a second cosine equalization of the output signal of the second cosine equalization circuit is performed. The circuit output signal is inputted to the second input terminal, and the cosine equalization circuit switching signal inputted from the reproduction control circuit to the third input terminal causes the first cosine equalization circuit output signal, the second cosine, etc. a switching circuit for switching and outputting a synchronization circuit output signal; a peak detection circuit for inputting a switching circuit output signal from the switching circuit and outputting a peak pulse train; and a peak detection circuit for outputting a synchronized data pulse from the peak pulse train by the read start signal The device includes a phase synchronization circuit that generates and outputs a read clock, and a demodulation circuit that demodulates stored information using the synchronized data pulse and the read clock.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In FIG. 1, a reproduced signal 101, which is an output signal of a magnetic head 1, is input to an amplifier circuit 2, and an amplifier circuit output signal 102 amplified by the amplifier circuit 2 is input to a filter 3, which extracts high frequency components. The removed filter output signal 103 is input to the first cosine equalization circuit 11 and the second cosine equalization circuit 40, and the first cosine equalization circuit 11 is a first cosine equalization circuit with improved peak shift. The output signal 201 is input to the first input terminal of the switching circuit 41, and the second cosine equalization circuit output signal 240 of the output signal of the second cosine equalization circuit 40 is input to the second input terminal of the switching circuit 41. input, switching circuit 41
inputs the cosine equalization circuit switching signal 106 of one output signal of the reproduction control circuit 6 to the third input terminal, and outputs the first cosine equalization circuit output signal 201 and the second cosine equalization circuit output signal 240.
and is outputted to the peak detection circuit 4 as a switching circuit output signal 241. The peak detection circuit 4 outputs its output signal, a peak pulse train 104, to the phase synchronization circuit 5, and the phase synchronization circuit 5 generates a synchronized data pulse 105 and a read clock 202 from the peak pulse train 104, and demodulates it. The demodulation circuit 12 demodulates the stored information using these signals. On the other hand, the reproduction control circuit 6
Input the reproduction control signal 108 and select the cosine equalization circuit switching signal 1
06 to the switching circuit 41, and a read start signal 107 to the phase synchronization circuit 5.

FIG. 2 is a circuit diagram showing details of the first equalized cosine circuit of the embodiment of FIG. 1.

As shown in FIG. 2, the filter output signal 103 is input to the delay line 21 and the buffer circuit 23, and is grounded via a resistor 24 for matching the impedance of the delay line 21. The output signal of the delay line 21 is input to the positive input terminal of the subtracter 22. on the other hand,
The output signal of the buffer circuit 23 is input to the negative input terminal of the subtracter 22 via a capacitor 25 and a resistor 26a.

A negative input terminal of the subtracter 22 is grounded via a resistor 27a.

In the internal circuit of the second cosine equalization circuit 40, the resistance values of the resistors 26a and 27a in FIG. 2 are changed to form resistors 26b and 27b.

Next, the operation of the above embodiment will be explained.

3 is a timing chart showing the operation sequence of the embodiment of FIG. 1, and FIG. 4 is a characteristic diagram showing the transfer characteristics of the first and second equalizing cosine circuits of the embodiment of FIG. 1.

As shown in FIG. 3, the read start signal 107 becomes active at the beginning of the gap portion of the peak pulse train 104, and the phase synchronization circuit 5 starts the pull-in operation at this point. The cosine equalization circuit switching signal 106 is the read start signal 1
07 becomes active and before the data start information (DM), and from the same time or before the read start signal 107 becomes active until before the data start information (DM). selects the second cosine equalizer 40, otherwise selects the first cosine equalizer 1
Select 1.

The first cosine equalization circuit 11 is a type of transversal filter, and its transfer characteristic is expressed by the following equation.

G(f)=l−Kcos2πfτ (K: tap gain, f: signal horse 1t, r Tilley line! time delay) Tap gain by switching between the second cosine equalization circuit 40 and the first cosine equalization circuit 11 becomes as follows.

11tWt! I40: K=R27b/(R26b+
R27b) LH$tl! ill: K=R27a/(
R26a+R27a) FIG. 4 is a characteristic diagram showing these characteristics, where the solid line reference numeral 501 curve is the characteristic of the first cosine equalization circuit 11, and the broken line reference numeral 502 is the second cosine equalization circuit 11. These are the characteristics of the string equalization circuit 40. fs is the frequency of the signal at the gap portion. First cosine equalization circuit 11
has a gain transfer characteristic in which the high frequency region is increased in order to improve the peak shift and amplitude fluctuation caused by the resolution of the readout signal. On the other hand, the characteristics of the second cosine equalization circuit 40 are such that the rise in the high frequency region is reduced and the drop in the signal in the gap portion is reduced, thereby improving the signal-to-noise ratio of the signal in the gap portion. This reduces the phase fluctuation of the peak pulse in the gap.

The phase synchronization circuit 5 extracts a read clock 202 from the peak pulse train 104 in order to generate synchronized data pulses 105 synchronized with the average phase of the peak pulse train 104.
generate. Read clock 202 and peak pulse train 1
In order to synchronize the average phase of 04, it is necessary to match the phases of the read clock 202 and the peak pulse train 104 at the start of reading, and for this reason, a gap section consisting of data of the same period is provided before the stored data. There is. The peak pulse in this gap portion is required to have a small phase variation in order to perform phase matching.

〔Effect of the invention〕

As explained above, the data storage device of the present invention has the effect of reducing the phase fluctuation of the peak pulse in the gap portion and improving the peak shift and amplitude fluctuation of the data portion caused by the resolution of the read signal. be. Therefore, it is possible to obtain a highly reliable data storage device in which the pull-in operation of the phase synchronization circuit is stabilized and the reliability of reproduction of read information is improved.

3 is a timing chart showing the operation sequence of the embodiment of FIG. 1, and FIG. 4 is a characteristic showing the transfer characteristics of the first and second equalizing cosine circuits of the embodiment of FIG. 1. It is a diagram.

1...Magnetic head, 2...Amplification circuit,
3... Filter, 4... Peak detection circuit, 5... Phase synchronization circuit, 6... Regeneration control circuit, 11... First Cosine equalization circuit, 12...
... Demodulation circuit, 21 ... Delay line,
22...Subtractor, 23...Buffer circuit, 24, 26a, 27a...Resistor, 25...
... Capacitor, 40 ... Second cosine equalization circuit, 41 ... Switching circuit.

Claims (1)

[Claims] 1. In a data storage device that reads out stored data having a gap portion consisting of data of a constant period at the beginning and performs a pull-in operation of a phase synchronization circuit to reproduce data information, A data storage device comprising two different transversal filters, the two transversal filters being switched and used when reading out the gap section and when reading out the data information. . 2. An amplifier circuit that inputs a reproduced signal that is an output signal of the magnetic head, a filter that inputs the amplifier circuit output signal amplified by the amplifier circuit, and a filter output signal that removes high frequency components from the filter. a first cosine equalization circuit and a second cosine equalization circuit; a reproduction control circuit that inputs a reproduction control signal and outputs a cosine equalization circuit switching signal and a read start signal; and the first cosine equalization circuit. A first cosine equalizer output signal with improved peak shift is input to a first input terminal, and a second cosine equalizer output signal of the output signal of the second cosine equalizer is input to a second input terminal. switching between the first cosine equalization circuit output signal and the second cosine equalization circuit output signal by the cosine equalization circuit switching signal inputted to the terminal and inputted from the reproduction control circuit to the third input terminal; a switching circuit that outputs a switching circuit; a peak detection circuit that receives a switching circuit output signal from the switching circuit and outputs a peak pulse train; and generates and outputs a synchronized data pulse and a read clock from the peak pulse train in response to the read start signal. A data storage device comprising: a phase synchronization circuit that demodulates stored information using the synchronization data pulse and the read clock.