JPH0556029A - Code conversion circuit - Google Patents

Abstract

PURPOSE:To improve the jitter immunity by expanding a signal pulse width resulting from applying equalization amplifier to a transmission code data and using an extracted timing signal so as to increase an identification margin. CONSTITUTION:A pulse width of an RZ code data 11 from a level conversion circuit 5 is expanded by a pulse expansion circuit 6, from which a signal 12 whose pulse width is expanded is obtained. A delay of a variable delay circuit 3 is selected so that an identification point of time of a clock signal 23 extracted by a timing extract circuit 2 comes in the vicinity of a center of the pulse width of the signal 12. Thus, the signal pulse 12 is correctly triggered at a leading edge of a signal 13 by a D flip-flop 4 and an NRZ code data signal 14 is correctly generated. Thus, the identification margin is increased and jitter immunity is almost doubled.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal transmission device, and more particularly, to a code conversion circuit for converting code data transmitted on a signal transmission path into waveform data after converting the waveform data.

[0002]

2. Description of the Related Art In digital transmission, a new pulse is reproduced from a received pulse added with waveform distortion caused by the characteristics of a transmission line and noise mixed in during transmission, so that factors that impair transmission quality are accumulated. The feature is that multi-relay transmission can be performed with high quality without doing so. In the digital transmission, there is a code conversion circuit for converting the RZ code into the NRZ code. A conventional example of the code conversion circuit is shown in FIG.

In FIG. 3, the RZ code data transmitted through the transmission line 21 is input to the waveform equalization circuit 1 and shaped and amplified into a waveform suitable for discrimination, and then the signal 22 is supplied to the timing extraction circuit 2 and the level conversion circuit 5. Is output. This signal 2
2 is level-converted by the level conversion circuit 5, and becomes RZ code data 11 of a logic level signal having only two signal levels of a high level signal and a low level signal. The RZ code data 11 is input to the D terminal of the D flip-flop 4. At the same time, the timing extraction circuit 2 generates a clock signal 23, which is a timing pulse extracted from the RZ code data transmitted from the signal 22 through the transmission line 21 by the self-timing method, and outputs the clock signal 23 to the variable delay circuit 3. .. In the variable delay circuit 3, the clock signal 23 is delayed by 1/4 cycle with respect to the RZ code data 11 to form the clock signal 13. This clock signal 13 is used to identify the presence / absence of a pulse in the received RZ code data, in order to identify the D flip-flop 4
Is input to the T terminal of. D of D flip-flop 4
The RZ code data 11 input to the terminal is generated as the NRZ code data signal 14 by being triggered by the rising edge of the clock signal 13 (this is the identification time point). This is shown in FIG.

[0004]

By the way, in the code conversion circuit 30 for extracting the timing pulse for identifying the presence or absence of the pulse by the self-timing method, the influence of the jitter of the pulse pattern of the transmitted RZ code data is affected. Appears directly in the timing pulse. Therefore, the following jitter tolerance characteristic is defined as one that determines the superiority or inferiority of the transmission pulse reproduction performance of the code conversion circuit 30.

Jitter tolerance

[0006]

[Equation 1]

[0007] E: Identification margin (UI _pp) f _o: Tank natural frequency (H _z) f _j of (resonant circuit): Jitter Frequency (H _z) Q: jitter tolerance represented by Q the equation 1 of the tank a Is higher, the NRZ code data is reproduced more correctly from the received RZ code data. The relationship between the jitter frequency f _j and the jitter tolerance a is shown in a logarithmic graph of FIG. As can be seen from FIG. 5, the jitter tolerance a becomes worse as the jitter frequency f _j increases, and becomes a constant value equal to the discrimination margin E at a certain frequency or higher. Therefore, in order to improve the jitter tolerance a, the tank Q may be reduced or the discrimination margin E may be increased.

If the tank Q is made small, the amplitude characteristic of the resonance circuit in the timing extraction circuit 2 is deteriorated, and as a result, a timing pulse extraction error occurs and the NR is correct.
Z code data cannot be reproduced. That is, the code conversion circuit 30
The entire zero continuous proof stress characteristic will be deteriorated. Also,
As shown in FIG. 4, the discrimination margin E can be increased to a maximum of 1/2 UI _pp because the rising edge of the timing pulse signal 13 is used as the discrimination time point. As described above, the optimum values of the tank Q and the discrimination margin E are uniquely determined from the circuit characteristics, and it is difficult to freely change the values.

Therefore, the present invention is to provide a code conversion circuit having an excellent jitter tolerance a without changing their electrical characteristics.

[0010]

A code conversion circuit according to the present invention comprises a waveform equalization circuit for equalizing and amplifying a received waveform by equalizing input pulse code data, and an output signal of the waveform equalization circuit. A timing extraction circuit for extracting the timing signal; a variable delay circuit for delaying the timing signal;
A pulse expansion circuit for expanding the pulse width of the output signal of the waveform equalization circuit, and an identification circuit for identifying the pulse in the output signal of the pulse expansion circuit with the output signal of the variable delay circuit. There is.

[0011]

The pulse width of the code data equalized and amplified by the waveform equalization circuit is expanded by the pulse expansion circuit.
The timing extraction circuit extracts and generates a timing pulse composed of a pulse synchronized with the code data. Further, the delayed delay pulse is delayed by the variable delay circuit so that the rising edge of the timing pulse is located in the middle of the pulse width of the code data. Then, with this delay timing pulse, in the identification circuit, the presence or absence of the pulse of the code data is triggered to be identified, whereby new code data is generated. By extending this pulse width, the discrimination margin can be greatly improved.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, referring to FIGS.
Will be described below with reference to. 1 is a block circuit diagram of an embodiment of the present invention, and FIG. 2 shows a timing chart of each signal of the circuit in FIG. The same parts as those in the conventional example are designated by the same reference numerals. In FIG. 1, the transmission line 21 is connected to the input terminal of the waveform equalization circuit 1, and the output of the waveform equalization circuit 1 is input to the level conversion circuit 5 and the timing extraction circuit 2, respectively. The output of the level conversion circuit 5 is input to the pulse expansion circuit 6, and the output of the timing extraction circuit 2 is input to the variable delay circuit 3. The output of the pulse expansion circuit 6 is input to the D terminal of the D flip-flop 4, and the output of the variable delay circuit 3 is input to the T terminal of the D flip-flop 4. The operation of the above configuration will be described in detail below.

The RZ code data transmitted through the transmission line 21 is equalized and amplified by the waveform equalization circuit 1 so that the received waveform is equalized and amplified so that the signal-to-noise ratio is improved and the intersymbol interference is minimized. It is said that. The equalized and amplified signal 22 is level-converted by the level conversion circuit 5 to be the RZ code data 11 of the logic level signal. This RZ code data 11
Is expanded by the pulse expansion circuit 6 to have a maximum pulse width of 1 UI _pp to obtain a signal 12. This signal 12 is input to the D terminal of the D flip-flop 4, which is the identification circuit.

Separately from this, in the timing extraction circuit 2,
A clock signal 23, which is a timing pulse, is extracted from the RZ code data transmitted from the signal 22 through the transmission path 21 by the self-timing method, and is output to the variable delay circuit 3. In the variable delay circuit 3, the clock signal 23 is delayed by the amount described below with respect to the RZ code data 11 to form the clock signal 13. The clock signal 13 is input to the T terminal of the D flip-flop 4 in order to identify the presence or absence of a pulse in the received RZ code data. The RZ code data 11 input to the D terminal of the D flip-flop 4 is regenerated as the NRZ code data signal 14 by being triggered by the rising edge of the clock signal 13 (this is the identification time point).

Next, the timing relationship of each signal will be described below with reference to FIG. The pulse width of the RZ code data 11 output from the level conversion circuit 5 has a width from time t0 to time t1 in the T1 cycle.
This RZ code data 11 is sent to the pulse expansion circuit 6 at time t0.
The signal 12 is expanded to the width from the time t2 to the time t2. The delay amount of the variable delay circuit 3 is determined so that the rising edge of the clock signal 23 extracted by the timing extraction circuit 2, that is, the identification time point is near the center of the pulse width of the signal 12. As a result, the pulse of the signal 12 is correctly triggered by the rising edge of the signal 13 at the time t1 in the D flip-flop 4, and the NRZ code data signal 14 is correctly generated. Conversely speaking, the delay amount of the variable delay circuit 3 is set to an amount that can correctly trigger the pulse of the signal 12 expanded by the pulse expansion circuit 6.

As described above, in order to identify the pulse of the RZ code data, the pulse width is extended as much as possible and the clock signal 13 is triggered to identify the presence or absence thereof. It has become possible to increase the size to about 1 UI _pp . As a result, the discrimination margin E can be doubled and the jitter tolerance a can be doubled as compared with the conventional one. Moreover, the selectivity of the delay amount of the variable delay circuit 3 is increased, and the reliability of the entire code conversion circuit can be improved. Although the code conversion circuit for converting RZ code data to NRZ code data has been described in the above embodiment, it is used for a circuit for converting a pulse signal having other periodicity into another pulse signal. It may be provided, or it may be used in a circuit for reproducing code data that is simply attenuated due to the characteristics of the transmission path.

[0017]

As described above, the code conversion circuit of the present invention extends the pulse width of the signal obtained by equalizing and amplifying the transmitted code data, and identifies it by the timing signal extracted from the code data. By increasing the discrimination margin, the jitter tolerance characteristic can be improved without changing the electrical characteristic such as changing the tank Q of the timing circuit. Therefore, since the discrimination margin is maximized as compared with the conventional case, the presence or absence of the pulse of the input signal can be sufficiently discriminated even if the jitter frequency of the timing signal is large. Moreover, this can be achieved only by adding simple circuit components, and a code conversion circuit with fewer identification errors can be realized.

[Brief description of drawings]

FIG. 1 is an example of the present invention.

FIG. 2 is a diagram showing a timing chart of the present invention.

FIG. 3 is a diagram showing a conventional example.

FIG. 4 is a diagram showing a timing chart of a conventional example.

FIG. 5 is a diagram showing a relationship between a jitter frequency f _j and a jitter tolerance a.

[Explanation of symbols]

 1 Waveform Equalization Circuit 2 Timing Extraction Circuit 3 Variable Delay Circuit 4 D Flip-Flop 5 Level Conversion Circuit 6 Pulse Expansion Circuit 11 RZ Code Data 12, 22 Signal 13 Clock Signal 14 NRZ Code Data Signal 21 Transmission Line 23 Clock Signal 30 Code Conversion circuit

Claims (1)

[Claims] 1. A waveform equalizer circuit for equalizing and amplifying a received waveform of input pulse code data in equal proportion, a timing extraction circuit for extracting a timing signal from an output signal of the waveform equalizer circuit, and the timing. A variable delay circuit that delays a signal, a pulse expansion circuit that expands the pulse width of the output signal of the waveform equalization circuit, and a pulse in the output signal of the pulse expansion circuit is identified by the output signal of the variable delay circuit. A code conversion circuit comprising: an identification circuit.