JPH04133450A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH04133450A JPH04133450A JP25666990A JP25666990A JPH04133450A JP H04133450 A JPH04133450 A JP H04133450A JP 25666990 A JP25666990 A JP 25666990A JP 25666990 A JP25666990 A JP 25666990A JP H04133450 A JPH04133450 A JP H04133450A
- Authority
- JP
- Japan
- Prior art keywords
- film
- opening
- insulating film
- antireflection
- selective growth
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000000463 material Substances 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 abstract description 15
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 5
- 239000005380 borophosphosilicate glass Substances 0.000 abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 abstract description 2
- 238000000059 patterning Methods 0.000 abstract description 2
- 238000004544 sputter deposition Methods 0.000 abstract description 2
- 238000005229 chemical vapour deposition Methods 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 7
- 239000010410 layer Substances 0.000 description 7
- 238000012545 processing Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 4
- 238000001459 lithography Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- NXHILIPIEUBEPD-UHFFFAOYSA-H tungsten hexafluoride Chemical compound F[W](F)(F)(F)(F)F NXHILIPIEUBEPD-UHFFFAOYSA-H 0.000 description 3
- 239000012535 impurity Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- -1 As5G) is formed Chemical compound 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000003667 anti-reflective effect Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000002209 hydrophobic effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置の製造方法に関する。本発明は、
例えば、高度に微細化・集積化された半導体集積回路の
製造等に用いることができる。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device. The present invention
For example, it can be used to manufacture highly miniaturized and integrated semiconductor integrated circuits.
本発明は半導体装置の製造方法において、基体上の絶縁
膜上に反射防止膜を形成した材料に開口を設けて選択成
長材料を成長させる場合に、該反射防止膜上に更に上層
絶縁膜を設けておくことにより、反射防止膜上に選択成
長材料が成長することを防止し、もって良好な選択成長
を行わせるようにしたものである。The present invention relates to a method for manufacturing a semiconductor device, in which an opening is formed in a material on which an anti-reflection film is formed on an insulating film on a substrate to grow a selectively grown material, and an upper insulating film is further provided on the anti-reflection film. This prevents the selective growth material from growing on the antireflection film, thereby allowing good selective growth to occur.
半導体装置の分野ではますます微細化・集積化が進んで
いる。例えば半導体集積回路の最小加工寸法は年々微細
化しており、研究開発レベルでは、例えば、0.50μ
m以下の0.35μmのレベルになるに至っている。特
にコンタクトホール等の開口の寸法は、0.4μm程度
となっている。コンタクトホールはこれを導電性物質で
埋め込んで接続をとらなければならないが、このように
微細な開口寸法のホールを埋め込むのは容易ではない。In the field of semiconductor devices, miniaturization and integration are progressing more and more. For example, the minimum processing size of semiconductor integrated circuits is becoming finer year by year, and at the research and development level, for example, 0.50μ
It has reached a level of 0.35 μm, which is less than m. In particular, the dimensions of openings such as contact holes are approximately 0.4 μm. The contact hole must be filled with a conductive material to establish a connection, but it is not easy to fill a hole with such a minute opening size.
かかる微細開口を埋め込む技術として、選択成長材料の
堆積技術が注目されている。As a technique for burying such fine openings, a selective growth material deposition technique is attracting attention.
その代表的なものは、W(タングステン)の選択CVD
技術である。これは、フッ化タングステン(WF、)ガ
スを用いてCVDすると、Wは酸化膜上には成長せず、
ポリシリコンやシリコン表面に選択的に成長することを
利用したものである。A typical example is W (tungsten) selection CVD.
It's technology. This is because when CVD is performed using tungsten fluoride (WF) gas, W does not grow on the oxide film.
It utilizes selective growth on the surface of polysilicon or silicon.
即ち図2(A)に示すように、シリコンやポリシリコン
の基体1上に酸化膜(SiO□や、PSG、BPSG、
As5Gなどの不純物含有酸化シリコン等)から成る絶
縁膜2が形成されて成る構造について、該絶縁膜2にコ
ンタクトホールとして開口3を形成して図2(B)のよ
うにし、その後WF6ガスによりCVDを行うと、Wは
酸化膜である絶縁膜2には成長ぜず、基体1が露出した
部分にのみ成長するので、図2(C)に示すように開口
2の底部からWが順次成長して埋め込まれ、良好な埋め
込み部4が選択的に開口2内にのみ形成される。That is, as shown in FIG. 2A, an oxide film (SiO□, PSG, BPSG, etc.) is formed on a silicon or polysilicon substrate 1.
Regarding the structure in which an insulating film 2 made of impurity-containing silicon oxide (such as As5G) is formed, an opening 3 is formed as a contact hole in the insulating film 2 as shown in FIG. 2(B), and then CVD is performed using WF6 gas. When this is done, W does not grow on the insulating film 2, which is an oxide film, but only on the exposed part of the base 1, so W grows sequentially from the bottom of the opening 2 as shown in FIG. 2(C). A good buried portion 4 is selectively formed only in the opening 2.
一方、上述したように最小加工寸法が小さくなったため
、KrFエキシマレーザ−のように極めて短波長の光を
用いたりソグラフィ技術が注目されている。かかる短波
長光を用いた加工により、加工可能最小寸法を小さくで
き、微細化を実現し得るからである。On the other hand, as the minimum processing size has become smaller as described above, lithography techniques that use extremely short wavelength light such as KrF excimer laser are attracting attention. This is because processing using such short wavelength light allows the minimum processable dimension to be reduced and miniaturization to be achieved.
ところが、上記のような短波長光を用いて加工を行おう
とすると、反射防止膜が要せられ、反射防止膜を用いる
と、上述の選択成長技術の使用が困難になるという問題
が生じる。However, when processing is attempted using short wavelength light as described above, an antireflection film is required, and the use of an antireflection film poses a problem in that it becomes difficult to use the selective growth technique described above.
以下これについて述べる。This will be discussed below.
短波長光、例えばKrFエキシマレーザ−は、その波長
がDeepUV領域(250n m )にあるため、下
地基体の反射率が高い。よってたとえ酸化膜上であって
も、下地を通して反射光が戻って来るため、反射防止が
必要になる。しかも反射防止膜を酸化膜上に形成すると
、表面の材質が変わるため、従来より知られている手法
では選択成長を行わせることが困難になる。Short-wavelength light, such as KrF excimer laser, has a wavelength in the deep UV region (250 nm), so the reflectance of the underlying substrate is high. Therefore, even if it is on an oxide film, the reflected light will return through the underlying layer, so anti-reflection is required. Moreover, when an antireflection film is formed on an oxide film, the surface material changes, making it difficult to perform selective growth using conventionally known methods.
即ち、図3(A)に示すように、シリコン等の基体1上
にSiO□やその他の酸化膜から成る絶縁膜2が形成さ
れて成る材料について、KrFエキシマレーザ−にて微
細加工を行おうとすると、これについてはたとえシリコ
ン表面であっても、かつ絶縁膜を通しても、反射が問題
になり、微細な開口を精度良く形成することができなく
なるため、絶縁膜2上に反射防止膜5を形成する必要が
出て来る。次いでこれを上記レーザー光でフォトリソグ
ラフィ加工して微細な開口3を形成し図3(B)のよう
にする。ところがこの間口3を、選択成長技術を用いて
、Wなどを成長させて埋め込もうとすると、開口3のみ
ならず、反射防止膜5上にもWは多少成長し、選択性が
低下して良好な埋め込みができなくなり、かつ、反射防
止膜5上に形成された部分からWの剥れなどが生してし
まうおそれがある。例えば、洗浄時に剥れが生じたり、
あるいはダストとなったりし、更には埋め込み部4から
のWの脱落をもたらすおそれもある。That is, as shown in FIG. 3(A), an attempt was made to perform microfabrication using a KrF excimer laser on a material in which an insulating film 2 made of SiO□ or other oxide film is formed on a substrate 1 such as silicon. Then, reflection becomes a problem even on the silicon surface and even through the insulating film, making it impossible to form minute openings with high precision. Therefore, an anti-reflection film 5 is formed on the insulating film 2. The need arises. Next, this is photolithographically processed using the laser beam described above to form fine openings 3 as shown in FIG. 3(B). However, when attempting to fill this opening 3 by growing W or the like using a selective growth technique, some W grows not only on the opening 3 but also on the antireflection film 5, reducing the selectivity. Good embedding may not be possible, and W may peel off from the portion formed on the antireflection film 5. For example, peeling may occur during cleaning,
Alternatively, it may become dust, and there is also a possibility that W may fall off from the embedded portion 4.
図3 (C)中、符号41をもって、かかる反射防止膜
5上の選択成長材料の成長を示した。In FIG. 3(C), reference numeral 41 indicates the growth of the selectively grown material on the antireflection film 5. In FIG.
上述のように、極めて微細な加工が要せられることに伴
って、反射防止膜を用いざるを得ない場合が出て来るの
であり、このような場合には、選択成長技術をそのまま
適用することは困難なのである。As mentioned above, as extremely fine processing is required, there are cases where it is necessary to use an anti-reflection coating, and in such cases, selective growth technology cannot be applied as is. is difficult.
本発明はこの問題点を解決して、反射防止膜を形成する
場合についても、容易かつ良好に選択成長技術を適用で
きる半導体装置の製造方法を提供せんとするものである
。An object of the present invention is to solve this problem and provide a method for manufacturing a semiconductor device in which selective growth technology can be easily and favorably applied even when forming an antireflection film.
本発明に係る半導体装置の製造方法は、基体上に絶縁膜
を形成し、該絶縁膜上に反射防止膜を形成し、該反射防
止膜上に上層絶縁膜を形成し、前記絶縁膜、反射防止膜
、上層絶縁膜に開口を形成して少なくとも基体表面を露
出させ、該開口に選択成長材料を成長させることにより
該開口を埋め込むことを特徴とする半導体装置の製造方
法である。この構成によって、上述の問題点が解決され
る。A method for manufacturing a semiconductor device according to the present invention includes forming an insulating film on a substrate, forming an anti-reflection film on the insulating film, forming an upper insulating film on the anti-reflection film, and forming an insulating film on the anti-reflective film. This method of manufacturing a semiconductor device is characterized in that an opening is formed in a prevention film and an upper insulating film to expose at least the surface of the substrate, and the opening is filled by growing a selectively grown material in the opening. This configuration solves the above-mentioned problems.
本発明において絶縁膜とは、選択成長材料に応じて、そ
の成長が行われない材料膜を言い、例えばWについては
酸化膜等である。In the present invention, the insulating film refers to a material film that is not grown depending on the selectively grown material; for example, for W, it is an oxide film or the like.
反射防止膜とは、着目する光に対し反射防止機能を有す
るもので、材質、膜厚等により設定でき、また、下地に
応じ、窒化シリコン、TiN、、Ti0N、a (アモ
ルファス)−3iなどを材料として用いることができる
。An anti-reflection film has an anti-reflection function against the light of interest, and can be set depending on the material, film thickness, etc. Depending on the underlying material, it can be made of silicon nitride, TiN, Ti0N, a (amorphous)-3i, etc. It can be used as a material.
本発明によれば、反射防止膜の上に更に上層絶縁膜を形
成したので、ここには選択成長材料は形成されず、よっ
て開口内にのみ選択成長が行われて良好な埋め込みが達
成できる。According to the present invention, since the upper insulating film is further formed on the anti-reflection film, no selectively grown material is formed there, so that selective growth is performed only within the opening, and good embedding can be achieved.
以下発明の実施例について、図面を参照して説明する。 Embodiments of the invention will be described below with reference to the drawings.
但し当然のことではあるが、本発明は以下述べる実施例
により限定されるものではない。However, it goes without saying that the present invention is not limited to the examples described below.
この実施例は、本発明を、KrFエキシマレーザ−リソ
グラフィ技術を用いて反射防止条件で微小コンタクトホ
ールを開け、これを更に選択WCVDで埋め込めるよう
に層間絶縁膜を形成して、具体化したものである。This embodiment embodies the present invention by using KrF excimer laser lithography technology to open a minute contact hole under antireflection conditions, and then forming an interlayer insulating film so that it can be filled with selective WCVD. It is.
図1 (a)〜(e)を参照する。Refer to FIGS. 1(a) to (e).
本実施例では、基体1として5インチの半導体基板を用
い、この上にBPSG (ホウ素リン含有のシリケート
ガラス。250nmにおける屈折率1.5)を5000
人形成して、絶縁膜2とした。これにより図1(a)の
構造を得た。In this example, a 5-inch semiconductor substrate is used as the base 1, and BPSG (silicate glass containing boron phosphorus, refractive index 1.5 at 250 nm) is coated on this substrate with a film thickness of 5,000 nm.
The insulating film 2 was formed by forming a layer. As a result, the structure shown in FIG. 1(a) was obtained.
次に、上記絶縁膜2上に、窒化シリコン(Si:+I’
J4)を反射防止条件になる膜厚で低圧CVD法で形成
する。例えば150人厚人厚、250nmにおける屈折
率が1.5になるようにする。これにより反射防止膜5
を形成した図1(b)の構造を得る。Next, silicon nitride (Si:+I'
J4) is formed by low-pressure CVD to a film thickness that satisfies anti-reflection conditions. For example, the refractive index at a thickness of 150 nm and 250 nm is set to 1.5. As a result, the antireflection film 5
The structure shown in FIG. 1(b) is obtained.
次に、この上に更にSiO□をスパッタ法(あるいはC
VD法)で100人厚7形成し、これにより上層絶縁膜
6を有する図1(C)の構造とした。Next, SiO□ is further applied on top of this by sputtering method (or C
The structure of FIG. 1C having an upper layer insulating film 6 was obtained by forming a 100-layer film with a thickness of 7 using a VD method (VD method).
反射防止機能は、上記5i=N4からなる反射防止膜5
と、この上層絶縁膜6との双方が果たすことになるので
、両層5,6を合わせて所望の反射防止条件になるよう
にする。The anti-reflection function is provided by the anti-reflection film 5 consisting of the above 5i=N4.
Since both layers 5 and 6 serve this purpose, the desired antireflection conditions are achieved by combining both layers 5 and 6.
次にバターニングして、図1 (d)に示すように、絶
縁膜2、反射防止膜5、上層絶縁膜6に開口3を形成し
て、少なくとも基体1の表面を露出させる。本例では具
体的には、図1 (d)に示すように、開口3の底部全
体において基体1表面が露出するようにした。即ち、開
口3の底部は、Wが選択成長し得るシリコンが露出した
状態にした。Next, by patterning, as shown in FIG. 1(d), openings 3 are formed in the insulating film 2, antireflection film 5, and upper insulating film 6 to expose at least the surface of the base 1. Specifically, in this example, as shown in FIG. 1(d), the surface of the base 1 was exposed at the entire bottom of the opening 3. That is, the bottom of the opening 3 was exposed to silicon where W could selectively grow.
本実施例では、バターニングは次のように実施した。即
ち上面の上層絶縁膜6の表面を疎水化処理後、フォトレ
ジストとして5AL−601を0.7μml布した。こ
れをエキシマレーザ−ステッパ(N A : 0.37
)を用い、露先量801IIJ/c4でバターニング後
、100°Cで60秒PEB (露光後ベータ)し、上
記レジスト用の現像液であるMF622で10分間現像
し、0.4μmのコンタクトホール用レジストパターン
を形成した。これをヘキソード型エツチング装置でフッ
素系ガスでエツチングしく例えばCt F b 50S
CCM、300讐の条件)、開口3を形成して、コンタ
クトホールとし、レジストは剥離した。In this example, buttering was performed as follows. That is, after the surface of the upper insulating film 6 on the upper surface was subjected to hydrophobic treatment, 0.7 μml of 5AL-601 was applied as a photoresist. This was performed using an excimer laser stepper (NA: 0.37
), with an exposure amount of 801 IIJ/c4, PEB (beta after exposure) was performed at 100°C for 60 seconds, and development was performed for 10 minutes with MF622, a developer for the above resist, to form a 0.4 μm contact hole. A resist pattern was formed. This is etched using a fluorine-based gas using a hexode type etching device, such as Ct F b 50S.
CCM (conditions of 300 mm), an opening 3 was formed to serve as a contact hole, and the resist was peeled off.
次に、選択W−CV Dを行ったところ、開口3内にの
み良好に選択的にWが成長し、図1 (e)に示すよう
に、開口3に良好に選択成長材料(W)4が埋め込まれ
た構造が得られた。Next, when selective W-CVD was performed, W was selectively grown only in the opening 3, and as shown in FIG. A structure was obtained in which .
選択W−CVDは、本例では具体的には次のように行っ
た。In this example, selective W-CVD was specifically performed as follows.
使用ガス系:WFb/S i H4/H2−10/ 7
/1000 SCC?1
温度: 260”C
圧カニ 200mTorr
勿論、その他WF、にジシランやH2を加えて還元を行
わせるような、他のガス系を適宜用いてもよい。Gas system used: WFb/S i H4/H2-10/7
/1000 SCC? 1 Temperature: 260"C Pressure: 200 mTorr Of course, other gas systems may be used as appropriate, such as adding disilane or H2 to WF to perform reduction.
このように、本実施例においては、反射防止膜5を用い
ることによりKrFエキシマレーザ−リソグラフィ技術
を用いて微細な開口3を形成でき、かつ、このように反
射防止条件にしたのにも拘わらず、該開口3に選択的に
良好な選択成長材料4の埋め込みを達成できたものであ
る。As described above, in this embodiment, by using the antireflection film 5, the fine openings 3 can be formed using the KrF excimer laser lithography technique, and even though the antireflection conditions are set in this way, , it was possible to selectively fill the opening 3 with the selectively grown material 4.
一方、比較例として、上記した実施例−1と全く同じ条
件にして、但し上層絶縁膜6は形成することなく選択W
−CVDを行った。この結果、Wは反射防止膜6上を含
む全面に成長し、良好な選択成長はできなかった。On the other hand, as a comparative example, under exactly the same conditions as in Example-1 described above, the upper insulating film 6 was not formed, but W was selected.
- CVD was performed. As a result, W grew over the entire surface including the antireflection film 6, and good selective growth was not possible.
上記実施例では、絶縁膜2はBPSGから形成したが、
その他のPSG、As5Gなどの不純物含有ガラス等の
CVD膜でもよく、熱酸化膜でもよい。SiO□を含有
する酸化膜であると、本実施例と同じ条件で、良好に実
施できる。In the above embodiment, the insulating film 2 was formed from BPSG, but
It may be a CVD film made of other impurity-containing glass such as PSG or As5G, or it may be a thermal oxidation film. An oxide film containing SiO□ can be satisfactorily carried out under the same conditions as in this example.
反射防止膜は窒化シリコンとしたが、所望の反射防止機
能が得られるものであれば任意である。Although silicon nitride was used as the antireflection film, any material can be used as long as it provides the desired antireflection function.
また、上層絶縁膜6も、例えば熱酸化や、アニールで5
in2等を形成したものでもよい。Further, the upper insulating film 6 may also be formed by, for example, thermal oxidation or annealing.
In2 or the like may be formed.
短波長光を用いて加工を行う場合などについても、容易
かつ良好に選択成長技術を適用できるという効果がもた
らされるものである。Even when processing is performed using short wavelength light, the selective growth technique can be applied easily and favorably.
〔図1(a)〜(e)〕実施例−1の工程を順に断面図
で示すものである。
c図2(A)〜(C)〕従来の技術を示し、特′に選択
CVD技術の基体工程を示すものである。
〔図3(A)〜(C)]従来の技術を示し、特に問題点
を示す図である。
〔符号の説明〕
1・・・基体、2・・・絶縁膜、3・・・開口、4・・
・選択成長材料、5・・・反射防止膜、6・・・上層絶
縁膜。
〔発明の効果〕[FIGS. 1(a) to 1(e)] The steps of Example-1 are sequentially shown in cross-sectional views. 2(A) to 2(C)] This shows the conventional technology, and particularly shows the substrate process of the selective CVD technology. [FIGS. 3(A) to 3(C)] FIGS. 3(A) to 3(C) are diagrams showing a conventional technique and particularly showing problems. [Explanation of symbols] 1... Base, 2... Insulating film, 3... Opening, 4...
- Selective growth material, 5... antireflection film, 6... upper layer insulating film. 〔Effect of the invention〕
Claims (1)
少なくとも基体表面を露出させ、該開口に選択成長材料
を成長させることにより該開口を埋め込むことを特徴と
する半導体装置の製造方法。[Claims] 1. forming an insulating film on a substrate, forming an antireflection film on the insulating film, forming an upper insulating film on the antireflection film, the insulating film, the antireflection film, 1. A method of manufacturing a semiconductor device, comprising: forming an opening in an upper insulating film to expose at least the surface of the substrate; and filling the opening by growing a selectively grown material in the opening.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP25666990A JPH04133450A (en) | 1990-09-26 | 1990-09-26 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP25666990A JPH04133450A (en) | 1990-09-26 | 1990-09-26 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04133450A true JPH04133450A (en) | 1992-05-07 |
Family
ID=17295826
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP25666990A Pending JPH04133450A (en) | 1990-09-26 | 1990-09-26 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04133450A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0653331A (en) * | 1992-07-31 | 1994-02-25 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
US5643833A (en) * | 1993-08-31 | 1997-07-01 | Sony Corporation | Method of making a contact hole in a semiconductor device |
-
1990
- 1990-09-26 JP JP25666990A patent/JPH04133450A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0653331A (en) * | 1992-07-31 | 1994-02-25 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
US5643833A (en) * | 1993-08-31 | 1997-07-01 | Sony Corporation | Method of making a contact hole in a semiconductor device |
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