JPH04133393A - Manufacture of printed circuit board - Google Patents
Manufacture of printed circuit boardInfo
- Publication number
- JPH04133393A JPH04133393A JP25488990A JP25488990A JPH04133393A JP H04133393 A JPH04133393 A JP H04133393A JP 25488990 A JP25488990 A JP 25488990A JP 25488990 A JP25488990 A JP 25488990A JP H04133393 A JPH04133393 A JP H04133393A
- Authority
- JP
- Japan
- Prior art keywords
- printed wiring
- wiring board
- copper
- hole
- foil
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 238000005530 etching Methods 0.000 claims abstract description 20
- 239000011888 foil Substances 0.000 claims abstract description 14
- 229910052751 metal Inorganic materials 0.000 claims abstract description 12
- 239000002184 metal Substances 0.000 claims abstract description 12
- 239000012286 potassium permanganate Substances 0.000 claims abstract description 5
- 238000007747 plating Methods 0.000 claims description 32
- 238000000034 method Methods 0.000 claims description 22
- 238000005554 pickling Methods 0.000 claims description 7
- 229910000679 solder Inorganic materials 0.000 claims description 7
- 238000005553 drilling Methods 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 30
- 229910052802 copper Inorganic materials 0.000 abstract description 17
- 239000010949 copper Substances 0.000 abstract description 17
- 239000011889 copper foil Substances 0.000 abstract description 13
- 239000004593 Epoxy Substances 0.000 abstract description 4
- 239000007864 aqueous solution Substances 0.000 abstract description 3
- 239000002904 solvent Substances 0.000 abstract description 3
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 2
- 238000007598 dipping method Methods 0.000 abstract 1
- 230000002401 inhibitory effect Effects 0.000 abstract 1
- SECXISVLQFMRJM-UHFFFAOYSA-N N-Methylpyrrolidone Chemical compound CN1CCCC1=O SECXISVLQFMRJM-UHFFFAOYSA-N 0.000 description 4
- KAESVJOAVNADME-UHFFFAOYSA-N Pyrrole Chemical compound C=1C=CNC=1 KAESVJOAVNADME-UHFFFAOYSA-N 0.000 description 4
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- 238000011282 treatment Methods 0.000 description 4
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000004094 surface-active agent Substances 0.000 description 2
- 238000005406 washing Methods 0.000 description 2
- 101000927339 Pithecopus azureus Dermaseptin-H3 Proteins 0.000 description 1
- 241001122767 Theaceae Species 0.000 description 1
- 238000001994 activation Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910000365 copper sulfate Inorganic materials 0.000 description 1
- ARUVKPQLZAKDPS-UHFFFAOYSA-L copper(II) sulfate Chemical compound [Cu+2].[O-][S+2]([O-])([O-])[O-] ARUVKPQLZAKDPS-UHFFFAOYSA-L 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- JEIPFZHSYJVQDO-UHFFFAOYSA-N iron(III) oxide Inorganic materials O=[Fe]O[Fe]=O JEIPFZHSYJVQDO-UHFFFAOYSA-N 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000007800 oxidant agent Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 235000021110 pickles Nutrition 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000011550 stock solution Substances 0.000 description 1
- 235000011149 sulphuric acid Nutrition 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は表裏両面に配線パターンを設けるとともにこれ
ら配線パターン相互を表裏面間で接続するスルーホール
を有するプリント配線板（両面スルーホールプリント配
線板又は多層プリント配線板）の製造方法に関する。Detailed Description of the Invention [Field of Industrial Application] The present invention provides a printed wiring board (a double-sided through-hole printed wiring board) having wiring patterns on both the front and back sides and through-holes connecting these wiring patterns between the front and back sides. or a multilayer printed wiring board).
両面スルーホールプリント配線板の製造方法として、第
３図に示す如き工程からなる方法が従来おこなわれてい
た。As a method for manufacturing a double-sided through-hole printed wiring board, a method consisting of steps as shown in FIG. 3 has conventionally been carried out.
即ち、例えばガラス−エポキシ胴貼積層板の所定個所を
テープコントロール方式のドリルで穴明け（ドリリング
）し、ついで研磨、洗浄等を含む清浄活性化処理（デス
ミア処理）をおこなったのち、無電解銅メッキ及びパネ
ルメッキ（第１銅メッキ）をおこない、ついで水洗、酸
洗等の常套処理をおこなったのちレジストによるパター
ニングをおこない、次に、これをマスクとして電解銅メ
ッキによるパターンメッキ（第２銅メッキ）をおこない
、ついで電解半田メッキをしたのちレジストパターンを
剥離し、この半田メッキをエツチングレジストとしてレ
ジスト剥離により露出した銅箔をエツチング液を用いて
除去するという工程を経てプリント配線板かつくられて
いた。That is, for example, holes are drilled at predetermined locations on a glass-epoxy clad laminate using a tape-controlled drill, and then a cleaning activation process (desmear process) including polishing, cleaning, etc. is performed, and then electroless copper is used. Plating and panel plating (copper 1 plating) are performed, followed by conventional treatments such as washing with water and pickling, followed by patterning with resist, and then using this as a mask pattern plating with electrolytic copper plating (copper 2 plating). ), then electrolytic solder plating was applied, the resist pattern was peeled off, and the solder plating was used as an etching resist, and the copper foil exposed by the resist peeling was removed using an etching solution to make printed wiring boards. .
この場合、第１銅メッキではスルーホール内に１５１程
度、基板表裏面に２０ｔｍ程度の厚みの銅か基板上の銅
箔（例えば１８１の厚み）上に形成され、第２銅メッキ
においてはスルーホール内に１０１程度の電解銅メッキ
がなされ、これによりスルーホール内のメッキ厚として
２５ｔｅａ以上を得ている。しかし、このような２段階
の銅層・ツキ工程をとるため、不用となる（即ち、のち
に工・ノチングされる）銅箔上にもメッキが２０−付着
するため、合計３８坤の厚みの銅層を工・ソチングする
ことが必要となり、その分だけサイドエ・ソチングの大
きさも大きくなり、微細なパターンの形成上きわめて不
利となる。In this case, in the first copper plating, copper is formed in the through hole with a thickness of about 151 mm, on the front and back sides of the board with a thickness of about 20 tm, or on the copper foil (for example, 181 mm thick) on the board, and in the second copper plating, the through hole is formed Electrolytic copper plating of approximately 101 mm is applied inside the through hole, resulting in a plating thickness of 25 tea or more within the through hole. However, since such a two-step copper layer and plating process is used, plating is also deposited on the copper foil that will not be used (that is, to be etched and notched later), resulting in a total thickness of 38 cm. It is necessary to etching and soching the copper layer, and the size of the side etching and soching becomes correspondingly large, which is extremely disadvantageous in forming fine patterns.
さらに、メッキ工程は他の工程と比較して処理速度が遅
いため、できるだけメッキ工程数は少ないことが好まし
い。Furthermore, since the processing speed of the plating process is slow compared to other processes, it is preferable that the number of plating processes be as small as possible.
本発明はより微細な配線パターンの形成が可能で、かつ
生産能率の向上を図ることができるプリント配線板の製
造方法を提供することを目的とする。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a printed wiring board that allows formation of finer wiring patterns and improves production efficiency.
本発明はプリント配線基板のスルーホール内壁面の導電
性付与を従来の如き無電解メ・ツキによらず、Ｎ−メチ
ル−２−ピロリジノンとビロールとの混合液を用いるこ
とによりおこない、最終的に不用となる配線基板上の金
属箔上には銅メッキ層を全く形成させないという手段を
講じ、上記課題の解決を図った。The present invention imparts conductivity to the inner wall surface of a through hole in a printed wiring board by using a mixed solution of N-methyl-2-pyrrolidinone and virol instead of using conventional electroless metal plating. We have attempted to solve the above problem by not forming any copper plating layer on the metal foil on the wiring board that is no longer needed.
すなわち、本発明は、
（ａ）絶縁基板の表裏両面に金属箔を被着してなるプリ
ント配線基板の所定個所をドリリングしてスルーホール
を形成する工程と；
（ｂ）過マンガン酸カリで該プリント配線基板を処理す
る工程と；
（ｃ）プリント配線パターンを形成するためのレジスト
パターンを形成する工程と：
（ｄ）ついで、ＤＭＳ−ｎ浴中に浸漬処理して上記スル
ーホール内壁面に導電性を付与する工程と；（ｃ）上記
（ｄ）工程で処理されたプリント配線基板を酸洗する工
程と；
（ｆ）この酸洗されたプリント配線基板を電解銅メッキ
する工程と；
（ｇ）上記レジストパターンを剥離除去する工程と；
（ｈ）上記レジストパターンの剥離によって露出した上
記金属箔をエツチング除去する工程と；を具備してなる
ことを特徴とするプリント配線板の製造方法を提供する
ものである。That is, the present invention includes the following steps: (a) Drilling a predetermined portion of a printed wiring board formed by covering both the front and back surfaces of an insulating substrate with metal foil to form a through hole; (b) Drilling a through hole with potassium permanganate; (c) forming a resist pattern for forming a printed wiring pattern; (d) then immersing the printed wiring board in a DMS-n bath to make the inner wall surface of the through hole conductive. (c) A step of pickling the printed wiring board treated in step (d) above; (f) A step of electrolytically plating the pickled printed wiring board; (g ) Peeling and removing the resist pattern; (h) etching and removing the metal foil exposed by peeling off the resist pattern; It is something to do.
なお、上記（ｆ）工程と（ｇ）工程との間に電解はんだ
メッキ工程を介在させるようにしてもよい。Note that an electrolytic solder plating step may be interposed between the above steps (f) and (g).
このはんだメッキ層は金属箔が銅箔の場合等において後
の金属箔エツチング工程（ｈ）の際のエツチングレジス
トとしての役割及び部品実装時のソルダリング処理を容
易にする役割をもっている。This solder plating layer has the role of an etching resist during the subsequent metal foil etching step (h) when the metal foil is copper foil, and the role of facilitating the soldering process during component mounting.
さらに、ソフトエツチング工程を上記（ｃ）工程と（ｄ
）工程との間、又は上記（ａ）工程と（ｂ）工程との間
に介在させてもよい。このソフトエツチングは金属箔表
面を粗面化し、めっきの密着性を良くするためのもので
ある。Furthermore, the soft etching process is performed in the above (c) process and (d).
) or between the above steps (a) and (b). This soft etching is intended to roughen the surface of the metal foil and improve plating adhesion.
さらに上記（ｂ）工程と（ｃ）工程との間に酸洗工程を
介在させてもよい。この場合の酸洗は表面錆を取り除き
レジストパターンの密着を向上させるものである。Furthermore, a pickling step may be interposed between the above steps (b) and (c). The pickling in this case removes surface rust and improves the adhesion of the resist pattern.
上記Ｄ Ｍ Ｓ −ＩＩ浴とはＮ−メチル−２−ピロリ
ジノンとビロールとの混合物（ピロールの含量＝１〜５
０モル％）である。The above D M S -II bath is a mixture of N-methyl-2-pyrrolidinone and pyrrole (pyrrole content = 1 to 5
0 mol%).
本発明においては、基板のドリリング工程ののち、レジ
ストパターンを基板表裏面の金属箔上に直接被着し、ス
ルーホール内壁面の導電性付与をＤＭＳ−ＩＩ浴でおこ
ない、その後、電解銅メッキによりスルーホール内に所
望厚さの導電層を得るようにしたから、サイドエツチン
グが可及的に小さくなり、より微細な配線パターンが可
能となり、又、メッキ工程が一回で済むため、生産能率
の向上が図れる。In the present invention, after the substrate drilling process, a resist pattern is directly deposited on the metal foil on the front and back surfaces of the substrate, and the inner wall surface of the through hole is made conductive using a DMS-II bath, and then electrolytic copper plating is performed. By obtaining a conductive layer of the desired thickness within the through-hole, side etching is minimized, allowing for finer wiring patterns, and since only one plating process is required, production efficiency is improved. Improvements can be made.
実施例１
第１図に示す如き工程によりプリント配線板を製造した
。これを第２図を参照して説明する。Example 1 A printed wiring board was manufactured by the steps shown in FIG. This will be explained with reference to FIG.
まず、表裏両面に銅箔２を貼着したガラス−エポキシ胴
貼積層板１ （３４０龍Ｘ５１Ｃ１＋ｍＸ１．６＋ｍ）
の所望位置を直径０．５ｗのドリルで穴明加工した（第
２図（ａ）参照）。ついて表面研磨によりパリを除去し
、さらに高圧洗浄等によるデスミア処理をおこなったの
ち、コンディショナーとして、ＮａＯＨ２重量％、ブラ
ソリ・ソト（Ｂｌａｓｏｌｉｔ） Ｍ Ｓ ＨＰａｒｔ
ＩＩ ３容量％（界面活性剤、ブラスバーグ社、西独
製）及びブラソリットＭ Ｓ ＨＰａｒｔＩＩ［（界面
活性剤、ブラスバーグ社、西独製）１０容量％を用いて
建浴し、６０℃、５分間処理した。First, glass-epoxy body laminated board 1 with copper foil 2 pasted on both front and back sides (340 Dragon
A hole was drilled at the desired position using a drill with a diameter of 0.5W (see Fig. 2(a)). Then, after removing pars by surface polishing and desmearing by high pressure washing etc., as a conditioner, NaOH 2% by weight, Blasolit M S HP Part
A bath was prepared using 3% by volume of Brasolit II (surfactant, manufactured by Blasberg, West Germany) and 10% by volume of Brasolit M S HP Part II (surfactant, manufactured by Blasberg, West Germany), and treated at 60°C for 5 minutes. did.
さらに、Ｋ Ｍ ｎ Ｏ４１５ｇ ／ ＩＩ及びＮａＯ
Ｈ１５ｇ／ｉｔからなる溶液を用いて過マンガン酸カリ
処理を９０℃にて５分間おこなった。次に、溶剤現像タ
イプのフォトレジストを用いて厚み４０−のレジストパ
ターン３を銅箔上に形成した（第２図す参照）。その後
、ＤＭＳ３（酸化剤、ブラスバーグ社製）１０重量％、
ａ硫酸１容量％からなるエツチング液を用いて３０℃に
て２分間ソフトエツチングした。ついで、ＤＭＳ−ＩＩ
原液を３倍に希釈した水溶液中に室温にて２分間浸漬し
、つづいて酸洗（濃硫酸５容量％）を２分間おこない、
スルーホール内壁に導電層４を形成させた（第２図（ｃ
）参照）。Furthermore, K M n O415g/II and NaO
Potassium permanganate treatment was performed at 90° C. for 5 minutes using a solution containing 15 g/it of H. Next, a resist pattern 3 having a thickness of 40 mm was formed on the copper foil using a solvent development type photoresist (see FIG. 2). After that, 10% by weight of DMS3 (oxidizing agent, manufactured by Blasberg),
Soft etching was performed at 30° C. for 2 minutes using an etching solution containing 1% by volume of sulfuric acid. Next, DMS-II
Immerse the stock solution in an aqueous solution 3 times diluted at room temperature for 2 minutes, then pickle (concentrated sulfuric acid 5% by volume) for 2 minutes,
A conductive layer 4 was formed on the inner wall of the through hole (Fig. 2(c)
)reference).
次に、硫酸銅メッキ浴として、Ｃｕ５Ｏ４ＳＨ２０８０
ｇ／ｆ！、Ｈ２Ｓ０４ １８０ｇ／ｌ、及び光沢剤（
ＬＰ６１６．ＬＰＡ、西独ＬＰＷ社製）からなる浴を用
い、銅メッキをおこなった。その結果、２Ａ／ｄｍ２Ｘ
９０分にてスルーホール内壁に３０ ｔｒｍ、銅箔表面
に４０．ｘの厚みの銅メッキ皮膜５を形成した。ついで
、その表面に１０ｕｍの厚みのはんだメッキ層６を形成
した（第２図（ｄ）参照）。Next, as a copper sulfate plating bath, Cu5O4SH2080
g/f! , H2S04 180g/l, and brightener (
LP616. Copper plating was performed using a bath consisting of LPA (manufactured by LPW, West Germany). As a result, 2A/dm2X
30 trm on the inner wall of the through hole and 40 trm on the copper foil surface in 90 minutes. A copper plating film 5 having a thickness of x was formed. Then, a solder plating layer 6 with a thickness of 10 um was formed on the surface (see FIG. 2(d)).
次に、溶剤を用いてレジストパターン３を除去しく第２
図（ｅ）、つづいてアルカリ系エツチング溶液を用いて
露出した銅箔２を除去した（第２図（ｆ））。Next, the resist pattern 3 is removed using a solvent.
2(e), and then the exposed copper foil 2 was removed using an alkaline etching solution (FIG. 2(f)).
このようにして得たプリント配線板は銅箔２の厚さたけ
エツチングすれば良いため、サイドエツチング量が少な
く、１８−の厚さの銅箔を用いた場合、１００−幅間隔
のレジストパターンに対し、ライン幅６０庫の配線パタ
ーンを得ることができた。Since the printed wiring board obtained in this way only needs to be etched to the thickness of the copper foil 2, the amount of side etching is small. On the other hand, a wiring pattern with a line width of 60 could be obtained.
実施例２
上記実施例１において、ソフトエツチング工程（第１図
（ｃ’ ） ）をレジストバターニングの後でなく、コ
ンディショナーによる処理の前におこなった以外は実施
例１と同様に処理した結果、実施例１と同様の結果が得
られた。Example 2 The same process as in Example 1 was performed except that the soft etching step (FIG. 1(c')) was performed not after resist buttering but before the conditioner treatment, resulting in the following results: Similar results as in Example 1 were obtained.
実施例３
上記実施例２において、過マンガン酸カリ処理工程のの
ち、５容量％Ｈ２ＳＯ４水溶液を用いて酸洗をおこなっ
た以外は実施例２と同様の処理を施してプリント配線板
を製造した。その結果、実施例１と同様の結果が得られ
た。Example 3 A printed wiring board was manufactured in the same manner as in Example 2, except that after the potassium permanganate treatment step, pickling was performed using a 5% by volume H2SO4 aqueous solution. As a result, the same results as in Example 1 were obtained.
以上説明したように、本発明によればＤ Ｍ Ｓ−■浴
への浸漬工程によりスルーホール内壁面に導電性を付与
するようにしたから、１回の銅メッキ工程でスルーホー
ル内に導電層を形成することが可能となり、プリント配
線板の生産能率を著しく向上させることができ、さらに
レジストパターンの形成を絶縁基板表裏の銅箔表面に直
接施すようにしたため、後のエツチング工程では不用な
銅箔のみを除去すればよく、そのためサイドエツチング
量を可及的に少なくすることができ、従来法と較べ、よ
り微細な配線パターンの形成が可能となった。As explained above, according to the present invention, conductivity is imparted to the inner wall surface of the through hole by the immersion process in the DMS-■ bath. This makes it possible to significantly improve the production efficiency of printed wiring boards.Furthermore, since the resist pattern is formed directly on the copper foil surface on the front and back of the insulating substrate, unnecessary copper is removed in the subsequent etching process. Only the foil needs to be removed, so the amount of side etching can be reduced as much as possible, making it possible to form finer wiring patterns compared to conventional methods.
なお、本発明は上記実施例の如き両面スルーホールプリ
ント配線板のほか多層プリント配線板の製造にも適用し
得る。The present invention can be applied to the production of multilayer printed wiring boards in addition to double-sided through-hole printed wiring boards as in the above embodiments.
第１図は本発明に係わるプリント配線板の製造方法を工
程順に示すブロック図、第２図は同じく本発明に係わる
プリント配線板の製造方法を工程順に示す要部断面図、
第３図は従来のプリント配線板の製造方法を工程順に示
すブロックズ図である。
］１８．ガラス−エポキシ胴貼積層板、２・・銅箔、３
・・・レジストパターン、４・・・導電層、５・・・銅
メッキ皮膜、６・・・はんだメッキ層。
出願人代理人 弁理士 鈴 江 武 彦第２図
第１図FIG. 1 is a block diagram showing a method for manufacturing a printed wiring board according to the present invention in the order of steps; FIG.
FIG. 3 is a block diagram showing the conventional method for manufacturing a printed wiring board in order of steps. ]18. Glass-epoxy shell laminate, 2...Copper foil, 3
...Resist pattern, 4...Conductive layer, 5...Copper plating film, 6...Solder plating layer. Applicant's agent Patent attorney Takehiko Suzue Figure 2 Figure 1
Claims (5)
ント配線基板の所定個所をドリリングしてスルーホール
を形成する工程と； （ｂ）過マンガン酸カリで該プリント配線基板を処理す
る工程と； （ｃ）プリント配線パターンを形成するためのレジスト
パターンを形成する工程と； （ｄ）ついで、ＤＭＳ−II浴中に浸漬処理して上記スル
ーホール内壁面に導電性を付与する工程と； （ｅ）上記（ｄ）工程で処理されたプリント配線基板を
酸洗する工程と； （ｆ）この酸洗されたプリント配線基板を電解銅メッキ
する工程と； （ｇ）上記レジストパターンを剥離除去する工程と； （ｈ）上記レジストパターンの剥離によって露出した上
記金属箔をエッチング除去する工程と；を具備してなる
ことを特徴とするプリント配線板の製造方法。(1) (a) Drilling a predetermined portion of a printed wiring board formed by covering both the front and back sides of an insulating substrate with metal foil to form a through hole; (b) Drilling the printed wiring board with potassium permanganate; (c) forming a resist pattern for forming a printed wiring pattern; (d) then immersing in a DMS-II bath to impart conductivity to the inner wall surface of the through hole; (e) A step of pickling the printed wiring board treated in step (d) above; (f) A step of electrolytically plating the pickled printed wiring board; (g) A step of applying the above resist. A method for manufacturing a printed wiring board, comprising: (h) removing the metal foil exposed by peeling off the resist pattern; and (h) removing the metal foil exposed by peeling off the resist pattern.
工程を介在させたことを特徴とする請求項１記載のプリ
ント配線板の製造方法。(2) The method for manufacturing a printed wiring board according to claim 1, characterized in that an electrolytic solder plating step is interposed between the steps (f) and (g).
工程との間に介在させたことを特徴とする請求項１記載
のプリント配線板の製造方法。(3) Soft etching process described above (c) and (d)
2. The method of manufacturing a printed wiring board according to claim 1, wherein the printed wiring board is interposed between the step and the step.
工程との間に介在させたことを特徴とする請求項１記載
のプリント配線板の製造方法。(4) Soft etching process described above (a) and (b)
2. The method of manufacturing a printed wiring board according to claim 1, wherein the printed wiring board is interposed between the step and the step.
介在させたことを特徴とする請求項１記載のプリント配
線板の製造方法。(5) The method for manufacturing a printed wiring board according to claim 1, characterized in that a pickling step is interposed between the steps (b) and (c).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25488990A JPH04133393A (en) | 1990-09-25 | 1990-09-25 | Manufacture of printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25488990A JPH04133393A (en) | 1990-09-25 | 1990-09-25 | Manufacture of printed circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04133393A true JPH04133393A (en) | 1992-05-07 |
Family
ID=17271249
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25488990A Pending JPH04133393A (en) | 1990-09-25 | 1990-09-25 | Manufacture of printed circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04133393A (en) |
-
1990
- 1990-09-25 JP JP25488990A patent/JPH04133393A/en active Pending
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