JPH04133346A - Hybrid integrated circuit and manufacture thereof - Google Patents
Hybrid integrated circuit and manufacture thereofInfo
- Publication number
- JPH04133346A JPH04133346A JP25570790A JP25570790A JPH04133346A JP H04133346 A JPH04133346 A JP H04133346A JP 25570790 A JP25570790 A JP 25570790A JP 25570790 A JP25570790 A JP 25570790A JP H04133346 A JPH04133346 A JP H04133346A
- Authority
- JP
- Japan
- Prior art keywords
- conductive
- integrated circuit
- conductive foil
- insulating film
- hybrid integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 239000011888 foil Substances 0.000 claims abstract description 51
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000005476 soldering Methods 0.000 claims abstract description 13
- 238000010396 two-hybrid screening Methods 0.000 claims abstract description 6
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 claims description 23
- 229910052742 iron Inorganic materials 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 5
- 229910000679 solder Inorganic materials 0.000 abstract description 7
- 235000000396 iron Nutrition 0.000 abstract 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 239000011889 copper foil Substances 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/281—Applying non-metallic protective coatings by means of a preformed insulating foil
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/36—Assembling printed circuits with other printed circuits
- H05K3/361—Assembling flexible printed circuits with other printed circuits
- H05K3/363—Assembling flexible printed circuits with other printed circuits by soldering
Landscapes
- Combinations Of Printed Boards (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明は二枚の混成集積回路基板間を電気的に接続する
インナーリードを具備する混成集積回路およびその製造
方法に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a hybrid integrated circuit having an inner lead for electrically connecting two hybrid integrated circuit boards, and a method for manufacturing the same.
（ロ）従来の技術
混成集積回路では高密度実装を実現するために多層導電
路構造や複数基板構造が提案されている。第３図に示す
構造は複数基板構造に関するものである。（１）（２）
は混成集積回路基板であり、所望の導電路上に回路素子
を付着して所望の回路を形成している。（３）は外部リ
ードであり、外付回路との電気的接続を行う。（４）は
混成集積回路基板（１）（２）間の内部接続を行うイン
ナーリードである。斯る複数基板構造では、インナーリ
ード（４）部分で矢印のように折り曲げることにより高
密度実装を実現している。(b) In conventional technology hybrid integrated circuits, multilayer conductive path structures and multi-board structures have been proposed in order to realize high-density packaging. The structure shown in FIG. 3 relates to a multiple substrate structure. (1) (2)
is a hybrid integrated circuit board on which circuit elements are attached on desired conductive surfaces to form desired circuits. (3) is an external lead, which is electrically connected to an external circuit. (4) is an inner lead that makes an internal connection between the hybrid integrated circuit boards (1) and (2). In such a multi-board structure, high-density mounting is realized by bending the inner leads (4) in the direction of the arrow.
従来のインナーリードを第４図および第５図を参照して
説明する。第４図に示すインナーリード（４＞は、二枚
のフレキシブル絶縁フィルム（５）（６）間に１ｍｍ間
隔で４０本ぐらいの銅箔なとの導電箔（７）を配列し、
絶縁フィルム（５）（６）は同形状に形成されて絶縁フ
ィルム（５）（６）からは導電箔（７）が３ｍｍ幅で両
端に露出されている。A conventional inner lead will be explained with reference to FIGS. 4 and 5. The inner lead (4) shown in Fig. 4 is made by arranging about 40 conductive foils (7) such as copper foil at 1 mm intervals between two flexible insulating films (5) and (6).
The insulating films (5) and (6) are formed in the same shape, and conductive foils (7) with a width of 3 mm are exposed at both ends of the insulating films (5) and (6).
しかしながらこのインナーリード（４）では導電箔（７
）が１ｍｍ幅で３５μ厚で薄いため、極めて変形し易く
、変形を防止するための取り扱いが難しかった。However, this inner lead (4) has a conductive foil (7).
) is thin with a width of 1 mm and a thickness of 35 μm, so it is extremely easily deformed and difficult to handle to prevent deformation.
そこで第５図に示すインナーリード（４）が考えられた
。ＰＣＢフレキシブル基板（８）上に導電箔（７）全部
を貼り付け、オーバーフィルムク９）でその先端を３ｍ
ｍ幅で露出されるインナーリード（４）である。このイ
ンナーリード（４）では導電箔（７）がすべてＰＣＢフ
レキシブル基板（８）で支持されているので、変形のお
それは全くなくなる。Therefore, an inner lead (4) shown in FIG. 5 was devised. Paste all of the conductive foil (7) on the PCB flexible board (8), and use an overfilm tape (9) to cover the tip by 3 m.
This is an inner lead (4) exposed with a width of m. Since the conductive foil (7) in this inner lead (4) is entirely supported by the PCB flexible board (8), there is no possibility of deformation.
斯る第５図のインナーリード（４）を利用する場合の混
成集積回路の製造方法を第６図を参照して詳述する。二
枚の混成集積回路基板（１）（２）の対向する辺に設け
た導電路から延長された電極（１０）を形成する。イン
ナーリード（４）のＰＣＢフレキシブル基板（８）を上
面にしてオーバーフィルム（９）より露出した導電箔（
７）を電極（１０）と当接して配置し、ＰＣＢフレキシ
ブル基板（８）上に半田ごて（１１）を圧着してインナ
ーリード（４）の導電箔（７）と電極（１０）とを半田
付けする。A method for manufacturing a hybrid integrated circuit using the inner lead (4) shown in FIG. 5 will be described in detail with reference to FIG. 6. Electrodes (10) are formed extending from conductive paths provided on opposite sides of two hybrid integrated circuit boards (1) and (2). The conductive foil (
7) in contact with the electrode (10), and press the soldering iron (11) onto the PCB flexible board (8) to connect the conductive foil (7) of the inner lead (4) and the electrode (10). Solder.
（ハ）発明が解決しようとする課題
しかしながら第５図に示すインナーリード（４）を有す
る混成集積回路では半田の加熱をＰＣＢフレキシブル基
板（８）を介して行っているので、第７図に示す如く半
田ごて（１１）は直ちに１８０°Ｃ以上に上昇するがＰ
ＣＢフレキシブル基板（８）上の導電箔（７）は約１分
間以上加熱をしないと１８０℃以上に上昇せず半田付け
を行うことができない問題点を有している。またこのた
めに混成集積回路の製造方法も極めて非効率なものとな
る問題点を有している。(c) Problems to be Solved by the Invention However, in the hybrid integrated circuit having the inner leads (4) shown in FIG. 5, the solder is heated via the PCB flexible board (8), so as shown in FIG. The soldering iron (11) immediately rises to over 180°C, but P
The conductive foil (7) on the CB flexible substrate (8) has the problem that the temperature does not rise to 180° C. or higher and cannot be soldered unless heated for about 1 minute or more. This also poses a problem in that the method for manufacturing hybrid integrated circuits is extremely inefficient.
（ニ）課題を解決するための手段
本発明は斯る問題点に鑑みてなぎれ、二枚の絶縁フィル
ム間に離間して配列した導電箔の絶縁フィルムからの露
出幅を基板の電極に当接する側を大きくしたインナーリ
ードを用いることにより、従来の問題点を解決した混成
集積回路およびその製造方法を提供するものである。(d) Means for Solving the Problems The present invention was developed in view of the above problems, and it is possible to apply the exposed width from the insulating film of the conductive foil arranged at a distance between two insulating films to the electrodes of the substrate. The present invention provides a hybrid integrated circuit and a method for manufacturing the same which solves the conventional problems by using inner leads with larger contact sides.
（ネ）作用
本発明に依れば、インナーリードの基板に当接する側の
絶縁フィルムの切欠部から導電箔を露出させているので
、導電箔の変形を防止できる。また半田ごては直接導電
箔に接触できるので、インナーリードの半田付けを極め
て効率よく行える。(f) Function According to the present invention, since the conductive foil is exposed from the notch of the insulating film on the side of the inner lead that contacts the substrate, deformation of the conductive foil can be prevented. Furthermore, since the soldering iron can directly contact the conductive foil, the inner leads can be soldered extremely efficiently.
（へ）実施例
第１図Ａ、Ｂ、Ｃおよび第２図を参照して本発明の一実
施例を詳述する。本発明に用いるインナーリード（４）
を第１図Ａ、Ｂ、Ｃを参照して説明する。このインナー
リード（４）はポリイミド等の二枚のフレキシブル絶縁
フィルム（２１）（２２）と、このフィルム間（２１）
（２２）にはさまれて離間して配列した銅箔などの導電
箔（７）で構成されている。(F) Embodiment An embodiment of the present invention will be described in detail with reference to FIGS. 1A, B, and C and FIG. 2. Inner lead used in the present invention (4)
will be explained with reference to FIGS. 1A, B, and C. This inner lead (4) is connected to two flexible insulating films (21) (22) made of polyimide, etc., and between these films (21)
(22) and is composed of conductive foils (7) such as copper foil arranged spaced apart from each other.
絶縁フィルム（２１＞（２２）は導′を箔（７）を被覆
する形状を異になる様に形成している。第１図Ａ、Ｅ。The insulating films (21>(22) are formed in different shapes to cover the conductor's foil (7). FIGS. 1A and E.
Ｃより明らかな様に、上面の絶縁フィルム（２１）は導
電箔（７）の先端部分を例えば３ ｍｔｎｉ出する様に
導電箔（７〉を被覆している。下面の絶縁フィルム（２
２）は各導電箔（７）の両端で一部を重畳し、基板の電
極（１０）と対向する部分に善導を箔（７）毎にＵ字状
の切欠部（２３）を設けて導電箔（７）を露出している
。従って第１図Ｃから明らかな様に各導電箔（７）はそ
の周辺で下面の絶縁フィルム（２２）で支持きれている
。As is clear from C, the insulating film (21) on the upper surface covers the conductive foil (7) so that the tip of the conductive foil (7) extends, for example, by 3 mtni.
2) overlaps a portion of each conductive foil (7) at both ends, and places a good conductor on the part facing the electrode (10) of the board by providing a U-shaped notch (23) in each foil (7) to make it conductive. The foil (7) is exposed. Therefore, as is clear from FIG. 1C, each conductive foil (7) is fully supported around it by the insulating film (22) on the lower surface.
斯る構造に依れば、インナーリード（４）の各導電箔（
７）は下面の絶縁フィルム（２２）でその先端まで支持
きれており、従来のものに比べて導電箔（７）の変形を
防止できる。According to such a structure, each conductive foil (
7) is fully supported up to its tip by the insulating film (22) on the lower surface, and can prevent deformation of the conductive foil (7) compared to conventional ones.
次にこのインナーリード（４）を用いた混成集積回路の
製造方法について説明する。Next, a method of manufacturing a hybrid integrated circuit using this inner lead (4) will be explained.
先ず第３図に示す如く、二枚の混成集積回路基板（１）
（２）を準備する。混成集積回路基板（１）（２）は同
一サイズで、セラミックスあるいはアルミニウム等の表
面を絶縁化した金属基板等を用い、その−面には、銅ペ
ーストのスクリーン印刷あるいは銅箔のエツチングによ
り形成した導電路を形成する。二枚の基板（１）（２，
）の対向する辺には導電路の一部として複数の電極（１
０）を対応して形成されている。First, as shown in Figure 3, two hybrid integrated circuit boards (1)
Prepare (2). The hybrid integrated circuit boards (1) and (2) are of the same size and are made of a metal substrate made of ceramic or aluminum with an insulated surface, and the lower side is formed by screen printing with copper paste or etching with copper foil. Forms a conductive path. Two boards (1) (2,
) have a plurality of electrodes (1
0).
次に第１図および第２図に示す如く、前述したインナー
リード（４）を準備し、二枚の基板（１）（２）の電極
（１０）間の接続を行う。インナーリード（４）の絶縁
フィルム（２１）（２２）から露出された導電箔（７）
は予め半田メツキしておき、基板（１）（２）の電極（
１０）上にも半田デイツプをしておく。続いてインナー
リード（４）の切欠部（２３）から露出した導電箔（７
）を電極（１０）と当接させ、上面より露出した導電箔
（７）に半田ごて（１１）を当接させて半田付けて行う
。この結果、半田ごて（１１）の熱は導電箔（７）を介
して直ちに電極（１０）に伝達され、すぐに半田を溶か
すことができるので、極めて効率良くインナーリード（
４）で基板（１）（２）間の電極（１０）の電気的接続
を行える。Next, as shown in FIGS. 1 and 2, the aforementioned inner leads (4) are prepared and connections are made between the electrodes (10) of the two substrates (1) and (2). Conductive foil (7) exposed from the insulation film (21) (22) of the inner lead (4)
are soldered in advance, and the electrodes (
10) Apply solder dip on top as well. Next, remove the conductive foil (7) exposed from the cutout (23) of the inner lead (4).
) is brought into contact with the electrode (10), and the soldering iron (11) is brought into contact with the conductive foil (7) exposed from the top surface to perform soldering. As a result, the heat of the soldering iron (11) is immediately transferred to the electrode (10) via the conductive foil (7), and the solder can be melted immediately, so the inner lead (
In step 4), the electrode (10) between the substrates (1) and (2) can be electrically connected.
（ト）発明の効果
本発明に依れば、導電箔（７）の先端まで下面の絶縁フ
ィルム（２２）で被覆でき、その先端の変形をＩＦ７止
できる。従ってインナーリード（４）の導電箔（７）の
間隔を大幅に狭くでき、多数本の導電箔（７）をインナ
ーリード（４）に形成できる利点を有する。(g) Effects of the Invention According to the present invention, the tip of the conductive foil (7) can be covered with the insulating film (22) on the lower surface, and deformation of the tip can be prevented by IF7. Therefore, there is an advantage that the interval between the conductive foils (7) of the inner lead (4) can be significantly narrowed, and a large number of conductive foils (7) can be formed on the inner lead (4).
また本発明では、半田ごて（１１）を直接インナーリー
ド（４）の導電箔（７）に当接できるので、インナーリ
ード〈４）の電極（１０）への半田付けも極めて効率良
く行え、更に下面の絶縁フィルム（２２）の切欠部（２
３）は各導電箔（７）毎に分離する働きを有し隣接する
電極（１０）間の半田ショートを防止できる利点を有す
る。Further, in the present invention, since the soldering iron (11) can be brought into direct contact with the conductive foil (7) of the inner lead (4), soldering to the electrode (10) of the inner lead (4) can be performed extremely efficiently. Furthermore, the notch (2) of the insulating film (22) on the lower surface
3) has the advantage of having the function of separating each conductive foil (7) and preventing solder shorts between adjacent electrodes (10).
第１図Ａ、Ｂ、Ｃは本発明に用いるインナーノードの上
面図、断面図および斜視図、第２図は本発明の製造方法
を説明する断面図、第３図は混成集積回路の複数基板構
造を説明する上面図、第４図Ａ、Ｂおよび第５図Ａ、Ｂ
は従来のインナーノードの上面図および断面図、第６図
は従来の製造方法を説明する断面図、第７図は従来の製
造方法における半田ごて加熱温度を説明する特性図であ
る。
（１）（２）は混成集積回路基板、（４）はインナーリ
ード、＜２１ ）（２２）は絶縁フィルム、（７）は導
電箔、（１０）は電極、（１１）は半田ごて、（２３）
は切欠部である。
第１図Ａ1A, B, and C are top views, cross-sectional views, and perspective views of the inner node used in the present invention; FIG. 2 is a cross-sectional view illustrating the manufacturing method of the present invention; and FIG. 3 is a plurality of substrates of a hybrid integrated circuit. Top view explaining the structure, Fig. 4 A, B and Fig. 5 A, B
6 is a top view and a sectional view of a conventional inner node, FIG. 6 is a sectional view illustrating the conventional manufacturing method, and FIG. 7 is a characteristic diagram illustrating the soldering iron heating temperature in the conventional manufacturing method. (1) (2) is a hybrid integrated circuit board, (4) is an inner lead, <21) (22) is an insulating film, (7) is a conductive foil, (10) is an electrode, (11) is a soldering iron, (23)
is the notch. Figure 1A
Claims (2)
を接続するインナーリードとを備え、前記インナーリー
ドを二枚の絶縁フィルム間に離間して配列された導電箔
で形成し、前記基板上の電極に当接する側の絶縁フィル
ムに各電極毎に切欠部を設け、反対側の絶縁フィルムは
前記切欠部上の導電箔を露出することを特徴とする混成
集積回路。(1) comprising two hybrid integrated circuit boards and inner leads connecting the conductive paths of the boards, the inner leads being formed of conductive foils spaced apart and arranged between two insulating films; A hybrid integrated circuit characterized in that a notch is provided for each electrode in the insulating film on the side that contacts the electrodes on the substrate, and the insulating film on the opposite side exposes the conductive foil on the notch.
されたインナーリードを準備し、各導電箔毎に設けた前
記絶縁フィルムの切欠部より露出する導電箔表面を前記
基板の電極と当接させ、反対側の絶縁フィルムより露出
された導電箔面に半田ごてを当接させて前記インナーリ
ードと前記基板の電極の接続を行う工程とを具備するこ
とを特徴とする混成集積回路の製造方法。(2) A step of preparing two hybrid integrated circuit boards, preparing inner leads formed of conductive foils arranged at a distance between two insulating films, and providing the insulating film for each conductive foil. Connect the inner lead and the electrode of the substrate by bringing the surface of the conductive foil exposed through the notch into contact with the electrode of the substrate, and by bringing a soldering iron into contact with the surface of the conductive foil exposed from the insulating film on the opposite side. A method for manufacturing a hybrid integrated circuit, comprising the steps of:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25570790A JPH04133346A (en) | 1990-09-25 | 1990-09-25 | Hybrid integrated circuit and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25570790A JPH04133346A (en) | 1990-09-25 | 1990-09-25 | Hybrid integrated circuit and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04133346A true JPH04133346A (en) | 1992-05-07 |
Family
ID=17282523
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25570790A Pending JPH04133346A (en) | 1990-09-25 | 1990-09-25 | Hybrid integrated circuit and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04133346A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003005445A1 (en) * | 2001-07-04 | 2003-01-16 | Sony Corporation | Semiconductor device and semiconductor module |
-
1990
- 1990-09-25 JP JP25570790A patent/JPH04133346A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003005445A1 (en) * | 2001-07-04 | 2003-01-16 | Sony Corporation | Semiconductor device and semiconductor module |
| US6992395B2 (en) | 2001-07-04 | 2006-01-31 | Sony Corporation | Semiconductor device and semiconductor module having external electrodes on an outer periphery |
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