JPH04133241A - Field electron emitting element - Google Patents

Field electron emitting element

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Publication number
JPH04133241A
JPH04133241A JP2254775A JP25477590A JPH04133241A JP H04133241 A JPH04133241 A JP H04133241A JP 2254775 A JP2254775 A JP 2254775A JP 25477590 A JP25477590 A JP 25477590A JP H04133241 A JPH04133241 A JP H04133241A
Authority
JP
Japan
Prior art keywords
projection
gate electrode
cone
emission device
current
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2254775A
Other languages
Japanese (ja)
Other versions
JP2946706B2 (en
Inventor
Hiroshi Komatsu
博志 小松
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
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Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP25477590A priority Critical patent/JP2946706B2/en
Publication of JPH04133241A publication Critical patent/JPH04133241A/en
Application granted granted Critical
Publication of JP2946706B2 publication Critical patent/JP2946706B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Abstract

PURPOSE:To lessen dispersion of electric characteristics over a large area, enlarge the current gain, and enhance the power efficiency by forming a conical projection on the surface of a flat base board, and allowing the tip of this projection to protrude from the assumed plane which is bounded by the peripheries of an opening provided in a gate electrode. CONSTITUTION:A conical projection 14 is formed by etching of a Si base board 11 having azimuth of (100) plane, wherein the height is 12000Angstrom and the appex angle in e cross-section is approx. 90deg. An insulative layer 12 shall preferably have a film thickness smaller than this height of projection, for ex. 6000Angstrom , and the DC dielectric breakdown voltage preferably be large, for ex. over 6X10<6>V/cm. Of a gate electrode 13, the conical electrode part 16 is formed in parallel with the wall surface of the projection 14. This electric field electron emitting element thus obtained has an anode current of 3muA with the gate voltage 100V when it is operated under a vacuum of 1X10<-7>Torr, and dispersion of the cathode current on a 3-inch Si base board is less than 10%. The current gain (I6k/I9k ratio) is 100.

Description

【発明の詳細な説明】 [産業上の利用分野コ [発明が解決しようとするfil!] しかし前述した従来技術による電界電子放出六本発明は
発光型表示装置、プリンタヘッド、電子は、以下に述べ
るいくつかの問題点を有していた、すなわち、 ■ 電気的特性のばらつきが大きν\ ・電子放出のしきい値電圧 ・電流密度 一電圧一電流特性など ■ 電流利得(I*v/I−比)が小さく、電力効率が
但い ■については、大きな平面基板上(こ−面シこわたって
踵状突起を形成する場合符【こ!I舊である。
[Detailed Description of the Invention] [Industrial Application Field] ] However, the above-mentioned conventional field electron emission device, light-emitting display device, printer head, and electronic device according to the present invention had several problems as described below. \ -Threshold voltage for electron emission, current density-voltage-current characteristics, etc.■ The current gain (I*v/I-ratio) is small and the power efficiency is low. When a heel-like process is formed across the whole body, this is the sign.

その理由の一つは、踵状突起をスパッタあるν\lよ蒸
着などの方法で作るためである。すなわち、線源からみ
ると基板の位置によって異なった仰角カー生じ、基板の
中心付近と周辺付近で畑状突起の鍜軸の基板面に対する
角度が異なるからである。また、別の理由としては、ゲ
ート電極の開口のためのエツチング工程において、間口
径im Iiらつき力5生じ、踵状突起の先端とゲート
電極との距離1カタばらつくからである。
One of the reasons for this is that the heel-like protrusion is formed by a method such as sputtering or vapor deposition. That is, when viewed from the radiation source, different elevation angles occur depending on the position of the substrate, and the angle of the axis of the field-like protrusion with respect to the substrate surface differs near the center and near the periphery of the substrate. Another reason is that in the etching process for opening the gate electrode, a fluctuation force 5 occurs in the diameter im Ii, and the distance between the tip of the heel-like projection and the gate electrode varies by 1 katak.

■についてはカソード、ゲート、及びアノードの幾何学
的な構造上、カソードである踵状突起からアノードに流
れるよりも踵状突起からゲートに電子が流れ易いからで
ある。
Regarding (2), this is because due to the geometric structures of the cathode, gate, and anode, electrons flow more easily from the heel-like protrusion to the gate than from the heel-like protrusion, which is the cathode, to the anode.

そこで、本発明は上述した従来技術の問題点を克服する
ためのもので、その目的とするところは、大面積にわた
って電圧・電流密度・しきい値電圧等の電気的特性のば
らつきが小さく、かつ電流利得(I −m/ ニー*比
)が大きく電力効率が高い電界電子放出素子を提供する
ところにある。
SUMMARY OF THE INVENTION Therefore, the present invention is intended to overcome the problems of the prior art described above, and its purpose is to reduce variations in electrical characteristics such as voltage, current density, and threshold voltage over a large area, and to The object of the present invention is to provide a field emission device with a large current gain (I-m/knee* ratio) and high power efficiency.

[課題を解決するための手段] 本発明の電界電子放出素子は、平面基板と、前記平面基
板の表面に形成された錘状突起と、前記平面基板の表面
に形成された絶縁層であって前記錘状突起の近傍で開口
された絶縁層と、前記絶縁層の表面に形成されたゲート
電極であって前記踵状突起の近傍で開口されたゲート電
極と、を有する電界電子放出素子に放て、前記錘状突起
の突起先端部が前記ゲート電極の開口部周辺部で概略規
定される仮想平面から上に突き出た構造を有することを
特徴とする。
[Means for Solving the Problems] A field emission device of the present invention comprises a flat substrate, a cone-shaped protrusion formed on the surface of the flat substrate, and an insulating layer formed on the surface of the flat substrate. A field emission device having an insulating layer having an opening in the vicinity of the cone-shaped projection, and a gate electrode formed on the surface of the insulating layer and having an opening in the vicinity of the heel-shaped projection. The tip of the cone-shaped projection has a structure that projects upward from a virtual plane roughly defined by the periphery of the opening of the gate electrode.

〔実施例] 本発明の電界電子放出素子及びその製造方法を実j[に
基づき、さらに詳細に説明する。但し、本発明は以下の
実施例に限定されるものではない。
[Example] The field emission device of the present invention and the method for manufacturing the same will be explained in more detail based on a practical example. However, the present invention is not limited to the following examples.

(実71例1〉 第1図(a)および(b)は本発明の電界電子放出素子
を説明するためのもので、電界電子放出素子の概略平面
図及びA−A’線に沿った概略断面図をそれぞれ示して
いる。
(Example 1 of 71) Figures 1 (a) and (b) are for explaining the field electron emission device of the present invention, and are a schematic plan view of the field electron emission device and a schematic diagram along the line A-A'. A cross-sectional view is shown in each case.

この電界電子放出素子は、単結晶のシリコン基板11の
表面に円!!型の畑状突起14をもち、錘状突起部を除
くシリコン基板表面に二酸化シリコン薄膜よりなる絶縁
層12をもち、絶縁層120表面にモリブテン(M o
 )金属薄膜よりなるゲート電極13をもつ構造であり
、該踵状突起14の突起先端部15がグー)1極13の
開口部周辺部で概略規定される仮想平面B−B’から上
に突き出た構造を有してしする。
This field emission device has a circle on the surface of a single-crystal silicon substrate 11! ! The surface of the silicon substrate except for the cone-shaped projections has an insulating layer 12 made of a silicon dioxide thin film, and the surface of the insulating layer 120 is made of molybdenum (Mo).
) It has a structure with a gate electrode 13 made of a metal thin film, and the protrusion tip 15 of the heel-like protrusion 14 protrudes upward from the virtual plane B-B' roughly defined by the periphery of the opening of the one pole 13. It has a similar structure.

シリコン基板11は(100)面方位をもち、キャリア
濃度は約I X 10”am−”である、ただし、低抵
抗化のためにシリコン基板全体もしくは錘状突起付近に
不純物を1xlO”am−”程度ドーピングしたものを
用いてもよい、fm状突起14はシリコン基板11をエ
ツチングして作製され、その高さは12000人、断面
の頂角は約90゜である、絶縁層22は膜厚が踵状突起
の高さより小さい方が好ましく、6000Aであり、直
流の絶縁破壊電圧が6X10”V/cm以上と大きいも
のが望ましい、ゲート電極13のうち、煙状電極部16
は踵状突起14の壁面に平行に形成されている。
The silicon substrate 11 has a (100) plane orientation, and the carrier concentration is about I x 10"am-".However, in order to lower the resistance, impurities are added to the entire silicon substrate or near the cone-like protrusions to 1xlO"am-" The fm-shaped protrusion 14 is made by etching the silicon substrate 11, and its height is 12,000 mm, and the apex angle of the cross section is about 90°.The insulating layer 22 has a film thickness of The smoke-shaped electrode portion 16 of the gate electrode 13 is preferably smaller than the height of the heel-like protrusion, is 6000A, and has a DC breakdown voltage of 6×10”V/cm or more.
is formed parallel to the wall surface of the heel-like process 14.

本実施例の電界電子放出素子は、約1xlO−’Tor
rの真空下で動作させたとき、 ■ ゲート電圧が100vにおいてアノード電流は3μ
Aであった。また、 ■ 3インチシリコン1&上でのカソード電流のばらつ
きは10%以下であった。また、■ 電流利得(I −
b/ 工s−比)は100であった。
The field emission device of this example has approximately 1xlO-'Tor
When operated in a vacuum of r, the anode current is 3μ when the gate voltage is 100V.
It was A. In addition, (1) The variation in cathode current on 3-inch silicon 1& was 10% or less. Also, ■ current gain (I −
b/engine s-ratio) was 100.

(実施例2) M2図は本発明の第二の実施例を説明するもので、シリ
コン単結晶基板表面に形成した電界電子放出素子の概略
断面図である。この電界電子放出素子は− キャリア温
度がlX10”cm″事の(100)面n型シリコン単
結晶基板よりなる第一電極21の表面に、シリコンjI
IN晶基板の一部からなる円錐状の錘状突起24と、シ
リコン酸化膜(SiOtl膜)からなる絶縁層22を設
け、ざらに絶a!22の表面にクロム(Or)からなる
ゲート電極23を設けた構造である。
(Example 2) Figure M2 explains a second example of the present invention, and is a schematic cross-sectional view of a field emission device formed on the surface of a silicon single crystal substrate. This field emission device has silicon jI on the surface of a first electrode 21 made of a (100) plane n-type silicon single crystal substrate with a carrier temperature of lx10"cm".
A conical cone-shaped protrusion 24 made of a part of the IN crystal substrate and an insulating layer 22 made of a silicon oxide film (SiOtl film) are provided, and the roughness is extremely high! In this structure, a gate electrode 23 made of chromium (Or) is provided on the surface of the gate electrode 22.

ゲート電極23は錘状突起24の上部において円型に開
口しており、水上突起24の突起先端部はゲート電極の
開口部周辺部で概略規定される仮想平面から上に突き出
ている。製造方法は当社特許[11平01−32762
1に記載されている方法に準じた製造方法を用いたが、
その製造方法中、バーズビーク状の5102薄膜形成後
、絶縁層23を形成する前に、5iOpHiiをエツチ
ングする工程を加え、錘状突起24を突き出させた。
The gate electrode 23 has a circular opening at the top of the cone-shaped projection 24, and the tip of the above-water projection 24 projects upward from a virtual plane roughly defined by the periphery of the opening of the gate electrode. The manufacturing method is based on our patent [11 Hei 01-32762
A manufacturing method similar to that described in 1 was used, but
In the manufacturing method, after forming the bird's beak-shaped 5102 thin film and before forming the insulating layer 23, a step of etching 5iOpHii was added to make the cone-shaped protrusion 24 protrude.

本実施例の電界電子放出素子は、約1×10りTorr
の真空下で動作させたとき、 ■ 3インチシリコン基板上でのカソード電流のばらつ
きは10%以下であった。また、■ 電流利得(工、皺
/Igk比)は100であった。
The field electron emission device of this example has a Torr of approximately 1×10 Torr.
(1) The variation in cathode current on a 3-inch silicon substrate was less than 10%. In addition, the current gain (Igk ratio) was 100.

(比較例1) 当社出願の特許(特願平02−109203)に記載の
構造と同様な構造を有する電界電子放出素子を試作して
、電気的特性のばらつきと利得を測定したところ下記の
結果を辱た。
(Comparative Example 1) A field emission device having a structure similar to that described in our patent application (Japanese Patent Application No. 02-109203) was fabricated as a prototype, and the variation in electrical characteristics and gain were measured. The following results were obtained. humiliated.

■ ■ 3インチシリコン[E上でのカソード電流のばらつき 
・・・ 10%以下 電流利得(X ah/ 工□比) −・・ 30(比較
例2) 当社出願の特許(特願平0l−327621)に記載の
構造と同様な構造を有する電界電子放出素子を試作・し
て、電気的特性のばらつきと利得を測定したところ下記
の結果を得た。
■ ■ Cathode current variation on 3-inch silicon [E
... 10% or less current gain (X ah / engineering ratio) - ... 30 (Comparative Example 2) Field electron emission having a structure similar to the structure described in our patent application (Japanese Patent Application No. 01-327621) When we prototyped a device and measured the variation in electrical characteristics and gain, we obtained the following results.

的特性を第工表で比較した0本発明の電界電子放出素子
が優れていることがわかった。
The field emission device of the present invention was found to be superior when its characteristics were compared using Table 1.

第1表 ■ 3インチシリコン基板上でのカソード電流のばらつ
き ・・・ 10%以下 ■ 電流利得(I−w/工、に比) ・・・   30 (比較例3) スピンドらの電界電子放出素子と同様な構造の電界電子
放出素子を試作して、電気的特性のばらつきと利得を測
定したところ下記の結果を得た。
Table 1 ■ Variation in cathode current on 3-inch silicon substrate ... 10% or less ■ Current gain (I-w/engine, relative to) ... 30 (Comparative example 3) Field emission device by Spind et al. When a field emission device with a similar structure was fabricated as a prototype and the variation in electrical characteristics and gain were measured, the following results were obtained.

■ 3インチシリコン基板上でのカソード電流のばらつ
き ・・・ 〜20% ■ 電流利得(工1に/工。k比) 本実施例及び比較例の電界電子放出素子の電気この理由
は以下のようなモデルを考えると理解できた。第3図(
a)及び(b)を用いて詳しく説明する。第3図(a)
は実施例1の電界電子放出素子の場合であり、第3図(
b)は比較例(1)の電界電子放出素子の場合である。
■ Variation in cathode current on a 3-inch silicon substrate ... ~20% ■ Current gain (1 to 1/k ratio) The reason for this is as follows: I was able to understand this by considering a model. Figure 3 (
This will be explained in detail using a) and (b). Figure 3(a)
is the case of the field emission device of Example 1, and Fig. 3 (
b) is the case of the field emission device of Comparative Example (1).

第3図を見てわかるように、本発明(実施例1)の電界
電子放出素子の方が従来(比較例1)の電界電子放出素
子より、幾何学的に見て、カソードである錘状突起34
からの放出電子がゲート電極33にトラップされずにア
ノード35に到達し易いことが推測できる。
As can be seen from FIG. 3, the field electron emission device of the present invention (Example 1) has a cone-shaped cathode, compared to the conventional field emission device (Comparative Example 1). Protrusion 34
It can be inferred that the emitted electrons easily reach the anode 35 without being trapped by the gate electrode 33.

(実施信3) 第4図(a)〜(f)は実施例1で述べた電界電子放出
素子の製造方法を説明するもので、ポイントとなる製造
工程終了後のシリコン基板の概略断面図を示したもので
ある。
(Working report 3) Figures 4 (a) to (f) explain the method for manufacturing the field electron emission device described in Example 1, and show a schematic cross-sectional view of the silicon substrate after the manufacturing process is completed, which is the key point. This is what is shown.

第4図に基づき本発明の電界電子放出素子の製造工程を
説明する。まず、直径3インチ、厚さ400μm(+)
n型シリコン慇板41の表面にKOH系エツチング液を
用いたシリコンの異方性エツチングによって錘状突起4
4を形成する。 (第4図(a))、  エツチングマ
スクには常圧CVD法によって堆積した二酸化シリコン
薄膜を0. 5μm口に加工したものを用い、異方性エ
ツチング液の組成としてKOH:  IPA:  H2
0=1:  2:  8(wt比)を用い、液温度を3
0°Cとした。約60分のエツチングによって、高さ1
2000人、頂角90°のほぼ円錐型の錘状突起が作製
される。
The manufacturing process of the field electron emission device of the present invention will be explained based on FIG. First, the diameter is 3 inches and the thickness is 400 μm (+)
The cone-shaped projections 4 are formed on the surface of the n-type silicon plate 41 by anisotropic etching of silicon using a KOH-based etching solution.
form 4. (FIG. 4(a)) The etching mask contains a silicon dioxide thin film deposited by atmospheric pressure CVD. The composition of the anisotropic etching solution was KOH: IPA: H2 using a 5 μm-sized one.
Using 0 = 1: 2: 8 (wt ratio), the liquid temperature was
The temperature was set to 0°C. By etching for about 60 minutes, the height is 1.
2,000 people, an almost conical cone-shaped process with an apex angle of 90° is produced.

つぎに、錘状突起を含むシリコン基板41の表面全体に
、高周浪スパッタ法によって二酸化シリコン薄膜よりな
る絶縁層42及びMo薄膜よりなるゲート電極43を連
続的に堆積するく同図(b))、絶縁層42の膜厚は約
600OAであるが、錘状突起44の斜面ではやや薄く
約5000人である。これはスパッタ粒子がシリコン基
板面に垂直な方向性をもっためである。ゲート電極43
の膜厚は約3000人である。つぎに、ゲート電極43
の表面にフォトレジスト薄膜49をスピンコード法によ
って塗布し形成する(同図(C))、  フォトレジス
ト薄膜は塗布時に粘性が低いため、突起の上部では膜厚
が薄くなる性貢がある。したがってフォトレジスト薄膜
49の膜厚は錘状突起44の上部では約1500人、平
面部では約13000人となる。つぎに、フォトレジス
ト薄膜49及びゲートT4極43をドライエツチングし
、錘状突起44の上部の絶縁層42を露出させる(同図
(d))、  ドライエツチング装置にはマイクロ波プ
ラズマエツチング装置を用い、エツチングガスCFs1
02の混合ガスを用いる。エツチングのはじめは、Oe
ガスによってフォトレジスト薄膜49が表面より均一に
アッシングされていく。約1500人のフォトレジスト
4WA49がエツチングされたところで、睡状突起44
上部のMo薄膜よりなるゲート電極43の一部が表面に
現れる。
Next, an insulating layer 42 made of a silicon dioxide thin film and a gate electrode 43 made of a Mo thin film are successively deposited on the entire surface of the silicon substrate 41 including the cone-shaped projections by high frequency sputtering. ), the thickness of the insulating layer 42 is about 600 OA, but on the slope of the cone-shaped projection 44 it is slightly thinner, about 5000 OA. This is because the sputtered particles have a directionality perpendicular to the silicon substrate surface. Gate electrode 43
The film thickness is approximately 3,000 people. Next, the gate electrode 43
A photoresist thin film 49 is applied on the surface of the protrusion by a spin code method (FIG. 4(C)). Since the photoresist thin film has low viscosity when applied, the film tends to be thinner at the top of the protrusion. Therefore, the thickness of the photoresist thin film 49 is about 1,500 on the top of the cone-shaped projection 44 and about 13,000 on the flat surface. Next, the photoresist thin film 49 and the gate T4 pole 43 are dry-etched to expose the insulating layer 42 above the cone-shaped projection 44 (FIG. 4(d)). A microwave plasma etching device is used as the dry etching device. , etching gas CFs1
02 mixed gas is used. The beginning of etching is Oe
The photoresist thin film 49 is uniformly ashed from the surface by the gas. After approximately 1,500 photoresists 4WA49 were etched, the sleep protrusions 44 were etched.
A part of the upper gate electrode 43 made of the Mo thin film appears on the surface.

表面に現れたMo薄膜はCF4ガスによってエツチング
され、同時にフォトレジスト薄@49もエツチングが進
行していく、CF1102比を適当に選ぶことによって
Mo薄膜とフォトレジスト薄膜のエツチング速度を同等
にすることが可能であり、エツチング時間を適度に設定
することで、第4図(d)のような断面のエツチング形
状を得ることが可能である0本実施例では、CF410
2=30/200とし、30分間のドライエツチングを
行った。このときゲート電極43の電極開口47の直径
は約16000人であった。つぎに、HF系エツチング
液によって開口部の絶縁層42をエツチング除去し、錘
状突起44を露出させる(同図(e))、HF系エツチ
ング液二酸化シリコン薄膜が溶け、Mo薄膜やシリコン
基板が溶けないものを選ぶ1ggえばHFバッファエツ
チング液などが好ましい、i&後にフォトレジスト薄膜
49を剥N液によって除去する(同図(f))。
The Mo thin film appearing on the surface is etched by the CF4 gas, and at the same time the photoresist thin film @49 is also etched.By appropriately selecting the CF1102 ratio, the etching speed of the Mo thin film and the photoresist thin film can be made equal. By setting the etching time appropriately, it is possible to obtain an etched cross-sectional shape as shown in FIG. 4(d).
2=30/200, and dry etching was performed for 30 minutes. At this time, the diameter of the electrode opening 47 of the gate electrode 43 was about 16,000. Next, the insulating layer 42 at the opening is etched away using an HF-based etching solution to expose the cone-shaped protrusion 44 (see (e) in the same figure).The HF-based etching solution dissolves the silicon dioxide thin film and removes the Mo thin film and silicon substrate. It is preferable to use an etchant that does not dissolve, such as an HF buffer etching solution.After i&, the photoresist thin film 49 is removed using a stripping solution (FIG. 4(f)).

上述した製造方法によって、錘状突起44がゲート電極
43の開口部周辺部で概略規定される仮想平Iから約2
000A上に突き出た電界電子放出素子を作製すること
ができた。
By the above-described manufacturing method, the cone-like protrusion 44 is approximately 2.0 mm from the virtual plane I roughly defined around the opening of the gate electrode 43.
A field emission device protruding above 000A could be manufactured.

本実施側による電界電子放出素子の製造方法においては
、煙先端45とゲート電極の踵状電極部46との距離は
、錘状突起44の斜面に形成された絶縁層42の膜厚に
よって法定される。従って、i!縁層42の膜厚の均−
牲をよく制御すれば、ゲ−トしきい値電圧の均一な電界
電子放出索子が得られることになる。
In the method for manufacturing a field emission device according to the present embodiment, the distance between the smoke tip 45 and the heel-shaped electrode portion 46 of the gate electrode is determined by the thickness of the insulating layer 42 formed on the slope of the cone-shaped protrusion 44. Ru. Therefore, i! Evenness of the film thickness of the edge layer 42
If the cost is well controlled, a field emission probe with uniform gate threshold voltage can be obtained.

なお、錘状突起24の突起部分に仕事間数の小さいBa
Oのような誘電体薄膜を形成するとゲートしきい値を低
下できる。
It should be noted that Ba, which has a small number of working spaces, is placed on the protruding portion of the cone-like protrusion 24.
Forming a dielectric thin film such as O can lower the gate threshold.

以上三つの実!l倒に放て平面!E !H,にシリコン
基板を用いたが、本発明はこれにとられれることなく、
他の結晶性基板やガラス基板などの絶縁性基板を利用す
ることも可能である。またゲート12を極や絶&を膜に
ついても同様である。
These three fruits! Throw it flat! E! Although a silicon substrate was used for H, the present invention is not limited to this.
It is also possible to use other insulating substrates such as crystalline substrates and glass substrates. The same applies to the gate 12 as a pole or as a film.

[発明の効果コ 本発明の電界電子放出素子は、平面基板と、前記平面基
板の表面に形成された雌状突起と、前記平面基板の表面
に形成された絶縁層であって前記錘状突起の近傍で開口
された絶縁層と、前記絶縁層の表面に形成されたゲート
電極であって前記錘状突起の近傍で開口されたゲート電
極と、を有する電界電子放出素子に放て、前記錘状突起
の突起先端部が前記ゲート電極の開口部周辺部で概略規
定される仮想平面から上に笑き出た構造を有するために
、大面積にわた)て放出電子のしきい値電圧・電流密度
・電圧−電流特性等の電気的特性のばらつきが小さく、
かつ利得(工、i/I−比)が大きく電力効率が高い電
界電子放出素子を提供することができるという効果があ
る。
[Effects of the Invention] The field emission device of the present invention includes a flat substrate, a female-shaped projection formed on the surface of the flat substrate, and an insulating layer formed on the surface of the flat substrate, and the conical projection formed on the surface of the flat substrate. and a gate electrode formed on the surface of the insulating layer and having an opening in the vicinity of the cone-shaped protrusion. Because the tip of the protrusion has a structure that protrudes upward from the virtual plane roughly defined by the periphery of the opening of the gate electrode, the threshold voltage and current of emitted electrons are reduced over a large area. Small variations in electrical characteristics such as density and voltage-current characteristics,
Moreover, it is possible to provide a field emission device with a large gain (i/I-ratio) and high power efficiency.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)及び(b)は本発明の実施例1に於る電界
電子放出素子の概略平面図及びA−A’線に沿った概略
断面図である。 第2図は本発明の第二の実施例を説明するもので、シリ
コン単結晶基板表面に形成した電界電子放出素子の既略
断面図である。 第3図(a)及び(b)は本発明の電界電子放出索子と
従来の電界電子放出素子の電界電子の放出の様子をモデ
ル化した図である。 第4図(a)〜(f)は本発明の電界電子放出素子の!
!遣方法を説明するための図である。 第6図は従来の電界電子放出素子の断面図であシリコン
基板 1色 縁 層 ゲート電極 錘状突起 突起先端部 踵状電極部 1を極間口 錘軸 シリコン基板 絶縁層 ゲートを極 雌状突起 シリコン基板 絶縁層 ゲート電極 錘状突起 アノード 放出電子の軌跡 シリコン基板 系色縁 層 ゲート電極 錘状突起 突起先端部 踵状電極部 電極開口 フォトレジスト薄膜 シリコン基板 絶縁層 ゲート電極 雌状突起 以上 出願人 セイコーエプソン株式会社 代理人 弁理士 鈴木喜三部 @1名 匈 〈・ メ二 l
FIGS. 1(a) and 1(b) are a schematic plan view and a schematic cross-sectional view taken along the line AA' of a field emission device according to Example 1 of the present invention. FIG. 2 explains a second embodiment of the present invention, and is a schematic cross-sectional view of a field emission device formed on the surface of a silicon single crystal substrate. FIGS. 3(a) and 3(b) are modeled views of the field electron emission behavior of the field electron emission probe of the present invention and the conventional field electron emission device. FIGS. 4(a) to 4(f) show the field electron emission device of the present invention!
! FIG. FIG. 6 is a cross-sectional view of a conventional field emission device. Substrate Insulating layer Gate electrode cone-shaped protrusion Anode Trajectory of emitted electrons Silicon substrate system Color Edge layer Gate electrode cone-shaped protrusion Tip part Heel-shaped electrode part Electrode opening Photoresist thin film Silicon substrate Insulating layer Gate electrode Female protrusion Applicant: Seiko Epson Agent Co., Ltd. Patent Attorney Kizobe Suzuki

Claims (1)

【特許請求の範囲】[Claims] 平面基板と、前記平面基板の表面に形成された錘状突起
と、前記平面基板の表面に形成された絶縁層であって前
記錘状突起の近傍で開口された絶縁層と、前記絶縁層の
表面に形成されたゲート電極であって前記錘状突起の近
傍で開口されたゲート電極と、を有する電界電子放出素
子に於て、前記錘状突起の突起先端部が前記ゲート電極
の開口部周辺部で概略規定される仮想平面から上に突き
出た構造を有することを特徴とする電界電子放出素子
a flat substrate, a cone-shaped protrusion formed on the surface of the flat substrate, an insulating layer formed on the surface of the flat substrate and having an opening near the cone-shaped protrusion, and In a field electron emission device having a gate electrode formed on the surface and having an opening near the cone-shaped projection, the tip of the cone-shaped projection is located near the opening of the gate electrode. A field emission device characterized by having a structure protruding upward from a virtual plane roughly defined by
JP25477590A 1990-09-25 1990-09-25 Field emission device Expired - Lifetime JP2946706B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25477590A JP2946706B2 (en) 1990-09-25 1990-09-25 Field emission device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25477590A JP2946706B2 (en) 1990-09-25 1990-09-25 Field emission device

Publications (2)

Publication Number Publication Date
JPH04133241A true JPH04133241A (en) 1992-05-07
JP2946706B2 JP2946706B2 (en) 1999-09-06

Family

ID=17269713

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25477590A Expired - Lifetime JP2946706B2 (en) 1990-09-25 1990-09-25 Field emission device

Country Status (1)

Country Link
JP (1) JP2946706B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08138530A (en) * 1994-11-16 1996-05-31 Nec Corp Field emission electron gun and manufacture thereof
US5965977A (en) * 1996-03-28 1999-10-12 Nec Corporation Apparatus and method for light emitting and cold cathode used therefor
US6281621B1 (en) 1992-07-14 2001-08-28 Kabushiki Kaisha Toshiba Field emission cathode structure, method for production thereof, and flat panel display device using same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6281621B1 (en) 1992-07-14 2001-08-28 Kabushiki Kaisha Toshiba Field emission cathode structure, method for production thereof, and flat panel display device using same
JPH08138530A (en) * 1994-11-16 1996-05-31 Nec Corp Field emission electron gun and manufacture thereof
US5965977A (en) * 1996-03-28 1999-10-12 Nec Corporation Apparatus and method for light emitting and cold cathode used therefor

Also Published As

Publication number Publication date
JP2946706B2 (en) 1999-09-06

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